diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/quick | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/quick')
20 files changed, 13403 insertions, 12711 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index b46274bd4..676e01409 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,133 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961841 # Number of seconds simulated -sim_ticks 1961841175000 # Number of ticks simulated -final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961837 # Number of seconds simulated +sim_ticks 1961837389000 # Number of ticks simulated +final_tick 1961837389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1272238 # Simulator instruction rate (inst/s) -host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42053157352 # Simulator tick rate (ticks/s) -host_mem_usage 308880 # Number of bytes of host memory used -host_seconds 46.65 # Real time elapsed on the host -sim_insts 59351715 # Number of instructions simulated -sim_ops 59351715 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24914752 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 32192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 287808 # Number of bytes read from this memory -system.physmem.bytes_read::total 28716928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 32192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7746368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7746368 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389293 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4497 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121037 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121037 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12699678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 146703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14637744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3948519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12699678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28716928 # Total number of bytes read from memory -system.physmem.bytesWritten 7746368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28019 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27836 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27466 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27826 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28236 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7222 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7890 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1961833946000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448702 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121037 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +host_inst_rate 1325125 # Simulator instruction rate (inst/s) +host_op_rate 1325124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42668778131 # Simulator tick rate (ticks/s) +host_mem_usage 308960 # Number of bytes of host memory used +host_seconds 45.98 # Real time elapsed on the host +sim_insts 60926932 # Number of instructions simulated +sim_ops 60926932 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 833280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 338432 # Number of bytes read from this memory +system.physmem.bytes_read::total 28741376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7742464 # Number of bytes written to this memory +system.physmem.bytes_written::total 7742464 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449084 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120976 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120976 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12685610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 172508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14650234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3946537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12685610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 172508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18596771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449084 # Number of read requests accepted +system.physmem.writeReqs 120976 # Number of write requests accepted +system.physmem.readBursts 449084 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120976 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28737920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3456 # Total number of bytes read from write queue +system.physmem.bytesWritten 7741568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28741376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7742464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 54 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7077 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28167 # Per bank write bursts +system.physmem.perBankRdBursts::1 28458 # Per bank write bursts +system.physmem.perBankRdBursts::2 28055 # Per bank write bursts +system.physmem.perBankRdBursts::3 27665 # Per bank write bursts +system.physmem.perBankRdBursts::4 27762 # Per bank write bursts +system.physmem.perBankRdBursts::5 27792 # Per bank write bursts +system.physmem.perBankRdBursts::6 28261 # Per bank write bursts +system.physmem.perBankRdBursts::7 27879 # Per bank write bursts +system.physmem.perBankRdBursts::8 28077 # Per bank write bursts +system.physmem.perBankRdBursts::9 27735 # Per bank write bursts +system.physmem.perBankRdBursts::10 27671 # Per bank write bursts +system.physmem.perBankRdBursts::11 28135 # Per bank write bursts +system.physmem.perBankRdBursts::12 28173 # Per bank write bursts +system.physmem.perBankRdBursts::13 28505 # Per bank write bursts +system.physmem.perBankRdBursts::14 28655 # Per bank write bursts +system.physmem.perBankRdBursts::15 28040 # Per bank write bursts +system.physmem.perBankWrBursts::0 7931 # Per bank write bursts +system.physmem.perBankWrBursts::1 7869 # Per bank write bursts +system.physmem.perBankWrBursts::2 7539 # Per bank write bursts +system.physmem.perBankWrBursts::3 7157 # Per bank write bursts +system.physmem.perBankWrBursts::4 7275 # Per bank write bursts +system.physmem.perBankWrBursts::5 7313 # Per bank write bursts +system.physmem.perBankWrBursts::6 7748 # Per bank write bursts +system.physmem.perBankWrBursts::7 7258 # Per bank write bursts +system.physmem.perBankWrBursts::8 7316 # Per bank write bursts +system.physmem.perBankWrBursts::9 7114 # Per bank write bursts +system.physmem.perBankWrBursts::10 7078 # Per bank write bursts +system.physmem.perBankWrBursts::11 7523 # Per bank write bursts +system.physmem.perBankWrBursts::12 7676 # Per bank write bursts +system.physmem.perBankWrBursts::13 8141 # Per bank write bursts +system.physmem.perBankWrBursts::14 8336 # Per bank write bursts +system.physmem.perBankWrBursts::15 7688 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1961830378000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 449084 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 120976 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 409885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -139,382 +141,444 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 922.589599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.543369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2381.494153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13878 35.12% 35.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6056 15.33% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3741 9.47% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2391 6.05% 65.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1744 4.41% 70.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1425 3.61% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1039 2.63% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 750 1.90% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 668 1.69% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 592 1.50% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 528 1.34% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 459 1.16% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 301 0.76% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 245 0.62% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 187 0.47% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 264 0.67% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 137 0.35% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 111 0.28% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 92 0.23% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 96 0.24% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 88 0.22% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 105 0.27% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1100 2.78% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 187 0.47% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 132 0.33% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.22% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 54 0.14% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 43 0.11% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 23 0.06% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 21 0.05% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 20 0.05% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 29 0.07% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.03% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 14 0.04% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 4 0.01% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 6 0.02% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.00% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 4 0.01% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 3 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.01% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.01% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 6 0.02% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2432 6.15% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 3 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.61% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 10 0.03% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 6 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 6 0.02% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39515 # Bytes accessed per row activation -system.physmem.totQLat 3750140000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12006448750 # Sum of mem lat for all requests -system.physmem.totBusLat 2243145000 # Total cycles spent in databus access -system.physmem.totBankLat 6013163750 # Total cycles spent in bank access -system.physmem.avgQLat 8359.11 # Average queueing delay per request -system.physmem.avgBankLat 13403.42 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26762.53 # Average memory access latency -system.physmem.avgRdBW 14.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 49252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 740.628604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.502021 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1737.958624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 17638 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7255 14.73% 50.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4934 10.02% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2938 5.97% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1843 3.74% 70.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1471 2.99% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1137 2.31% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 871 1.77% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 749 1.52% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 678 1.38% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 696 1.41% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 441 0.90% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 346 0.70% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 295 0.60% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 325 0.66% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 366 0.74% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 215 0.44% 85.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 196 0.40% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 200 0.41% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 126 0.26% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 182 0.37% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 862 1.75% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 228 0.46% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 113 0.23% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 126 0.26% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 100 0.20% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.17% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 47 0.10% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 73 0.15% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 75 0.15% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 79 0.16% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 32 0.06% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 84 0.17% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 61 0.12% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 26 0.05% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 60 0.12% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 59 0.12% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 68 0.14% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 29 0.06% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 67 0.14% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 63 0.13% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 57 0.12% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 25 0.05% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 61 0.12% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 59 0.12% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 69 0.14% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 25 0.05% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 65 0.13% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.12% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 65 0.13% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 25 0.05% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 59 0.12% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 71 0.14% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 22 0.04% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 70 0.14% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 53 0.11% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 60 0.12% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 27 0.05% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 61 0.12% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 63 0.13% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 34 0.07% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 63 0.13% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 57 0.12% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 62 0.13% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 28 0.06% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 58 0.12% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 54 0.11% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.13% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 361 0.73% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 57 0.12% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 23 0.05% 95.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 53 0.11% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 23 0.05% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 58 0.12% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 23 0.05% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 51 0.10% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 22 0.04% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 54 0.11% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 39 0.08% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 55 0.11% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.04% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 55 0.11% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 27 0.05% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 50 0.10% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.04% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 54 0.11% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 25 0.05% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 53 0.11% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 22 0.04% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 52 0.11% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 23 0.05% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 54 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 23 0.05% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 52 0.11% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 23 0.05% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 54 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 23 0.05% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 53 0.11% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 23 0.05% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 55 0.11% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 26 0.05% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 57 0.12% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 421 0.85% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 12 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 6 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 40 0.08% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 179 0.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49252 # Bytes accessed per row activation +system.physmem.totQLat 6314810500 # Total ticks spent queuing +system.physmem.totMemAccLat 14686644250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2245150000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6126683750 # Total ticks spent accessing banks +system.physmem.avgQLat 14063.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13644.26 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32707.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.90 # Average write queue length over time -system.physmem.readRowHits 433153 # Number of row buffer hits during reads -system.physmem.writeRowHits 96987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes -system.physmem.avgGap 3443390.65 # Average gap between requests -system.membus.throughput 18639952 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292620 # Transaction distribution -system.membus.trans_dist::ReadResp 292620 # Transaction distribution -system.membus.trans_dist::WriteReq 12397 # Transaction distribution -system.membus.trans_dist::WriteResp 12397 # Transaction distribution -system.membus.trans_dist::Writeback 121037 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4186 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 858 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3168 # Transaction distribution -system.membus.trans_dist::ReadExReq 163944 # Transaction distribution -system.membus.trans_dist::ReadExResp 163855 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36531890 # Total data (bytes) -system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39129000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing +system.physmem.readRowHits 424855 # Number of row buffer hits during reads +system.physmem.writeRowHits 95885 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.26 # Row buffer hit rate for writes +system.physmem.avgGap 3441445.42 # Average gap between requests +system.physmem.pageHitRate 91.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18657286 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292799 # Transaction distribution +system.membus.trans_dist::ReadResp 292799 # Transaction distribution +system.membus.trans_dist::WriteReq 14111 # Transaction distribution +system.membus.trans_dist::WriteResp 14111 # Transaction distribution +system.membus.trans_dist::Writeback 120976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16467 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11554 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7080 # Transaction distribution +system.membus.trans_dist::ReadExReq 164905 # Transaction distribution +system.membus.trans_dist::ReadExResp 164053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1098283 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82306 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31175680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31257986 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36566146 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36566146 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43190000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1559666750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1566162500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3812357322 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3824002662 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376301000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 341780 # number of replacements -system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use -system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 28709 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1793292 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820882 # number of Writeback hits -system.l2c.Writeback_hits::total 820882 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 160 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 201 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 36 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 176285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7535 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183820 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 908184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 953017 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 79667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 36244 # number of demand (read+write) hits -system.l2c.demand_hits::total 1977112 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 908184 # number of overall hits -system.l2c.overall_hits::cpu0.data 953017 # number of overall hits -system.l2c.overall_hits::cpu1.inst 79667 # number of overall hits -system.l2c.overall_hits::cpu1.data 36244 # number of overall hits -system.l2c.overall_hits::total 1977112 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12993 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271572 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 511 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 178 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2440 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2923 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 33 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 106 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 118111 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 4331 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122442 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12993 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389683 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 511 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 4509 # number of demand (read+write) misses -system.l2c.demand_misses::total 407696 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12993 # number of overall misses -system.l2c.overall_misses::cpu0.data 389683 # number of overall misses -system.l2c.overall_misses::cpu1.inst 511 # number of overall misses -system.l2c.overall_misses::cpu1.data 4509 # number of overall misses -system.l2c.overall_misses::total 407696 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1030661993 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16900238244 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 41124000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 15490750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17987514987 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1078963 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 302487 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1381450 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 69997 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 92496 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 162493 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7866556623 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 326108488 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8192665111 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1030661993 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 24766794867 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 41124000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 341599238 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 26180180098 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1030661993 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 24766794867 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 41124000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 341599238 # number of overall miss cycles -system.l2c.overall_miss_latency::total 26180180098 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 921177 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1048304 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 80178 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 28887 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2078546 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820882 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820882 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2600 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 524 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3124 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 51 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 91 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 142 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 294396 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 11866 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306262 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 921177 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1342700 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 80178 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 40753 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2384808 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 921177 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1342700 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 80178 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 40753 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2384808 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014105 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259058 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006373 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006162 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137237 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938462 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.921756 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.935659 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.647059 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.802198 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.746479 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.401198 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.364992 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.399795 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290223 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006373 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.110642 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170955 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290223 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006373 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.110642 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170955 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79324.404910 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 62231.151385 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80477.495108 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 87026.685393 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 63057.888713 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.197951 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 626.267081 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 472.613753 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2121.121212 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1267.068493 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1532.952830 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66603.082041 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75296.349111 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 66910.578976 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64214.954520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64214.954520 # average overall miss latency +system.l2c.tags.replacements 342163 # number of replacements +system.l2c.tags.tagsinuse 65223.750612 # Cycle average of tags in use +system.l2c.tags.total_refs 2442870 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407350 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.996980 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8613125750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55316.946263 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4805.666179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4897.139369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 159.783438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 44.215363 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.844070 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.074724 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002438 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995235 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 684304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 664415 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 317640 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 107160 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1773519 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 792069 # number of Writeback hits +system.l2c.Writeback_hits::total 792069 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 188 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 543 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 129070 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 43262 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172332 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 684304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 793485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 317640 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 150422 # number of demand (read+write) hits +system.l2c.demand_hits::total 1945851 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 684304 # number of overall hits +system.l2c.overall_hits::cpu0.data 793485 # number of overall hits +system.l2c.overall_hits::cpu1.inst 317640 # number of overall hits +system.l2c.overall_hits::cpu1.data 150422 # number of overall hits +system.l2c.overall_hits::total 1945851 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13023 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271669 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285437 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2958 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1767 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4725 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 117954 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5056 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 123010 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13023 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 389623 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 5298 # number of demand (read+write) misses +system.l2c.demand_misses::total 408447 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13023 # number of overall misses +system.l2c.overall_misses::cpu0.data 389623 # number of overall misses +system.l2c.overall_misses::cpu1.inst 503 # number of overall misses +system.l2c.overall_misses::cpu1.data 5298 # number of overall misses +system.l2c.overall_misses::total 408447 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 996362741 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17553106248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 38541500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 19247750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18607258239 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1197458 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 10193060 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11390518 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 953959 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 139494 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1093453 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8253462501 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 385340740 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8638803241 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 996362741 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 25806568749 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 38541500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 404588490 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 27246061480 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 996362741 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 25806568749 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 38541500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 404588490 # number of overall miss cycles +system.l2c.overall_miss_latency::total 27246061480 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 697327 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 936084 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 318143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 107402 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2058956 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 792069 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 792069 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3146 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2310 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5456 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 956 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 949 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1905 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 247024 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 48318 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295342 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 697327 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1183108 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 318143 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 155720 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2354298 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 697327 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1183108 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 318143 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 155720 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2354298 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018676 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.290219 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002253 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138632 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940242 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764935 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.866019 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961297 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976818 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969029 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.477500 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.104640 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.416500 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018676 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.329322 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001581 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.034023 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173490 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018676 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.329322 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001581 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.034023 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173490 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76507.927590 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 64612.106085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76623.260437 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79536.157025 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 65188.669440 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 404.820149 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5768.568195 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2410.691640 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1038.040261 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 150.478964 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 592.336403 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69971.874638 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76214.545095 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 70228.463060 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76507.927590 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 66234.715992 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76623.260437 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76366.268403 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 66706.479617 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76507.927590 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 66234.715992 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76623.260437 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76366.268403 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 66706.479617 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,8 +587,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79517 # number of writebacks -system.l2c.writebacks::total 79517 # number of writebacks +system.l2c.writebacks::writebacks 79456 # number of writebacks +system.l2c.writebacks::total 79456 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits @@ -534,111 +598,111 @@ system.l2c.demand_mshr_hits::total 11 # nu system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12990 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271572 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 503 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 178 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285243 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2440 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 33 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 106 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 118111 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 4331 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122442 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12990 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 389683 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 503 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 4509 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407685 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12990 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 389683 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 503 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 4509 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407685 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 866381257 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13503893756 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 34165000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13232750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14417672763 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24556937 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4864483 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29421420 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 330033 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1060106 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6385916377 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 270944012 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6656860389 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 866381257 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 19889810133 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 34165000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 284176762 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21074533152 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 866381257 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 19889810133 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 34165000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 284176762 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21074533152 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373141500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17611000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390752500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1974248000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 499178500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2473426500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3347389500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 516789500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3864179000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259058 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006162 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.137232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938462 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.921756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.935659 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.647059 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.802198 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401198 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.364992 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.399795 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.170951 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.170951 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49724.911832 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74341.292135 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 50545.229026 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.318443 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10071.393375 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10065.487513 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13020 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271669 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 495 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 242 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285426 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2958 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1767 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4725 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 919 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 927 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1846 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 117954 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5056 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123010 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13020 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389623 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 495 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5298 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408436 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13020 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389623 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 495 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5298 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408436 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 832352009 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14156448252 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31778000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 16225250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15036803511 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29732955 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17692267 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47425222 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9190919 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9270927 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 18461846 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6776581499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 321158260 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7097739759 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 832352009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 20933029751 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 31778000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 337383510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22134543270 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 832352009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 20933029751 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 31778000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 337383510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22134543270 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373137500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17612000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1390749500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154547500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 679451000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2833998500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527685000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 697063000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4224748000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290219 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002253 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138627 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940242 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764935 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.866019 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961297 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969029 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477500 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.104640 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.416500 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.329322 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.034023 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173485 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.329322 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.034023 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173485 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52109.177904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67046.487603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52681.968395 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.708925 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.601585 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.084021 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54067.075692 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62559.226968 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 54367.458789 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57451.052944 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63520.225475 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57700.510194 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -649,39 +713,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.571330 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1754532770000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.571330 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035708 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035708 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21912883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21912883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10439154521 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10439154521 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10461067404 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10461067404 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10461067404 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10461067404 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12952701816 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12952701816 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12973950199 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12973950199 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12973950199 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12973950199 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -690,40 +754,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123106.084270 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251231.096482 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 274830 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 311722.704467 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 311722.704467 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 405757 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27442 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29467 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.014941 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.769878 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12655383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12655383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8289732904 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8289732904 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10802664199 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10802664199 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -732,14 +796,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -757,22 +821,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8725663 # DTB read hits +system.cpu0.dtb.read_hits 7530179 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 6139453 # DTB write hits +system.cpu0.dtb.write_hits 5118893 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 14865116 # DTB hits +system.cpu0.dtb.data_hits 12649072 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 4015307 # ITB hits +system.cpu0.itb.fetch_hits 3650586 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 4019291 # ITB accesses +system.cpu0.itb.fetch_accesses 3654570 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -785,55 +849,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923682350 # number of cpu cycles simulated +system.cpu0.numCycles 3923674778 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54601969 # Number of instructions committed -system.cpu0.committedOps 54601969 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50544405 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 297630 # Number of float alu accesses -system.cpu0.num_func_calls 1438477 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6291508 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50544405 # number of integer instructions -system.cpu0.num_fp_insts 297630 # number of float instructions -system.cpu0.num_int_register_reads 69247284 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37427910 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 145753 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 148838 # number of times the floating registers were written -system.cpu0.num_mem_refs 14912078 # number of memory refs -system.cpu0.num_load_insts 8757685 # Number of load instructions -system.cpu0.num_store_insts 6154393 # Number of store instructions -system.cpu0.num_idle_cycles 3674902109.498127 # Number of idle cycles -system.cpu0.num_busy_cycles 248780240.501873 # Number of busy cycles -system.cpu0.not_idle_fraction 0.063405 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.936595 # Percentage of idle cycles +system.cpu0.committedInsts 47959136 # Number of instructions committed +system.cpu0.committedOps 47959136 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44491652 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211334 # Number of float alu accesses +system.cpu0.num_func_calls 1203195 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5632072 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44491652 # number of integer instructions +system.cpu0.num_fp_insts 211334 # number of float instructions +system.cpu0.num_int_register_reads 61191395 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33136181 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 103249 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105046 # number of times the floating registers were written +system.cpu0.num_mem_refs 12690027 # number of memory refs +system.cpu0.num_load_insts 7557911 # Number of load instructions +system.cpu0.num_store_insts 5132116 # Number of store instructions +system.cpu0.num_idle_cycles 3700191977.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223482800.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.056958 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.943042 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 204697 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 73289 40.68% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104766 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 180167 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71920 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.35% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71914 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 145946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899196330000 96.81% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95025500 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 769055500 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5164500 0.00% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 61774827500 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961840403000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981321 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6812 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165228 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56779 40.23% 40.23% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.40% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81809 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141128 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56269 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55834 48.70% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114643 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902446374500 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95095000 0.00% 96.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 766988500 0.04% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 322426000 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58205747500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961836631500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991018 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.686425 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810060 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682492 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812333 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -865,37 +929,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3942 2.08% 2.13% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.16% # number of callpals executed -system.cpu0.kern.callpal::swpipl 173212 91.45% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 6702 3.54% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rti 4842 2.56% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 189397 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7440 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches +system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3084 2.06% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134176 89.75% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.48% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4411 2.95% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149500 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7010 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1368 -system.cpu0.kern.mode_good::user 1369 +system.cpu0.kern.mode_good::kernel 1372 +system.cpu0.kern.mode_good::user 1373 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.183871 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195720 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.310705 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958025785500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3814613000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327448 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958037655500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3798971500 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3943 # number of times the context was actually changed +system.cpu0.kern.swap_context 3085 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -927,47 +991,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 105075557 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2099191 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2099176 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12397 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12397 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 820882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4248 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 894 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 205232754 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.throughput 103908079 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2101783 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101768 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14111 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14111 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792069 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16689 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28302 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 338794 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297244 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1394675 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121086 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 636287 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 464415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5616463 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44628928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119461456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20361152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17008562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201460098 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201449794 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2400960 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4792055385 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4148559004 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3140628756 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 6195378103 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5519397625 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 360929992 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 206344318 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1431747492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 796288703 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1391673 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 53949 # Transaction distribution -system.iobus.trans_dist::WriteResp 53949 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1398649 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55663 # Transaction distribution +system.iobus.trans_dist::WriteResp 55663 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -979,11 +1043,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42620 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126072 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56040 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -995,12 +1059,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2730242 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 82306 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2743922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743922 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13365000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1022,59 +1086,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378297154 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377760199 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26795000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42664000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 920572 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53689788 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53689788 # number of overall hits -system.cpu0.icache.overall_hits::total 53689788 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 921200 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 921200 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 921200 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 921200 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921200 # number of overall misses -system.cpu0.icache.overall_misses::total 921200 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12937764004 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12937764004 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54610988 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54610988 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54610988 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54610988 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016868 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016868 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016868 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016868 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14044.468089 # average overall miss latency +system.cpu0.icache.tags.replacements 696718 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.401211 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47270807 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 697230 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.798011 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40083254250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.401211 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47270807 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47270807 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47270807 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47270807 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47270807 # number of overall hits +system.cpu0.icache.overall_hits::total 47270807 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 697348 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 697348 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 697348 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 697348 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 697348 # number of overall misses +system.cpu0.icache.overall_misses::total 697348 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9977651756 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9977651756 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47968155 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47968155 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47968155 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47968155 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014538 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014538 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014538 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014538 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14307.995084 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1083,112 +1147,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 921200 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 921200 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 921200 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 921200 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697348 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 697348 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 697348 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 697348 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1349865 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5646858 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177791 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177791 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 193304 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 193304 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 13154053 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13154053 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 13154053 # number of overall hits -system.cpu0.dcache.overall_hits::total 13154053 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1040730 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1040730 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297940 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16884 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16884 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1338670 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1338670 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1338670 # number of overall misses -system.cpu0.dcache.overall_misses::total 1338670 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38431746570 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38431746570 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38431746570 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38431746570 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8547925 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8547925 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5944798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5944798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194675 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194675 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 193703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092368 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092368 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092368 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545 # average overall miss latency +system.cpu0.dcache.tags.replacements 1186136 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.274988 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11457169 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1186648 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.655070 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 107469250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.274988 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6449366 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6449366 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4705451 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4705451 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140478 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140478 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147984 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147984 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11154817 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11154817 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11154817 # number of overall hits +system.cpu0.dcache.overall_hits::total 11154817 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939343 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 256772 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 256772 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13639 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13639 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5591 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5591 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1196115 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1196115 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1196115 # number of overall misses +system.cpu0.dcache.overall_misses::total 1196115 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37523052456 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37523052456 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096844 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096844 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096844 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096844 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31370.773258 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1197,62 +1261,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 798646 # number of writebacks -system.cpu0.dcache.writebacks::total 798646 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1338670 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1338670 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 682430 # number of writebacks +system.cpu0.dcache.writebacks::total 682430 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196115 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1196115 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1264,22 +1328,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 957039 # DTB read hits +system.cpu1.dtb.read_hits 2385380 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 556340 # DTB write hits +system.cpu1.dtb.write_hits 1707840 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 1513379 # DTB hits +system.cpu1.dtb.data_hits 4093220 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1320031 # ITB hits +system.cpu1.itb.fetch_hits 1814538 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1321095 # ITB accesses +system.cpu1.itb.fetch_accesses 1815602 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1292,51 +1356,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921887017 # number of cpu cycles simulated +system.cpu1.numCycles 3921880904 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 4749746 # Number of instructions committed -system.cpu1.committedOps 4749746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4446088 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 30301 # Number of float alu accesses -system.cpu1.num_func_calls 145582 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 455512 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4446088 # number of integer instructions -system.cpu1.num_fp_insts 30301 # number of float instructions -system.cpu1.num_int_register_reads 6169769 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3384887 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 19629 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 19442 # number of times the floating registers were written -system.cpu1.num_mem_refs 1521715 # number of memory refs -system.cpu1.num_load_insts 962201 # Number of load instructions -system.cpu1.num_store_insts 559514 # Number of store instructions -system.cpu1.num_idle_cycles 3904242469.193159 # Number of idle cycles -system.cpu1.num_busy_cycles 17644547.806841 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004499 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995501 # Percentage of idle cycles +system.cpu1.committedInsts 12967796 # Number of instructions committed +system.cpu1.committedOps 12967796 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11946960 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses +system.cpu1.num_func_calls 410982 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1284197 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11946960 # number of integer instructions +system.cpu1.num_fp_insts 174217 # number of float instructions +system.cpu1.num_int_register_reads 16422187 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8787604 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written +system.cpu1.num_mem_refs 4116157 # number of memory refs +system.cpu1.num_load_insts 2399132 # Number of load instructions +system.cpu1.num_store_insts 1717025 # Number of store instructions +system.cpu1.num_idle_cycles 3872385828.119347 # Number of idle cycles +system.cpu1.num_busy_cycles 49495075.880653 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012620 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2329 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 33659 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8392 30.97% 30.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 7.27% 38.24% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.32% 38.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 16645 61.43% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 27095 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8384 44.74% 44.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 10.51% 55.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.47% 55.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8296 44.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 18738 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917649813500 97.79% 97.79% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700167000 0.04% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 60318500 0.00% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42533179500 2.17% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960943478500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999047 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2742 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78306 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26634 38.27% 38.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40476 58.16% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69596 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25767 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25250 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53503 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909643308000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700945000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 361639500 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50234529500 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940422000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967448 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.498408 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.691567 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.623826 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768765 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1352,81 +1416,81 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 283 1.02% 1.06% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.07% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.03% 1.09% # number of callpals executed -system.cpu1.kern.callpal::swpipl 22604 81.73% 82.82% # number of callpals executed -system.cpu1.kern.callpal::rdps 2147 7.76% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal::rti 2432 8.79% 99.41% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.44% 99.84% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.78% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63390 88.19% 91.60% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 2.99% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::rti 3719 5.17% 99.77% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 27656 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 652 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 379 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 12 -system.cpu1.kern.mode_switch_good::kernel 0.581288 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71875 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2907 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 809 +system.cpu1.kern.mode_good::user 368 +system.cpu1.kern.mode_good::idle 441 +system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.005811 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.245785 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 284 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 79630 # number of replacements -system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 4672446 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 4672446 # number of overall hits -system.cpu1.icache.overall_hits::total 4672446 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 80179 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 80179 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 80179 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 80179 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 80179 # number of overall misses -system.cpu1.icache.overall_misses::total 80179 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1082064992 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1082064992 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 4752625 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 4752625 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 4752625 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 4752625 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016870 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016870 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016870 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016870 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13495.615959 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.151703 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309310 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17986321500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1483696000 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1940592550000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2002 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 317593 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.454785 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12652531 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318104 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.774825 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959964216000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.454785 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12652531 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12652531 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12652531 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12652531 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12652531 # number of overall hits +system.cpu1.icache.overall_hits::total 12652531 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318144 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318144 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318144 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318144 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318144 # number of overall misses +system.cpu1.icache.overall_misses::total 318144 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4187615492 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4187615492 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12970675 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12970675 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12970675 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12970675 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024528 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.641735 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13162.641735 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13162.641735 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1435,112 +1499,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 80179 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 80179 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 80179 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 80179 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016870 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016870 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11492.510608 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318144 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318144 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318144 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318144 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3551128508 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3551128508 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024528 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024528 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024528 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11162.016282 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 40890 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 531046 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 9250 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 9250 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 9554 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 9554 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1448467 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1448467 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1448467 # number of overall hits -system.cpu1.dcache.overall_hits::total 1448467 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 31971 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 31971 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 13337 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 13337 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 850 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 850 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 495 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 495 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 45308 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 45308 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 45308 # number of overall misses -system.cpu1.dcache.overall_misses::total 45308 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 398942000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 398942000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 455916495 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 455916495 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 9380250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 9380250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3699073 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3699073 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 854858495 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 854858495 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 854858495 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 854858495 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 949392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 949392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 544383 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 544383 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 10100 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 10100 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 10049 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 10049 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1493775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1493775 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1493775 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1493775 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033675 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033675 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.024499 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.024499 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.049259 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.049259 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030331 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.030331 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030331 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030331 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12478.245910 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12478.245910 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34184.336432 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34184.336432 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11035.588235 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11035.588235 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7472.874747 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7472.874747 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18867.716408 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18867.716408 # average overall miss latency +system.cpu1.dcache.tags.replacements 159205 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.204508 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3919863 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 159531 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.571168 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048842695500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.204508 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949618 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949618 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2222453 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2222453 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1596000 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1596000 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48034 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48034 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50617 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50617 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3818453 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3818453 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3818453 # number of overall hits +system.cpu1.dcache.overall_hits::total 3818453 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 116850 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 116850 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 57159 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 57159 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9086 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9086 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6023 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6023 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 174009 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 174009 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 174009 # number of overall misses +system.cpu1.dcache.overall_misses::total 174009 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411488249 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1411488249 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1045308027 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1045308027 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82519500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 82519500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44276427 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 44276427 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2456796276 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2456796276 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2456796276 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2456796276 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2339303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2339303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1653159 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1653159 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57120 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57120 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56640 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56640 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3992462 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3992462 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3992462 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3992462 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049951 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049951 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034576 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034576 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159069 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159069 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106338 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106338 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043584 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043584 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043584 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043584 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12079.488652 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12079.488652 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18287.724190 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18287.724190 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9082.049307 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9082.049307 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7351.224805 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7351.224805 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14118.788545 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14118.788545 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1549,62 +1613,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 22236 # number of writebacks -system.cpu1.dcache.writebacks::total 22236 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 31971 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 31971 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 13337 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 13337 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 850 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 850 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 495 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 45308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 45308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 45308 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 45308 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 109639 # number of writebacks +system.cpu1.dcache.writebacks::total 109639 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 174009 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 174009 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 0de871519..479e1f707 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,123 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.918473 # Number of seconds simulated -sim_ticks 1918473094000 # Number of ticks simulated -final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920428 # Number of seconds simulated +sim_ticks 1920428041000 # Number of ticks simulated +final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 948634 # Simulator instruction rate (inst/s) -host_op_rate 948634 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32389976926 # Simulator tick rate (ticks/s) -host_mem_usage 304780 # Number of bytes of host memory used -host_seconds 59.23 # Real time elapsed on the host -sim_insts 56188014 # Number of instructions simulated -sim_ops 56188014 # Number of ops (including micro ops) simulated +host_inst_rate 1218375 # Simulator instruction rate (inst/s) +host_op_rate 1218374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41646226437 # Simulator tick rate (ticks/s) +host_mem_usage 305884 # Number of bytes of host memory used +host_seconds 46.11 # Real time elapsed on the host +sim_insts 56182750 # Number of instructions simulated +sim_ops 56182750 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28350528 # Total number of bytes read from memory -system.physmem.bytesWritten 7389888 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1918461222000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442977 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 115467 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442968 # Number of read requests accepted +system.physmem.writeReqs 115466 # Number of write requests accepted +system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue +system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 27966 # Per bank write bursts +system.physmem.perBankRdBursts::1 28089 # Per bank write bursts +system.physmem.perBankRdBursts::2 28297 # Per bank write bursts +system.physmem.perBankRdBursts::3 28053 # Per bank write bursts +system.physmem.perBankRdBursts::4 27407 # Per bank write bursts +system.physmem.perBankRdBursts::5 27545 # Per bank write bursts +system.physmem.perBankRdBursts::6 26911 # Per bank write bursts +system.physmem.perBankRdBursts::7 26762 # Per bank write bursts +system.physmem.perBankRdBursts::8 27807 # Per bank write bursts +system.physmem.perBankRdBursts::9 27255 # Per bank write bursts +system.physmem.perBankRdBursts::10 27714 # Per bank write bursts +system.physmem.perBankRdBursts::11 27327 # Per bank write bursts +system.physmem.perBankRdBursts::12 27431 # Per bank write bursts +system.physmem.perBankRdBursts::13 28073 # Per bank write bursts +system.physmem.perBankRdBursts::14 28024 # Per bank write bursts +system.physmem.perBankRdBursts::15 28256 # Per bank write bursts +system.physmem.perBankWrBursts::0 7722 # Per bank write bursts +system.physmem.perBankWrBursts::1 7593 # Per bank write bursts +system.physmem.perBankWrBursts::2 7833 # Per bank write bursts +system.physmem.perBankWrBursts::3 7543 # Per bank write bursts +system.physmem.perBankWrBursts::4 7010 # Per bank write bursts +system.physmem.perBankWrBursts::5 6982 # Per bank write bursts +system.physmem.perBankWrBursts::6 6469 # Per bank write bursts +system.physmem.perBankWrBursts::7 6223 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6661 # Per bank write bursts +system.physmem.perBankWrBursts::10 7099 # Per bank write bursts +system.physmem.perBankWrBursts::11 6780 # Per bank write bursts +system.physmem.perBankWrBursts::12 7009 # Per bank write bursts +system.physmem.perBankWrBursts::13 7722 # Per bank write bursts +system.physmem.perBankWrBursts::14 7773 # Per bank write bursts +system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1920416169000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 442968 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 115466 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -129,233 +131,289 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation -system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests -system.physmem.totBusLat 2214635000 # Total cycles spent in databus access -system.physmem.totBankLat 5924943750 # Total cycles spent in bank access -system.physmem.avgQLat 8261.25 # Average queueing delay per request -system.physmem.avgBankLat 13376.80 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26638.04 # Average memory access latency -system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation +system.physmem.totQLat 6257775000 # Total ticks spent queuing +system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks +system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 13.19 # Average write queue length over time -system.physmem.readRowHits 427838 # Number of row buffer hits during reads -system.physmem.writeRowHits 93417 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes -system.physmem.avgGap 3435369.03 # Average gap between requests -system.membus.throughput 18671288 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292313 # Transaction distribution -system.membus.trans_dist::ReadResp 292313 # Transaction distribution -system.membus.trans_dist::WriteReq 9649 # Transaction distribution -system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115467 # Transaction distribution +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing +system.physmem.readRowHits 419360 # Number of row buffer hits during reads +system.physmem.writeRowHits 92763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes +system.physmem.avgGap 3438931.31 # Average gap between requests +system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18651952 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292310 # Transaction distribution +system.membus.trans_dist::ReadResp 292310 # Transaction distribution +system.membus.trans_dist::WriteReq 9650 # Transaction distribution +system.membus.trans_dist::WriteResp 9650 # Transaction distribution +system.membus.trans_dist::Writeback 115466 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158147 # Transaction distribution -system.membus.trans_dist::ReadExResp 158147 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 158141 # Transaction distribution +system.membus.trans_dist::ReadExResp 158141 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35784972 # Total data (bytes) +system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35784340 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -364,14 +422,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -388,19 +446,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -414,14 +472,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +488,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +513,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9065600 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9064966 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356756 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6356267 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15422356 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15421233 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974352 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973920 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979362 # ITB accesses +system.cpu.itb.fetch_accesses 4978917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -483,51 +541,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3836946188 # number of cpu cycles simulated +system.cpu.numCycles 3840856082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56188014 # Number of instructions committed -system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1483456 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls -system.cpu.num_int_insts 52059797 # number of integer instructions -system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read -system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15474978 # number of memory refs -system.cpu.num_load_insts 9102456 # Number of load instructions -system.cpu.num_store_insts 6372522 # Number of store instructions -system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles -system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles -system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934855 # Percentage of idle cycles +system.cpu.committedInsts 56182750 # Number of instructions committed +system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses +system.cpu.num_func_calls 1483342 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054772 # number of integer instructions +system.cpu.num_fp_insts 324326 # number of float instructions +system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read +system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written +system.cpu.num_mem_refs 15473812 # number of memory refs +system.cpu.num_load_insts 9101789 # Number of load instructions +system.cpu.num_store_insts 6372023 # Number of store instructions +system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934400 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -563,33 +621,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192891 # number of callpals executed +system.cpu.kern.callpal::total 192898 # number of callpals executed system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4176 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -621,12 +679,12 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1410582 # Throughput (bytes/s) +system.iobus.throughput 1409150 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51201 # Transaction distribution -system.iobus.trans_dist::WriteResp 51201 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51202 # Transaction distribution +system.iobus.trans_dist::WriteResp 51202 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -638,11 +696,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -654,12 +712,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2706164 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2706172 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -681,59 +739,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928665 # number of replacements -system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits -system.cpu.icache.overall_hits::total 55270512 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses -system.cpu.icache.overall_misses::total 929336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency +system.cpu.icache.tags.replacements 928358 # number of replacements +system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits +system.cpu.icache.overall_hits::total 55265541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses +system.cpu.icache.overall_misses::total 929029 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,126 +800,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016536 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016536 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336065 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835407 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835407 # number of Writeback hits +system.cpu.l2cache.tags.replacements 336056 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65296.863719 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2447536 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.100265 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6747777750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4758.900638 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4955.117636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 835114 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835114 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187779 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187779 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916024 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002748 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918772 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916024 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002748 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918772 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187645 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187645 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915717 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002459 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918176 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915717 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002459 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918176 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271918 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285210 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271915 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285207 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116714 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116708 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116708 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388632 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 401924 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388623 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 401915 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388632 # number of overall misses -system.cpu.l2cache.overall_misses::total 401924 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1060624743 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16925556244 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17986180987 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 388623 # number of overall misses +system.cpu.l2cache.overall_misses::total 401915 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1012336742 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17564329991 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18576666733 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7757662128 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7757662128 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1060624743 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24683218372 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25743843115 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1060624743 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24683218372 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25743843115 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 929316 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2016203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 835407 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 835407 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8190852374 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8190852374 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1012336742 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 25755182365 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26767519107 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1012336742 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 25755182365 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26767519107 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 929009 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1086729 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2015738 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 835114 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835114 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304493 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304493 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929316 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391380 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320696 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929316 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391380 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014303 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250181 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304353 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304353 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929009 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391082 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320091 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929009 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391082 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320091 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014308 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250214 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141490 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383306 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383306 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014303 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279314 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173191 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014303 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279314 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173191 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79794.217800 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62245.074780 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 63062.939543 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014308 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279367 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173232 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014308 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279367 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173232 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66467.280086 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66467.280086 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 64051.519976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 64051.519976 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,66 +928,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 73955 # number of writebacks -system.cpu.l2cache.writebacks::total 73955 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 73954 # number of writebacks +system.cpu.l2cache.writebacks::total 73954 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271918 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285210 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116708 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116708 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388632 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401924 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388623 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401915 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388632 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401924 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 893093257 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13525299756 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14418393013 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 388623 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401915 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 845706258 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14164824509 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15010530767 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6297401372 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6297401372 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 893093257 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19822701128 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20715794385 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 893093257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19822701128 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20715794385 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334143500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334143500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229575000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229575000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6731491626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6731491626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 845706258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20896316135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21742022393 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 845706258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20896316135 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21742022393 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895642000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895642000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250214 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141490 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383306 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383306 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173232 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173232 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53955.835392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53955.835392 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -937,79 +995,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390866 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1390568 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14049173 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391080 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099472 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107298250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852671 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183038 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183038 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13667738 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13667738 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13667738 # number of overall hits -system.cpu.dcache.overall_hits::total 13667738 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069668 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069668 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304510 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304510 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17219 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17219 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374178 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374178 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374178 # number of overall misses -system.cpu.dcache.overall_misses::total 1374178 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28240934256 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28240934256 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10606589383 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10606589383 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229410500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 229410500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38847523639 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38847523639 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38847523639 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38847523639 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8884735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8884735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157181 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157181 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15041916 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15041916 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15041916 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15041916 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120394 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120394 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085985 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085985 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091357 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091357 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091357 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091357 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28269.644572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28269.644572 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits +system.cpu.dcache.overall_hits::total 13666948 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069470 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069470 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17259 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373840 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373840 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373840 # number of overall misses +system.cpu.dcache.overall_misses::total 1373840 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28875755759 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28875755759 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11035273137 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11035273137 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228925250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228925250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39911028896 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39911028896 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39911028896 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39911028896 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8884092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8884092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156696 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156696 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1018,54 +1076,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks -system.cpu.dcache.writebacks::total 835407 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks +system.cpu.dcache.writebacks::total 835114 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,31 +1131,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution +system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 643b5e070..951921c42 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,148 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194884 # Number of seconds simulated -sim_ticks 1194883580500 # Number of ticks simulated -final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.195756 # Number of seconds simulated +sim_ticks 1195756323500 # Number of ticks simulated +final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 298011 # Simulator instruction rate (inst/s) -host_op_rate 379758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5802481089 # Simulator tick rate (ticks/s) -host_mem_usage 399660 # Number of bytes of host memory used -host_seconds 205.93 # Real time elapsed on the host -sim_insts 61368273 # Number of instructions simulated -sim_ops 78202205 # Number of ops (including micro ops) simulated +host_inst_rate 469394 # Simulator instruction rate (inst/s) +host_op_rate 598174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9145402965 # Simulator tick rate (ticks/s) +host_mem_usage 398732 # Number of bytes of host memory used +host_seconds 130.75 # Real time elapsed on the host +sim_insts 61373013 # Number of instructions simulated +sim_ops 78210923 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory +system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory +system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 425896384 # Total number of bytes read from memory -system.physmem.bytesWritten 52573888 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194879167500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6825 # Categorize read packet sizes -system.physmem.readPktSize::3 6488064 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159742 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64631 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654771 # Number of read requests accepted +system.physmem.writeReqs 821574 # Number of write requests accepted +system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415729 # Per bank write bursts +system.physmem.perBankRdBursts::1 415559 # Per bank write bursts +system.physmem.perBankRdBursts::2 414962 # Per bank write bursts +system.physmem.perBankRdBursts::3 415336 # Per bank write bursts +system.physmem.perBankRdBursts::4 422370 # Per bank write bursts +system.physmem.perBankRdBursts::5 415375 # Per bank write bursts +system.physmem.perBankRdBursts::6 415451 # Per bank write bursts +system.physmem.perBankRdBursts::7 415289 # Per bank write bursts +system.physmem.perBankRdBursts::8 415350 # Per bank write bursts +system.physmem.perBankRdBursts::9 415631 # Per bank write bursts +system.physmem.perBankRdBursts::10 415265 # Per bank write bursts +system.physmem.perBankRdBursts::11 414898 # Per bank write bursts +system.physmem.perBankRdBursts::12 415464 # Per bank write bursts +system.physmem.perBankRdBursts::13 416088 # Per bank write bursts +system.physmem.perBankRdBursts::14 415829 # Per bank write bursts +system.physmem.perBankRdBursts::15 415792 # Per bank write bursts +system.physmem.perBankWrBursts::0 7314 # Per bank write bursts +system.physmem.perBankWrBursts::1 7200 # Per bank write bursts +system.physmem.perBankWrBursts::2 6696 # Per bank write bursts +system.physmem.perBankWrBursts::3 6864 # Per bank write bursts +system.physmem.perBankWrBursts::4 7395 # Per bank write bursts +system.physmem.perBankWrBursts::5 6961 # Per bank write bursts +system.physmem.perBankWrBursts::6 7170 # Per bank write bursts +system.physmem.perBankWrBursts::7 6990 # Per bank write bursts +system.physmem.perBankWrBursts::8 6985 # Per bank write bursts +system.physmem.perBankWrBursts::9 7249 # Per bank write bursts +system.physmem.perBankWrBursts::10 6972 # Per bank write bursts +system.physmem.perBankWrBursts::11 6687 # Per bank write bursts +system.physmem.perBankWrBursts::12 7224 # Per bank write bursts +system.physmem.perBankWrBursts::13 7527 # Per bank write bursts +system.physmem.perBankWrBursts::14 7429 # Per bank write bursts +system.physmem.perBankWrBursts::15 7403 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1195751937000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6825 # Read request sizes (log2) +system.physmem.readPktSize::3 6488064 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 159882 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 64738 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -157,31 +159,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -189,282 +191,423 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation -system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests -system.physmem.totBusLat 33270500000 # Total cycles spent in databus access -system.physmem.totBankLat 8590725000 # Total cycles spent in bank access -system.physmem.avgQLat 19013.79 # Average queueing delay per request -system.physmem.avgBankLat 1291.04 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25304.84 # Average memory access latency -system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 14.04 # Average write queue length over time -system.physmem.readRowHits 6636405 # Number of row buffer hits during reads -system.physmem.writeRowHits 97666 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes -system.physmem.avgGap 159826.58 # Average gap between requests +system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 75 0.10% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 96 0.13% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 79 0.11% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 29 0.04% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 17 0.02% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 176 0.23% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 83 0.11% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 12 0.02% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 24 0.03% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 154 0.21% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 2 0.00% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 30 0.04% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13639 1 0.00% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 90 0.12% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 16 0.02% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 91 0.12% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 14 0.02% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 2 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 154 0.21% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 12 0.02% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 76 0.10% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 82 0.11% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 16 0.02% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 19 0.03% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 4 0.01% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 270 0.36% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 2 0.00% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 17 0.02% 86.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 84 0.11% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 77 0.10% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 12 0.02% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 2 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 156 0.21% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 14 0.02% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 92 0.12% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 12 0.02% 86.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 95 0.13% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 30 0.04% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 1 0.00% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 153 0.20% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 23 0.03% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 10 0.01% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 83 0.11% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 180 0.24% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20551 2 0.00% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 18 0.02% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 75 0.10% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 92 0.12% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 14 0.02% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 35 0.05% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 142 0.19% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 87 0.12% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 1 0.00% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 4 0.01% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 166 0.22% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 23 0.03% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 66 0.09% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 30 0.04% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 147 0.20% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 27 0.04% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 68 0.09% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 24 0.03% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 1 0.00% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 171 0.23% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 5 0.01% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 19 0.03% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 83 0.11% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 139 0.19% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 34 0.05% 89.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 75 0.10% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 2 0.00% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 88 0.12% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 2 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 75 0.10% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 24 0.03% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 21 0.03% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 180 0.24% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 2 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 82 0.11% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 10 0.01% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 24 0.03% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 153 0.20% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 28 0.04% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 92 0.12% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 14 0.02% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 87 0.12% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 12 0.02% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 151 0.20% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 11 0.01% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 72 0.10% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 84 0.11% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 15 0.02% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 273 0.36% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 27 0.04% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 28 0.04% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 83 0.11% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 70 0.09% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 153 0.20% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 13 0.02% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 85 0.11% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 13 0.02% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 90 0.12% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 32 0.04% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 150 0.20% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 9 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 172 0.23% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 19 0.03% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 2 0.00% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 23 0.03% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 70 0.09% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 89 0.12% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 2 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 74 0.10% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 31 0.04% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 140 0.19% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 81 0.11% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 14 0.02% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 5 0.01% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 169 0.23% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 23 0.03% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 29 0.04% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 152 0.20% 94.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 26 0.03% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 66 0.09% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 22 0.03% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 165 0.22% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 4 0.01% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 13 0.02% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42560-42567 1 0.00% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 87 0.12% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 139 0.19% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 32 0.04% 95.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43584-43591 1 0.00% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 72 0.10% 95.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 72 0.10% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 22 0.03% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 169 0.23% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 83 0.11% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 7 0.01% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 22 0.03% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 150 0.20% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 96 0.13% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 12 0.02% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 92 0.12% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 3 0.00% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 18 0.02% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 2 0.00% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 154 0.21% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 17 0.02% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 94 0.13% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 97 0.13% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 12 0.02% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation +system.physmem.totQLat 159590177750 # Total ticks spent queuing +system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks +system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.83 # Data bus utilization in percentage +system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing +system.physmem.readRowHits 6598517 # Number of row buffer hits during reads +system.physmem.writeRowHits 94894 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes +system.physmem.avgGap 159938.04 # Average gap between requests +system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -483,286 +626,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60029719 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703148 # Transaction distribution -system.membus.trans_dist::ReadResp 7703148 # Transaction distribution -system.membus.trans_dist::WriteReq 767203 # Transaction distribution -system.membus.trans_dist::WriteResp 767203 # Transaction distribution -system.membus.trans_dist::Writeback 64631 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution -system.membus.trans_dist::ReadExReq 137763 # Transaction distribution -system.membus.trans_dist::ReadExResp 137302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes) +system.membus.throughput 59999152 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703168 # Transaction distribution +system.membus.trans_dist::ReadResp 7703168 # Transaction distribution +system.membus.trans_dist::WriteReq 767205 # Transaction distribution +system.membus.trans_dist::WriteResp 767205 # Transaction distribution +system.membus.trans_dist::Writeback 64738 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution +system.membus.trans_dist::ReadExReq 137900 # Transaction distribution +system.membus.trans_dist::ReadExResp 137428 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71728526 # Total data (bytes) +system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71744366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69624 # number of replacements -system.l2c.tags.tagsinuse 53154.717455 # Cycle average of tags in use -system.l2c.tags.total_refs 1650852 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134785 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.248039 # Average number of references to valid blocks. +system.l2c.tags.replacements 69764 # number of replacements +system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use +system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40039.692381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4638.680952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5789.816440 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1927.067698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 756.788910 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.610957 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.088346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011548 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1438 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 483013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 241892 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1869 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372280 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110462 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1219260 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576006 # number of Writeback hits -system.l2c.Writeback_hits::total 576006 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1292 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 416 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1708 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65542 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45349 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110891 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1438 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 483013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307434 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1869 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 372280 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155811 # number of demand (read+write) hits -system.l2c.demand_hits::total 1330151 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1438 # number of overall hits -system.l2c.overall_hits::cpu0.inst 483013 # number of overall hits -system.l2c.overall_hits::cpu0.data 307434 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1869 # number of overall hits -system.l2c.overall_hits::cpu1.inst 372280 # number of overall hits -system.l2c.overall_hits::cpu1.data 155811 # number of overall hits -system.l2c.overall_hits::total 1330151 # number of overall hits +system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.811096 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1510 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 483170 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 242041 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3562 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1809 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110996 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220343 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576824 # number of Writeback hits +system.l2c.Writeback_hits::total 576824 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 452 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 372569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 156291 # number of demand (read+write) hits +system.l2c.demand_hits::total 1331260 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4686 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1510 # number of overall hits +system.l2c.overall_hits::cpu0.inst 483170 # number of overall hits +system.l2c.overall_hits::cpu0.data 307663 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3562 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1809 # number of overall hits +system.l2c.overall_hits::cpu1.inst 372569 # number of overall hits +system.l2c.overall_hits::cpu1.data 156291 # number of overall hits +system.l2c.overall_hits::total 1331260 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9716 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6835 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9720 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22441 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3974 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7345 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 385 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 476 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 44603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139739 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1892 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22455 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3383 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 7371 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 866 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 95249 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 44598 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139847 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 104852 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6835 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 104969 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 46493 # number of demand (read+write) misses -system.l2c.demand_misses::total 162180 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 46490 # number of demand (read+write) misses +system.l2c.demand_misses::total 162302 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses -system.l2c.overall_misses::cpu0.data 104852 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6835 # number of overall misses +system.l2c.overall_misses::cpu0.data 104969 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses -system.l2c.overall_misses::cpu1.data 46493 # number of overall misses -system.l2c.overall_misses::total 162180 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 687750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 482771250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 688091749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 282183750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 151111000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1605057249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11611000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12427970 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24038970 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1906918 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117452 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3024370 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6193599427 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2824169884 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9017769311 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 687750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 482771250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6881691176 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 282183750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2975280884 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10622826560 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 687750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 482771250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6881691176 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 282183750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2975280884 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10622826560 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1440 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 489845 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 251608 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1870 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 376276 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 112352 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1241701 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 576006 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 576006 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5266 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3787 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 9053 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 640 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1216 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 160678 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 89952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250630 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1440 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 489845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1870 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 376276 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 202304 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492331 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1440 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 489845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1870 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 376276 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 202304 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492331 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013947 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038616 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010620 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.016822 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018073 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754652 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890151 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.811333 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601562 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826389 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.708059 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.592091 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.495853 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.557551 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013947 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.254319 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010620 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.229818 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108676 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013947 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.254319 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010620 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.229818 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108676 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70663.239169 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 70820.476431 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70616.554054 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 79952.910053 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71523.428056 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2921.741319 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3686.730940 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3272.834581 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4953.033766 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2347.588235 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3512.624855 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65102.583953 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63317.935655 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 64532.945785 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 65500.225429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 65500.225429 # average overall miss latency +system.l2c.overall_misses::cpu1.inst 4001 # number of overall misses +system.l2c.overall_misses::cpu1.data 46490 # number of overall misses +system.l2c.overall_misses::total 162302 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 302000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 491601250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 735185497 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 283983750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 151633750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1662931247 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11383008 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12410968 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 23793976 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1839921 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117953 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2957874 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6545912193 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3449006386 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9994918579 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 302000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 491601250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 7281097690 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 283983750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3600640136 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11657849826 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 302000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 491601250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 7281097690 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 283983750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3600640136 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11657849826 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4690 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1512 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 490005 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 251761 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3562 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 376570 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 112888 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1242798 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 576824 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 576824 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5277 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3835 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9112 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 655 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1232 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 160871 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 89893 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250764 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4690 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1512 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 490005 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 412632 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3562 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1810 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 376570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 202781 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1493562 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4690 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1512 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 490005 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 412632 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3562 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1810 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 376570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 202781 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1493562 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001323 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013949 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038608 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000552 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010625 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.016760 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018068 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.755732 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.882138 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.808933 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.590840 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830156 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.702922 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.592083 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.496123 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.557684 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001323 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013949 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.254389 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000552 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010625 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.229262 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108668 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001323 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013949 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.254389 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000552 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010625 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.229262 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108668 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71924.103877 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75636.368004 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70978.192952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 80144.688161 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 74056.167758 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2854.314945 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3668.627845 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3228.052639 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4754.317829 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2333.931106 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3415.558891 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68724.209105 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77335.449706 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 71470.382482 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71828.134133 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71828.134133 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -771,8 +914,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64631 # number of writebacks -system.l2c.writebacks::total 64631 # number of writebacks +system.l2c.writebacks::writebacks 64738 # number of writebacks +system.l2c.writebacks::total 64738 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -781,149 +924,149 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6831 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9716 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6834 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9720 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22440 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 3974 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3371 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 7345 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 385 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 476 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 95136 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 44603 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139739 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4001 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1892 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22454 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3988 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3383 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7371 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 387 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 866 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 95249 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 44598 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139847 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6831 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 104852 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6834 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 104969 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3996 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 46493 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162179 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4001 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 46490 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162301 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6831 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 104852 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6834 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 104969 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3996 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 46493 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162179 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 635750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 396501000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 564859249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 231739250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 127085000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1320993999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39771967 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33821856 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 73593823 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3851884 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768975 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 8620859 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5000986069 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2264195114 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7265181183 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 635750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 396501000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5565845318 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 231739250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2391280114 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8586175182 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 635750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 396501000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5565845318 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 231739250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2391280114 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8586175182 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 323836500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647640494 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070543500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167046869994 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272049535 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486218500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16758268035 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 323836500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919690029 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556762000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183805138029 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038616 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016822 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018072 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754652 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890151 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.811333 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601562 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826389 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708059 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592091 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495853 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.557551 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108675 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108675 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58137.016159 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67240.740741 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58867.825267 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 4001 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 46490 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162301 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 254000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 405760500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 614009497 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233748250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 128083750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1382043497 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39929483 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33964367 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 73893850 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3876386 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4797478 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 8673864 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5351778297 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2889281614 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8241059911 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 254000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 405760500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5965787794 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 233748250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3017365364 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9623103408 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 254000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 405760500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5965787794 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 233748250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3017365364 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9623103408 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648858491 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5098250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154081373749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167080044240 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272206162 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486212000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16758418162 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921064653 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5098250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154567585749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183838462402 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592083 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -944,64 +1087,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118384606 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137140510 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks) +system.toL2Bus.throughput 118413539 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137274438 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45439063 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution +system.iobus.throughput 45405912 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution system.iobus.trans_dist::WriteResp 7946 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) @@ -1021,14 +1164,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) @@ -1048,18 +1191,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294390 # Total data (bytes) +system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294406 # Total data (bytes) system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1101,32 +1244,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9653247 # DTB read hits -system.cpu0.dtb.read_misses 3738 # DTB read misses -system.cpu0.dtb.write_hits 7597488 # DTB write hits -system.cpu0.dtb.write_misses 1585 # DTB write misses +system.cpu0.dtb.read_hits 9652613 # DTB read hits +system.cpu0.dtb.read_misses 3746 # DTB read misses +system.cpu0.dtb.write_hits 7596890 # DTB write hits +system.cpu0.dtb.write_misses 1582 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9656985 # DTB read accesses -system.cpu0.dtb.write_accesses 7599073 # DTB write accesses +system.cpu0.dtb.read_accesses 9656359 # DTB read accesses +system.cpu0.dtb.write_accesses 7598472 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17250735 # DTB hits -system.cpu0.dtb.misses 5323 # DTB misses -system.cpu0.dtb.accesses 17256058 # DTB accesses -system.cpu0.itb.inst_hits 43297764 # ITB inst hits +system.cpu0.dtb.hits 17249503 # DTB hits +system.cpu0.dtb.misses 5328 # DTB misses +system.cpu0.dtb.accesses 17254831 # DTB accesses +system.cpu0.itb.inst_hits 43298526 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1143,79 +1286,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses -system.cpu0.itb.hits 43297764 # DTB hits +system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses +system.cpu0.itb.hits 43298526 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43299969 # DTB accesses -system.cpu0.numCycles 2389767161 # number of cpu cycles simulated +system.cpu0.itb.accesses 43300731 # DTB accesses +system.cpu0.numCycles 2391512647 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42570861 # Number of instructions committed -system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses +system.cpu0.committedInsts 42571581 # Number of instructions committed +system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403492 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48060351 # number of integer instructions +system.cpu0.num_func_calls 1403638 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48058821 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18020156 # number of memory refs -system.cpu0.num_load_insts 10037111 # Number of load instructions -system.cpu0.num_store_insts 7983045 # Number of store instructions -system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles -system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles +system.cpu0.num_mem_refs 18019009 # number of memory refs +system.cpu0.num_load_insts 10036459 # Number of load instructions +system.cpu0.num_store_insts 7982550 # Number of store instructions +system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles +system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490078 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits -system.cpu0.icache.overall_hits::total 42807156 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses -system.cpu0.icache.overall_misses::total 490591 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency +system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490259 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits +system.cpu0.icache.overall_hits::total 42807737 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490772 # number of overall misses +system.cpu0.icache.overall_misses::total 490772 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6820513233 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6820513233 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6820513233 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6820513233 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6820513233 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6820513233 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298509 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43298509 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43298509 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43298509 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43298509 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43298509 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011335 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011335 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011335 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011335 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011335 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011335 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.519078 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.519078 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13897.519078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13897.519078 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1224,120 +1367,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490772 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490772 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490772 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490772 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490772 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490772 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5836336767 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5836336767 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5836336767 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5836336767 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5836336767 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5836336767 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11892.155149 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 406634 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6494912 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156532 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156532 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159004 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159004 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 15632259 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 15632259 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 15632259 # number of overall hits -system.cpu0.dcache.overall_hits::total 15632259 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 263669 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 263669 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 176685 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 176685 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9910 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9910 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7384 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7384 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 440354 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 440354 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 440354 # number of overall misses -system.cpu0.dcache.overall_misses::total 440354 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3876875497 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3876875497 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7541622539 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7541622539 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98733750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 98733750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40506385 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 40506385 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11418498036 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11418498036 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11418498036 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11418498036 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401016 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9401016 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671597 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028047 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026483 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026483 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044378 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044378 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9963.042381 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9963.042381 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5485.696777 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5485.696777 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency +system.cpu0.dcache.tags.replacements 407019 # number of replacements +system.cpu0.dcache.tags.tagsinuse 470.951702 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 15966189 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 407531 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 39.177852 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.951702 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919828 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.919828 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9136364 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9136364 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6494337 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6494337 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156491 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156491 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158920 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 158920 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15630701 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15630701 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15630701 # number of overall hits +system.cpu0.dcache.overall_hits::total 15630701 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 264039 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 264039 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176698 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176698 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9925 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9925 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7429 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7429 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440737 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440737 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440737 # number of overall misses +system.cpu0.dcache.overall_misses::total 440737 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3925412746 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3925412746 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7893125788 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7893125788 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98805250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98805250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40843887 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40843887 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11818538534 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11818538534 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11818538534 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11818538534 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400403 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9400403 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671035 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6671035 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166349 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166349 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16071438 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16071438 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16071438 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16071438 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028088 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028088 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026487 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026487 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059640 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059640 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044659 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044659 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027424 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027424 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027424 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027424 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14866.791444 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14866.791444 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1346,66 +1489,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376568 # number of writebacks -system.cpu0.dcache.writebacks::total 376568 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263669 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263669 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176685 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176685 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9910 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9910 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7379 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7379 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440354 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440354 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440354 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440354 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3344880503 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3344880503 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7142186461 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7142186461 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78848250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78848250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25751615 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25751615 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks +system.cpu0.dcache.writebacks::total 376552 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10487066964 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10487066964 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10487066964 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10487066964 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764220500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764220500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807115461 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807115461 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39571335961 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028047 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028047 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026483 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026483 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044348 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044348 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1415,26 +1558,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5705173 # DTB read hits -system.cpu1.dtb.read_misses 3576 # DTB read misses -system.cpu1.dtb.write_hits 3872049 # DTB write hits -system.cpu1.dtb.write_misses 645 # DTB write misses +system.cpu1.dtb.read_hits 5708064 # DTB read hits +system.cpu1.dtb.read_misses 3582 # DTB read misses +system.cpu1.dtb.write_hits 3874465 # DTB write hits +system.cpu1.dtb.write_misses 647 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5708749 # DTB read accesses -system.cpu1.dtb.write_accesses 3872694 # DTB write accesses +system.cpu1.dtb.read_accesses 5711646 # DTB read accesses +system.cpu1.dtb.write_accesses 3875112 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9577222 # DTB hits -system.cpu1.dtb.misses 4221 # DTB misses -system.cpu1.dtb.accesses 9581443 # DTB accesses -system.cpu1.itb.inst_hits 19377969 # ITB inst hits +system.cpu1.dtb.hits 9582529 # DTB hits +system.cpu1.dtb.misses 4229 # DTB misses +system.cpu1.dtb.accesses 9586758 # DTB accesses +system.cpu1.itb.inst_hits 19382020 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1451,79 +1594,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses -system.cpu1.itb.hits 19377969 # DTB hits +system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses +system.cpu1.itb.hits 19382020 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19380140 # DTB accesses -system.cpu1.numCycles 2388332817 # number of cpu cycles simulated +system.cpu1.itb.accesses 19384191 # DTB accesses +system.cpu1.numCycles 2390063941 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18797412 # Number of instructions committed -system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses +system.cpu1.committedInsts 18801432 # Number of instructions committed +system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796668 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22263010 # number of integer instructions +system.cpu1.num_func_calls 796781 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22272671 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10012651 # number of memory refs -system.cpu1.num_load_insts 5981805 # Number of load instructions -system.cpu1.num_store_insts 4030846 # Number of store instructions -system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles -system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles +system.cpu1.num_mem_refs 10017952 # number of memory refs +system.cpu1.num_load_insts 5984754 # Number of load instructions +system.cpu1.num_store_insts 4033198 # Number of store instructions +system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles +system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles +system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376539 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits -system.cpu1.icache.overall_hits::total 19000914 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses -system.cpu1.icache.overall_misses::total 377051 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency +system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376793 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits +system.cpu1.icache.overall_hits::total 19004711 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses +system.cpu1.icache.overall_misses::total 377305 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1532,120 +1675,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 220336 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.526784 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8228665 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 220703 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.283884 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106211109000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.526784 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920951 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920951 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 4388185 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4388185 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3672248 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3672248 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73451 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 73451 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73727 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 73727 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8060433 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8060433 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8060433 # number of overall hits -system.cpu1.dcache.overall_hits::total 8060433 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133748 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133748 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 112730 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 112730 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9735 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9735 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9394 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9394 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 246478 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 246478 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 246478 # number of overall misses -system.cpu1.dcache.overall_misses::total 246478 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1649486235 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1649486235 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3739097468 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3739097468 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77937249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 77937249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49168975 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49168975 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5388583703 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5388583703 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5388583703 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5388583703 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4521933 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4521933 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3784978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3784978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 83186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83121 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83121 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8306911 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8306911 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8306911 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8306911 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029578 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.029578 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029784 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029784 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117027 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117027 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113016 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113016 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029671 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029671 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029671 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12332.791780 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12332.791780 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33168.610556 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33168.610556 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8005.880740 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8005.880740 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5234.082925 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5234.082925 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21862.331336 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21862.331336 # average overall miss latency +system.cpu1.dcache.tags.replacements 220883 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920854 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4390672 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4390672 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3674527 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3674527 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73485 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73485 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73732 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73732 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8065199 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8065199 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8065199 # number of overall hits +system.cpu1.dcache.overall_hits::total 8065199 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134090 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134090 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112827 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112827 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9762 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9762 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9429 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9429 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 246917 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246917 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 246917 # number of overall misses +system.cpu1.dcache.overall_misses::total 246917 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1656976729 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1656976729 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4353399476 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4353399476 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77544499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77544499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49349978 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49349978 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6010376205 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6010376205 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6010376205 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6010376205 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524762 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4524762 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3787354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83161 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83161 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8312116 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8312116 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8312116 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8312116 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029635 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029635 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029790 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029790 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117265 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117265 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113382 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113382 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029706 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029706 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029706 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029706 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12357.198367 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12357.198367 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38584.731279 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38584.731279 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7943.505327 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7943.505327 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5233.850673 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5233.850673 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24341.686498 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24341.686498 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1654,66 +1797,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 199438 # number of writebacks -system.cpu1.dcache.writebacks::total 199438 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133748 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133748 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112730 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 112730 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9735 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9735 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9393 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9393 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 246478 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 246478 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 246478 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 246478 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1381071765 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1381071765 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks +system.cpu1.dcache.writebacks::total 200272 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112827 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9426 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9426 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1735,10 +1878,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index efd49eb78..50a428e90 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,130 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615716 # Number of seconds simulated -sim_ticks 2615716222000 # Number of ticks simulated -final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616536 # Number of seconds simulated +sim_ticks 2616536483000 # Number of ticks simulated +final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250038 # Simulator instruction rate (inst/s) -host_op_rate 318184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10864403710 # Simulator tick rate (ticks/s) -host_mem_usage 394540 # Number of bytes of host memory used -host_seconds 240.76 # Real time elapsed on the host -sim_insts 60199078 # Number of instructions simulated -sim_ops 76605946 # Number of ops (including micro ops) simulated +host_inst_rate 552343 # Simulator instruction rate (inst/s) +host_op_rate 702879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24008008080 # Simulator tick rate (ticks/s) +host_mem_usage 395660 # Number of bytes of host memory used +host_seconds 108.99 # Real time elapsed on the host +sim_insts 60197580 # Number of instructions simulated +sim_ops 76603973 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory -system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 991665344 # Total number of bytes read from memory -system.physmem.bytesWritten 51967296 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615711849000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6652 # Categorize read packet sizes -system.physmem.readPktSize::3 15335424 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152695 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57971 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494693 # Number of read requests accepted +system.physmem.writeReqs 811927 # Number of write requests accepted +system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue +system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 967983 # Per bank write bursts +system.physmem.perBankRdBursts::1 967714 # Per bank write bursts +system.physmem.perBankRdBursts::2 967672 # Per bank write bursts +system.physmem.perBankRdBursts::3 967769 # Per bank write bursts +system.physmem.perBankRdBursts::4 974609 # Per bank write bursts +system.physmem.perBankRdBursts::5 968229 # Per bank write bursts +system.physmem.perBankRdBursts::6 967807 # Per bank write bursts +system.physmem.perBankRdBursts::7 967736 # Per bank write bursts +system.physmem.perBankRdBursts::8 968546 # Per bank write bursts +system.physmem.perBankRdBursts::9 968137 # Per bank write bursts +system.physmem.perBankRdBursts::10 967949 # Per bank write bursts +system.physmem.perBankRdBursts::11 967746 # Per bank write bursts +system.physmem.perBankRdBursts::12 967851 # Per bank write bursts +system.physmem.perBankRdBursts::13 967741 # Per bank write bursts +system.physmem.perBankRdBursts::14 967766 # Per bank write bursts +system.physmem.perBankRdBursts::15 967796 # Per bank write bursts +system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankWrBursts::1 6410 # Per bank write bursts +system.physmem.perBankWrBursts::2 6422 # Per bank write bursts +system.physmem.perBankWrBursts::3 6344 # Per bank write bursts +system.physmem.perBankWrBursts::4 6906 # Per bank write bursts +system.physmem.perBankWrBursts::5 7096 # Per bank write bursts +system.physmem.perBankWrBursts::6 6901 # Per bank write bursts +system.physmem.perBankWrBursts::7 6892 # Per bank write bursts +system.physmem.perBankWrBursts::8 7193 # Per bank write bursts +system.physmem.perBankWrBursts::9 6845 # Per bank write bursts +system.physmem.perBankWrBursts::10 6667 # Per bank write bursts +system.physmem.perBankWrBursts::11 6550 # Per bank write bursts +system.physmem.perBankWrBursts::12 6596 # Per bank write bursts +system.physmem.perBankWrBursts::13 6392 # Per bank write bursts +system.physmem.perBankWrBursts::14 6532 # Per bank write bursts +system.physmem.perBankWrBursts::15 6576 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2616532122000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6652 # Read request sizes (log2) +system.physmem.readPktSize::3 15335424 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 152617 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 57909 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1265330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1118297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1122310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3740106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2667387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2661184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2667924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 54482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -140,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -172,281 +174,478 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 16 0.04% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 6 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 5 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 5 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 6 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 6 0.02% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 9 0.02% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 42 0.11% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 2 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 4 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 8 0.02% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 5 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 6 0.02% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 1 0.00% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 6 0.02% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 10 0.03% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 2 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 5 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 58.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 3 0.01% 58.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 3 0.01% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 3 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 1 0.00% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 2 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 2 0.01% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 2 0.01% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 1 0.00% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 4 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 6 0.02% 58.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 16 0.04% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 4 0.01% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 4 0.01% 58.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 4 0.01% 58.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 2 0.01% 58.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 2 0.01% 58.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 5 0.01% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 7 0.02% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 6 0.02% 58.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 8 0.02% 58.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 8 0.02% 58.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 328 0.86% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 24 0.06% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 141 0.37% 59.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 169 0.44% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8831 1 0.00% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 2 0.01% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 3 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 2 0.01% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-14015 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 4 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-15039 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 2 0.01% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 5 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18687 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20415 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22207 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23231 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 4 0.01% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24255 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 3 0.01% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25407 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25791 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation -system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests -system.physmem.totBusLat 77465575000 # Total cycles spent in databus access -system.physmem.totBankLat 16358058750 # Total cycles spent in bank access -system.physmem.avgQLat 19154.87 # Average queueing delay per request -system.physmem.avgBankLat 1055.83 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25210.70 # Average memory access latency -system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.12 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 13.76 # Average write queue length over time -system.physmem.readRowHits 15468398 # Number of row buffer hits during reads -system.physmem.writeRowHits 93875 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes -system.physmem.avgGap 160406.60 # Average gap between requests +system.physmem.bytesPerActivate::samples 89727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11127.069087 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1028.273701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16706.873806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23194 25.85% 25.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14559 16.23% 42.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2860 3.19% 45.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2118 2.36% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1356 1.51% 49.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1216 1.36% 50.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 947 1.06% 51.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1180 1.32% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 650 0.72% 53.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 587 0.65% 54.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 521 0.58% 54.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 703 0.78% 55.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 336 0.37% 55.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 268 0.30% 56.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 216 0.24% 56.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 509 0.57% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 151 0.17% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 159 0.18% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 138 0.15% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 229 0.26% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 246 0.27% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 69 0.08% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 53 0.06% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 188 0.21% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 32 0.04% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 26 0.03% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 180 0.20% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 16 0.02% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 28 0.03% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 12 0.01% 61.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 150 0.17% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 27 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 112 0.12% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 11 0.01% 62.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 157 0.17% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 16 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 359 0.40% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 100 0.11% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 89 0.10% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 18 0.02% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 147 0.16% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 177 0.20% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 149 0.17% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 161 0.18% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 11 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 82 0.09% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 497 0.55% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 11 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 18 0.02% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 64 0.07% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 138 0.15% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 89 0.10% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 2 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 276 0.31% 65.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 33 0.04% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 146 0.16% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 83 0.09% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 65.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 526 0.59% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 79 0.09% 66.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 1 0.00% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 37 0.04% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 1 0.00% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 10 0.01% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 407 0.45% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 12 0.01% 66.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 33 0.04% 66.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 77 0.09% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 527 0.59% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 2 0.00% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 85 0.09% 67.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 150 0.17% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 29 0.03% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 279 0.31% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.09% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 6 0.01% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 13 0.01% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 496 0.55% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 2 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 77 0.09% 68.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 4 0.00% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 153 0.17% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 141 0.16% 69.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 1 0.00% 69.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 162 0.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 137 0.15% 69.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 74 0.08% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 90 0.10% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 343 0.38% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 145 0.16% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 2 0.00% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 90 0.10% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 2 0.00% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 133 0.15% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 164 0.18% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 153 0.17% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 1 0.00% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 162 0.18% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 88 0.10% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 278 0.31% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 83 0.09% 71.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 199 0.22% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 2 0.00% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 139 0.15% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 9 0.01% 71.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 416 0.46% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 138 0.15% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 203 0.23% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 87 0.10% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 275 0.31% 73.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 89 0.10% 73.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 73.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 155 0.17% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 155 0.17% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 162 0.18% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 2 0.00% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 131 0.15% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 2 0.00% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 93 0.10% 74.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 74.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 142 0.16% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 3 0.00% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 2 0.00% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 340 0.38% 74.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 81 0.09% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 77 0.09% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 2 0.00% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 134 0.15% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 2 0.00% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 164 0.18% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 141 0.16% 75.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 1 0.00% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20935 1 0.00% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 149 0.17% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 80 0.09% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 2 0.00% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 482 0.54% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 10 0.01% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 5 0.01% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22215 1 0.00% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 92 0.10% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 5 0.01% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 269 0.30% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 35 0.04% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 146 0.16% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 81 0.09% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 526 0.59% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 74 0.08% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 36 0.04% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 12 0.01% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 404 0.45% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 7 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 28 0.03% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 84 0.09% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 7 0.01% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 523 0.58% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 80 0.09% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 152 0.17% 78.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 32 0.04% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 4 0.00% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.09% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 3 0.00% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 17 0.02% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 484 0.54% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 1 0.00% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 77 0.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 152 0.17% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 1 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 140 0.16% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 163 0.18% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 2 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 130 0.14% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 75 0.08% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 86 0.10% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 3 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 336 0.37% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 140 0.16% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 2 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 91 0.10% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30407 1 0.00% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 134 0.15% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 156 0.17% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 152 0.17% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 157 0.17% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 2 0.00% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 86 0.10% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 272 0.30% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 83 0.09% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 202 0.23% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 144 0.16% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 2 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 415 0.46% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 148 0.16% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 208 0.23% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 2 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 85 0.09% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 2 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 270 0.30% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 85 0.09% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 157 0.17% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 152 0.17% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34624-34631 2 0.00% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 147 0.16% 85.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 134 0.15% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 90 0.10% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35392-35399 2 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 4 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35520-35527 1 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 143 0.16% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 337 0.38% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 82 0.09% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 76 0.08% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 131 0.15% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 154 0.17% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 139 0.15% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 153 0.17% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 2 0.00% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 81 0.09% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37760-37767 2 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 483 0.54% 87.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 12 0.01% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.09% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 271 0.30% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 30 0.03% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 152 0.17% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 3 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 86 0.10% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 521 0.58% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 77 0.09% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 28 0.03% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 10 0.01% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 402 0.45% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 9 0.01% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 35 0.04% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 4 0.00% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 79 0.09% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 523 0.58% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 79 0.09% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 146 0.16% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 34 0.04% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 269 0.30% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 89 0.10% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 3 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 13 0.01% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 1 0.00% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 482 0.54% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 78 0.09% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 151 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 138 0.15% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 3 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 153 0.17% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 134 0.15% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 77 0.09% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 341 0.38% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 2 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 140 0.16% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 93 0.10% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 133 0.15% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 149 0.17% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 156 0.17% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 157 0.17% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 88 0.10% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 298 0.33% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 110 0.12% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 200 0.22% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 70 0.08% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 136 0.15% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 9 0.01% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5002 5.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89727 # Bytes accessed per row activation +system.physmem.totQLat 373414318500 # Total ticks spent queuing +system.physmem.totMemAccLat 469593144750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18713571250 # Total ticks spent accessing banks +system.physmem.avgQLat 24102.05 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1207.87 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30309.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.98 # Data bus utilization in percentage +system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing +system.physmem.readRowHits 15419103 # Number of row buffer hits during reads +system.physmem.writeRowHits 91153 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.23 # Row buffer hit rate for writes +system.physmem.avgGap 160458.28 # Average gap between requests +system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -459,49 +658,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54136917 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546596 # Transaction distribution -system.membus.trans_dist::ReadResp 16546596 # Transaction distribution +system.membus.throughput 54116520 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546551 # Transaction distribution +system.membus.trans_dist::ReadResp 16546551 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57971 # Transaction distribution +system.membus.trans_dist::Writeback 57909 # Transaction distribution system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132250 # Transaction distribution -system.membus.trans_dist::ReadExResp 132250 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 132216 # Transaction distribution +system.membus.trans_dist::ReadExResp 132216 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141606813 # Total data (bytes) +system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141597849 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910601500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950348835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34633819250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -509,13 +708,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47816267 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution +system.iobus.throughput 47801275 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution system.iobus.trans_dist::WriteResp 8166 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -537,12 +736,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -564,14 +763,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073785 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073781 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -617,32 +816,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42037561750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996146 # DTB read hits -system.cpu.dtb.read_misses 7341 # DTB read misses -system.cpu.dtb.write_hits 11230467 # DTB write hits -system.cpu.dtb.write_misses 2217 # DTB write misses +system.cpu.dtb.read_hits 14995644 # DTB read hits +system.cpu.dtb.read_misses 7334 # DTB read misses +system.cpu.dtb.write_hits 11230146 # DTB write hits +system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3498 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 197 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003487 # DTB read accesses -system.cpu.dtb.write_accesses 11232684 # DTB write accesses +system.cpu.dtb.read_accesses 15002978 # DTB read accesses +system.cpu.dtb.write_accesses 11232358 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226613 # DTB hits -system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236171 # DTB accesses -system.cpu.itb.inst_hits 61492923 # ITB inst hits +system.cpu.dtb.hits 26225790 # DTB hits +system.cpu.dtb.misses 9546 # DTB misses +system.cpu.dtb.accesses 26235336 # DTB accesses +system.cpu.itb.inst_hits 61491413 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -659,79 +858,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61497394 # ITB inst accesses -system.cpu.itb.hits 61492923 # DTB hits +system.cpu.itb.inst_accesses 61495884 # ITB inst accesses +system.cpu.itb.hits 61491413 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61497394 # DTB accesses -system.cpu.numCycles 5231432444 # number of cpu cycles simulated +system.cpu.itb.accesses 61495884 # DTB accesses +system.cpu.numCycles 5233072966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60199078 # Number of instructions committed -system.cpu.committedOps 76605946 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872726 # Number of integer alu accesses +system.cpu.committedInsts 60197580 # Number of instructions committed +system.cpu.committedOps 76603973 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68871033 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140465 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948429 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872726 # number of integer instructions +system.cpu.num_func_calls 2140403 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948247 # number of instructions that are conditional controls +system.cpu.num_int_insts 68871033 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394779183 # number of times the integer registers were read -system.cpu.num_int_register_writes 74182470 # number of times the integer registers were written +system.cpu.num_int_register_reads 394768801 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180798 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394080 # number of memory refs -system.cpu.num_load_insts 15660200 # Number of load instructions -system.cpu.num_store_insts 11733880 # Number of store instructions -system.cpu.num_idle_cycles 4581975478.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649456965.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124145 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875855 # Percentage of idle cycles +system.cpu.num_mem_refs 27393280 # number of memory refs +system.cpu.num_load_insts 15659727 # Number of load instructions +system.cpu.num_store_insts 11733553 # Number of store instructions +system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles +system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles +system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875495 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856273 # number of replacements -system.cpu.icache.tags.tagsinuse 510.884220 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60636138 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856785 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.771708 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19799760250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.884220 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997821 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60636138 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60636138 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60636138 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60636138 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60636138 # number of overall hits -system.cpu.icache.overall_hits::total 60636138 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856785 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856785 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856785 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856785 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856785 # number of overall misses -system.cpu.icache.overall_misses::total 856785 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11770019500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11770019500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11770019500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11770019500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11770019500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11770019500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61492923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61492923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61492923 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61492923 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61492923 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61492923 # number of overall (read+write) accesses +system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 856254 # number of replacements +system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60634647 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856766 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.771537 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60634647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60634647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60634647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60634647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60634647 # number of overall hits +system.cpu.icache.overall_hits::total 60634647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856766 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856766 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856766 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856766 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856766 # number of overall misses +system.cpu.icache.overall_misses::total 856766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773893500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11773893500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11773893500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11773893500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11773893500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11773893500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13737.424792 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13737.424792 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13737.424792 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13737.424792 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.251093 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13742.251093 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13742.251093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13742.251093 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,174 +939,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856785 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856785 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856785 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856785 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856785 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856785 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051263500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10051263500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051263500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10051263500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051263500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10051263500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 414413750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856766 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856766 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856766 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856766 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856766 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856766 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056315500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056315500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056315500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056315500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 435321250 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.371931 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.371931 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.528683 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.528683 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62587 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50733.810806 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1683077 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127973 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.151813 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2564904211000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37696.862224 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6998.396772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6034.666541 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 62509 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50754.670173 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1682271 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.153944 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.408308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.399948 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.976844 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106787 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.092082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.774137 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844543 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370162 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226960 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595785 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595785 # number of Writeback hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844545 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369635 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226417 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595234 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595234 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113425 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113425 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8720 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3535 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844543 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 483587 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340385 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8720 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3535 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844543 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 483587 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340385 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113385 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113385 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8705 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3532 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 844545 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 483020 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1339802 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8705 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3532 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844545 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 483020 # number of overall hits +system.cpu.l2cache.overall_hits::total 1339802 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10601 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9837 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20445 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133893 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133893 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2907 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2907 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10601 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143730 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154338 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143633 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154225 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10601 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143730 # number of overall misses -system.cpu.l2cache.overall_misses::total 154338 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 390500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747407000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 696870750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1444790750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 470980 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 470980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8609068107 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8609068107 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 390500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 747407000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9305938857 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10053858857 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 390500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 747407000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9305938857 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10053858857 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3537 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 855144 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 379999 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247405 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595785 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595785 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247318 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247318 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8725 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3537 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 855144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627317 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494723 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8725 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3537 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 855144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627317 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494723 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012397 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016390 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541380 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541380 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012397 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229119 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103255 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012397 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229119 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103255 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78100 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70503.443071 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70841.796279 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70667.192468 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.990251 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.990251 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64298.119446 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64298.119446 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65141.824159 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65141.824159 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143633 # number of overall misses +system.cpu.l2cache.overall_misses::total 154225 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752463500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 738211000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1491129750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9619522392 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9619522392 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 752463500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10357733392 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11110652142 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 752463500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10357733392 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11110652142 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855130 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 379444 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595234 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595234 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2933 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247209 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247209 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8710 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3534 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 855130 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 626653 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494027 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8710 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3534 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855130 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 626653 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494027 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025851 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991135 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991135 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541340 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541340 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229207 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103228 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229207 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103228 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71087.718470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75258.538077 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73091.012695 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.671827 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.671827 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71881.892575 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71881.892575 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71087.718470 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72112.490806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72041.835902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71087.718470 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72112.490806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72041.835902 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -916,92 +1115,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57971 # number of writebacks -system.cpu.l2cache.writebacks::total 57971 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57909 # number of writebacks +system.cpu.l2cache.writebacks::total 57909 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10601 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9837 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20445 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133893 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133893 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2907 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2907 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10601 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143730 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154338 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143633 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154225 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10601 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143730 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154338 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 326500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 613945500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 572634250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1187003750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28725872 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28725872 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6933351393 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6933351393 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 326500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 613945500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7505985643 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8120355143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 326500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 613945500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7505985643 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8120355143 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 322980250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657157250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166980137500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702542535 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702542535 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 322980250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359699785 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183682680035 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025887 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016390 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541380 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541380 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103255 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103255 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57913.923215 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58212.285250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58058.388359 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.044568 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.044568 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51782.777240 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51782.777240 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143633 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154225 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619898500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 615330500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1235596750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29079907 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29079907 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7944865608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7944865608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619898500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8560196108 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9180462358 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619898500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8560196108 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9180462358 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 343871250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166656947250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167000818500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702635650 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702635650 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 343871250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359582900 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183703454150 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991135 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991135 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103228 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103228 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58563.863958 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62731.216230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60565.499240 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.407981 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.407981 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59368.017755 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59368.017755 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1011,79 +1210,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626805 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.881003 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655596 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 627317 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.709158 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 640871250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.881003 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999768 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195774 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195774 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972821 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972821 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168595 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168595 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168595 # number of overall hits -system.cpu.dcache.overall_hits::total 23168595 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250216 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250216 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618715 # number of overall misses -system.cpu.dcache.overall_misses::total 618715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5384538000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5384538000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10623511265 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10623511265 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158750500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158750500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16008049265 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16008049265 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16008049265 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16008049265 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564273 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564273 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223037 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223037 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787310 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787310 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787310 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787310 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027167 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027167 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024476 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024476 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14612.083072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14612.083072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42457.361899 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42457.361899 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13804.391304 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25873.058298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency +system.cpu.dcache.tags.replacements 626141 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655438 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.748863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195736 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195736 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236394 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236394 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168333 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168333 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168333 # number of overall hits +system.cpu.dcache.overall_hits::total 23168333 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250142 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250142 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11385 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11385 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618201 # number of overall misses +system.cpu.dcache.overall_misses::total 618201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416878250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5416878250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621403015 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11621403015 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158363750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158363750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17038281265 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17038281265 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17038281265 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17038281265 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23786534 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23786534 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23786534 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23786534 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045948 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045948 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025990 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025990 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025990 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025990 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14717.418267 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14717.418267 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46459.223221 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46459.223221 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.859464 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.859464 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27561.070372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27561.070372 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1092,54 +1291,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595785 # number of writebacks -system.cpu.dcache.writebacks::total 595785 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250216 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250216 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10058410735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135673500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135673500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14701227235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14701227235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595234 # number of writebacks +system.cpu.dcache.writebacks::total 595234 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250142 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250142 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11385 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11385 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678465750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678465750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069177985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069177985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135539250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135539250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747643735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15747643735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045948 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045948 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025990 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025990 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12711.184212 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12711.184212 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44251.577044 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44251.577044 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11905.072464 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.072464 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1147,37 +1346,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution +system.cpu.toL2Bus.throughput 52965120 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454582 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454582 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247209 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514380 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54754804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138418857 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138418857 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3008581500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295429750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534385915 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1193,10 +1392,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1538389615750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1538389615750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index e69bdd504..79d47dc5b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,131 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.192278 # Number of seconds simulated -sim_ticks 5192277855000 # Number of ticks simulated -final_tick 5192277855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196390 # Number of seconds simulated +sim_ticks 5196390180000 # Number of ticks simulated +final_tick 5196390180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 964497 # Simulator instruction rate (inst/s) -host_op_rate 1859169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39021883302 # Simulator tick rate (ticks/s) -host_mem_usage 587612 # Number of bytes of host memory used -host_seconds 133.06 # Real time elapsed on the host -sim_insts 128336541 # Number of instructions simulated -sim_ops 247382226 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2866368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +host_inst_rate 893068 # Simulator instruction rate (inst/s) +host_op_rate 1721530 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36161085452 # Simulator tick rate (ticks/s) +host_mem_usage 586592 # Number of bytes of host memory used +host_seconds 143.70 # Real time elapsed on the host +sim_insts 128334813 # Number of instructions simulated +sim_ops 247385808 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2883712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9005696 # Number of bytes read from this memory -system.physmem.bytes_read::total 12698368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8111936 # Number of bytes written to this memory -system.physmem.bytes_written::total 8111936 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8989184 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8110912 # Number of bytes written to this memory +system.physmem.bytes_written::total 8110912 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45058 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140714 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198412 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126749 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126749 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 552044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198404 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126733 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126733 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1734440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2445626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1562308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1562308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1562308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 552044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1729890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2443592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1560874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1734440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4007933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198412 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 126749 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 198412 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 126749 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 12698368 # Total number of bytes read from memory -system.physmem.bytesWritten 8111936 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12698368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8111936 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1635 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12070 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 11839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 11744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12175 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8067 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8252 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7644 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8073 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7938 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7649 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 5192277790500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198412 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126749 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1087 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 158670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1729890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4004466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198404 # Number of read requests accepted +system.physmem.writeReqs 126733 # Number of write requests accepted +system.physmem.readBursts 198404 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126733 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12694144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue +system.physmem.bytesWritten 8109888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12697856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8110912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1616 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12580 # Per bank write bursts +system.physmem.perBankRdBursts::1 12146 # Per bank write bursts +system.physmem.perBankRdBursts::2 12820 # Per bank write bursts +system.physmem.perBankRdBursts::3 12639 # Per bank write bursts +system.physmem.perBankRdBursts::4 12420 # Per bank write bursts +system.physmem.perBankRdBursts::5 12033 # Per bank write bursts +system.physmem.perBankRdBursts::6 12032 # Per bank write bursts +system.physmem.perBankRdBursts::7 12154 # Per bank write bursts +system.physmem.perBankRdBursts::8 12328 # Per bank write bursts +system.physmem.perBankRdBursts::9 11842 # Per bank write bursts +system.physmem.perBankRdBursts::10 12289 # Per bank write bursts +system.physmem.perBankRdBursts::11 12385 # Per bank write bursts +system.physmem.perBankRdBursts::12 12618 # Per bank write bursts +system.physmem.perBankRdBursts::13 13039 # Per bank write bursts +system.physmem.perBankRdBursts::14 12508 # Per bank write bursts +system.physmem.perBankRdBursts::15 12513 # Per bank write bursts +system.physmem.perBankWrBursts::0 8180 # Per bank write bursts +system.physmem.perBankWrBursts::1 7837 # Per bank write bursts +system.physmem.perBankWrBursts::2 8283 # Per bank write bursts +system.physmem.perBankWrBursts::3 8150 # Per bank write bursts +system.physmem.perBankWrBursts::4 7961 # Per bank write bursts +system.physmem.perBankWrBursts::5 7589 # Per bank write bursts +system.physmem.perBankWrBursts::6 7480 # Per bank write bursts +system.physmem.perBankWrBursts::7 7728 # Per bank write bursts +system.physmem.perBankWrBursts::8 7696 # Per bank write bursts +system.physmem.perBankWrBursts::9 7447 # Per bank write bursts +system.physmem.perBankWrBursts::10 7846 # Per bank write bursts +system.physmem.perBankWrBursts::11 7788 # Per bank write bursts +system.physmem.perBankWrBursts::12 8080 # Per bank write bursts +system.physmem.perBankWrBursts::13 8539 # Per bank write bursts +system.physmem.perBankWrBursts::14 8032 # Per bank write bursts +system.physmem.perBankWrBursts::15 8081 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5196390116500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 198404 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 126733 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 155323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 52 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -137,296 +139,310 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 459.065810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.635945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1572.397321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 18574 41.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7178 15.85% 56.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4205 9.28% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2900 6.40% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1973 4.36% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1677 3.70% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1250 2.76% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1043 2.30% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 738 1.63% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 608 1.34% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 523 1.15% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 460 1.02% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 307 0.68% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 311 0.69% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 233 0.51% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 396 0.87% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 152 0.34% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 138 0.30% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 115 0.25% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 132 0.29% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 133 0.29% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 129 0.28% 95.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 607 1.34% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 165 0.36% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 95 0.21% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 80 0.18% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 50 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 52 0.11% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 21 0.05% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 24 0.05% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 26 0.06% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 33 0.07% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 17 0.04% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 17 0.04% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 9 0.02% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 10 0.02% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 5 0.01% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 8 0.02% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 10 0.02% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 7 0.02% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.00% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 11 0.02% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 3 0.01% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 12 0.03% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 18 0.04% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 7 0.02% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 3 0.01% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 3 0.01% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 3 0.01% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 10 0.02% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 3 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 3 0.01% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 7 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 244 0.54% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 12 0.03% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17155 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17283 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45297 # Bytes accessed per row activation -system.physmem.totQLat 3410755000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7054990000 # Sum of mem lat for all requests -system.physmem.totBusLat 991695000 # Total cycles spent in databus access -system.physmem.totBankLat 2652540000 # Total cycles spent in bank access -system.physmem.avgQLat 17196.59 # Average queueing delay per request -system.physmem.avgBankLat 13373.77 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35570.36 # Average memory access latency -system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 5072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 20 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 53708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.265063 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.541838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1283.636288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 22377 41.66% 41.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 8801 16.39% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5780 10.76% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3435 6.40% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2322 4.32% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1859 3.46% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1339 2.49% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1034 1.93% 87.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 806 1.50% 88.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 663 1.23% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 546 1.02% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 427 0.80% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 325 0.61% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 307 0.57% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 277 0.52% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 550 1.02% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 185 0.34% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 190 0.35% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 112 0.21% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 109 0.20% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 125 0.23% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 422 0.79% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 149 0.28% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.16% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 55 0.10% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 85 0.16% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 52 0.10% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 36 0.07% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 25 0.05% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 24 0.04% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 18 0.03% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 26 0.05% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 25 0.05% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 20 0.04% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.02% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 14 0.03% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 11 0.02% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 14 0.03% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 11 0.02% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 9 0.02% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 10 0.02% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 13 0.02% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 26 0.05% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 12 0.02% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 9 0.02% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 19 0.04% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 10 0.02% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 9 0.02% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 12 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 12 0.02% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 15 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 10 0.02% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 20 0.04% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 13 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 24 0.04% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 11 0.02% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 19 0.04% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 10 0.02% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 13 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 7 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 9 0.02% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 11 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 7 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 9 0.02% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 9 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 10 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 9 0.02% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 7 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 9 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 7 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 5 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 13 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 8 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 7 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 8 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 10 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 5 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 9 0.02% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 151 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 4 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 19 0.04% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 4 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 14 0.03% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 4 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 4 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 6 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 32 0.06% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 178 0.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 53708 # Bytes accessed per row activation +system.physmem.totQLat 5080719250 # Total ticks spent queuing +system.physmem.totMemAccLat 8752324250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 991730000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2679875000 # Total ticks spent accessing banks +system.physmem.avgQLat 25615.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13511.11 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 44126.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.08 # Average write queue length over time -system.physmem.readRowHits 181292 # Number of row buffer hits during reads -system.physmem.writeRowHits 98480 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.70 # Row buffer hit rate for writes -system.physmem.avgGap 15968328.89 # Average gap between requests -system.membus.throughput 4372413 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623536 # Transaction distribution -system.membus.trans_dist::ReadResp 623536 # Transaction distribution -system.membus.trans_dist::WriteReq 13773 # Transaction distribution -system.membus.trans_dist::WriteResp 13773 # Transaction distribution -system.membus.trans_dist::Writeback 126749 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2152 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution -system.membus.trans_dist::ReadExReq 159747 # Transaction distribution -system.membus.trans_dist::ReadExResp 159747 # Transaction distribution -system.membus.trans_dist::MessageReq 1654 # Transaction distribution -system.membus.trans_dist::MessageResp 1654 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.98 # Average write queue length when enqueuing +system.physmem.readRowHits 173438 # Number of row buffer hits during reads +system.physmem.writeRowHits 97917 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.26 # Row buffer hit rate for writes +system.physmem.avgGap 15982155.57 # Average gap between requests +system.physmem.pageHitRate 83.47 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.27 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 4365247 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623514 # Transaction distribution +system.membus.trans_dist::ReadResp 623514 # Transaction distribution +system.membus.trans_dist::WriteReq 13775 # Transaction distribution +system.membus.trans_dist::WriteResp 13775 # Transaction distribution +system.membus.trans_dist::Writeback 126733 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1634 # Transaction distribution +system.membus.trans_dist::ReadExReq 159484 # Transaction distribution +system.membus.trans_dist::ReadExResp 159484 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391769 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1582207 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1724531 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1724207 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14957248 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16623909 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5853056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5853056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22483581 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22483581 # Total data (bytes) -system.membus.snoop_data_through_bus 219200 # Total snoop data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14938368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16605037 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5870400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5870400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22482057 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22482057 # Total data (bytes) +system.membus.snoop_data_through_bus 201472 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 256796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 359311000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 359316000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1350436000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1352149000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2614907754 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2612327754 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 428881000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 428873750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47507 # number of replacements -system.iocache.tags.tagsinuse 0.110729 # Cycle average of tags in use +system.iocache.tags.replacements 47501 # number of replacements +system.iocache.tags.tagsinuse 0.113099 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5049641350000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.110729 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006921 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006921 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses -system.iocache.ReadReq_misses::total 842 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5049776837000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.113099 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007069 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007069 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses -system.iocache.demand_misses::total 47562 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses -system.iocache.overall_misses::total 47562 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 148613936 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 148613936 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10808111078 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10808111078 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10956725014 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10956725014 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10956725014 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10956725014 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses +system.iocache.demand_misses::total 47556 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses +system.iocache.overall_misses::total 47556 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144134686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144134686 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12487439330 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12487439330 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 12631574016 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12631574016 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 12631574016 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12631574016 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -435,40 +451,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 176501.111639 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 176501.111639 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 231337.993964 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 231337.993964 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 230367.205206 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 230367.205206 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 172843 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 172409.911483 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 267282.519906 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 265614.728236 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 265614.728236 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 216457 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 15866 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11594 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.893924 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 18.669743 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104797436 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104797436 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8377057578 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8377057578 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8481855014 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8481855014 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100637686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100637686 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10056284830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10056284830 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10156922516 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10156922516 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -477,14 +493,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 124462.513064 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 124462.513064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 179303.458433 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 179303.458433 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -498,13 +514,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 631773 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230147 # Transaction distribution -system.iobus.trans_dist::ReadResp 230147 # Transaction distribution +system.iobus.throughput 631264 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230141 # Transaction distribution +system.iobus.trans_dist::ReadResp 230141 # Transaction distribution system.iobus.trans_dist::WriteReq 57579 # Transaction distribution system.iobus.trans_dist::WriteResp 57579 # Transaction distribution -system.iobus.trans_dist::MessageReq 1654 # Transaction distribution -system.iobus.trans_dist::MessageResp 1654 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -524,11 +540,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578750 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -548,13 +564,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280340 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280340 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3946566 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3280296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280296 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3948164 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -590,87 +606,87 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424359014 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424033266 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53490000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52989250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.numCycles 10384555710 # number of cpu cycles simulated +system.cpu.numCycles 10392780360 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128336541 # Number of instructions committed -system.cpu.committedOps 247382226 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231975048 # Number of integer alu accesses +system.cpu.committedInsts 128334813 # Number of instructions committed +system.cpu.committedOps 247385808 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231978567 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299863 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23167946 # number of instructions that are conditional controls -system.cpu.num_int_insts 231975048 # number of integer instructions +system.cpu.num_func_calls 2299773 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23169265 # number of instructions that are conditional controls +system.cpu.num_int_insts 231978567 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434515715 # number of times the integer registers were read -system.cpu.num_int_register_writes 197846848 # number of times the integer registers were written +system.cpu.num_int_register_reads 434513747 # number of times the integer registers were read +system.cpu.num_int_register_writes 197852200 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132806307 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95529498 # number of times the CC registers were written -system.cpu.num_mem_refs 22249600 # number of memory refs -system.cpu.num_load_insts 13881232 # Number of load instructions -system.cpu.num_store_insts 8368368 # Number of store instructions -system.cpu.num_idle_cycles 9777359201.998117 # Number of idle cycles -system.cpu.num_busy_cycles 607196508.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058471 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941529 # Percentage of idle cycles +system.cpu.num_cc_register_reads 132813019 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95534921 # number of times the CC registers were written +system.cpu.num_mem_refs 22245363 # number of memory refs +system.cpu.num_load_insts 13878746 # Number of load instructions +system.cpu.num_store_insts 8366617 # Number of store instructions +system.cpu.num_idle_cycles 9785238216.998117 # Number of idle cycles +system.cpu.num_busy_cycles 607542143.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058458 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941542 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 792807 # number of replacements -system.cpu.icache.tags.tagsinuse 510.358419 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144581557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 793319 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.248953 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161241203250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.358419 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996794 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996794 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144581557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144581557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144581557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144581557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144581557 # number of overall hits -system.cpu.icache.overall_hits::total 144581557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 793326 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 793326 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 793326 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 793326 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 793326 # number of overall misses -system.cpu.icache.overall_misses::total 793326 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11210417756 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11210417756 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11210417756 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11210417756 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11210417756 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11210417756 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145374883 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145374883 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145374883 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145374883 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145374883 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145374883 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005457 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005457 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005457 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005457 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005457 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005457 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14130.909306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14130.909306 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14130.909306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14130.909306 # average overall miss latency +system.cpu.icache.tags.replacements 788090 # number of replacements +system.cpu.icache.tags.tagsinuse 510.351939 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144584753 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 788602 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 183.343122 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161436066250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.351939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996781 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144584753 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144584753 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144584753 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144584753 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144584753 # number of overall hits +system.cpu.icache.overall_hits::total 144584753 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 788609 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 788609 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 788609 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 788609 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 788609 # number of overall misses +system.cpu.icache.overall_misses::total 788609 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11107362758 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11107362758 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11107362758 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11107362758 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11107362758 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11107362758 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145373362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145373362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145373362 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145373362 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145373362 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145373362 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005425 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005425 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005425 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005425 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005425 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005425 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14084.752720 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14084.752720 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -679,80 +695,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793326 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793326 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793326 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793326 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793326 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793326 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9617488244 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9617488244 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9617488244 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9617488244 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9617488244 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9617488244 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005457 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005457 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005457 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12122.996402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12122.996402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788609 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 788609 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 788609 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 788609 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 788609 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 788609 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9525299242 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9525299242 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9525299242 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9525299242 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9525299242 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9525299242 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005425 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005425 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005425 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3898 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.066238 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7439 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3908 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.903531 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5166941674000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066238 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191640 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191640 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7461 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7461 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 3741 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.069761 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7617 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3752 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.030117 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069761 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191860 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191860 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7617 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7617 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7463 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7463 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7463 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7463 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4754 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4754 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4754 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4754 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4754 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4754 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48555250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48555250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48555250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 48555250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48555250 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 48555250 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12215 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12215 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7619 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7619 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7619 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7619 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4604 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4604 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4604 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4604 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4604 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4604 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 44886750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 44886750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12217 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12217 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12217 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12217 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.389194 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.389194 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.389130 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.389130 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.389130 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.389130 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10213.557005 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10213.557005 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10213.557005 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376729 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376729 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376667 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.376667 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376667 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.376667 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9749.511295 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9749.511295 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9749.511295 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,78 +777,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 837 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 837 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4754 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4754 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4754 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4754 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4754 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4754 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39044750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39044750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39044750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39044750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39044750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39044750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.389194 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.389194 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.389130 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.389130 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8213.031132 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 621 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 621 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4604 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4604 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4604 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4604 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4604 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4604 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35677750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35677750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35677750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35677750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35677750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35677750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376729 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376729 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376667 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376667 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7749.294092 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7667 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.048611 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13083 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7683 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.702850 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163398099000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.048611 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315538 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315538 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13083 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13083 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13083 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13083 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13083 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13083 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8874 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8874 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8874 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8874 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8874 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8874 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95939000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95939000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95939000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 95939000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95939000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 95939000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21957 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21957 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21957 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21957 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21957 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21957 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404154 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404154 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404154 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404154 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404154 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404154 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10811.246338 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10811.246338 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10811.246338 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 7948 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052475 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12793 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7961 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.606959 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052475 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315780 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315780 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12806 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12806 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12806 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12806 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12806 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12806 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9138 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9138 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9138 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9138 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9138 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9138 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97347500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97347500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97347500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 97347500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97347500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 97347500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21944 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21944 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21944 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21944 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21944 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21944 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.416424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.416424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.416424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.416424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.416424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.416424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -841,90 +857,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2999 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2999 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8874 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8874 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8874 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8874 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8874 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78190500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78190500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78190500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78190500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404154 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404154 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404154 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8811.189993 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8811.189993 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8811.189993 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9138 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9138 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9138 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9138 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9138 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9138 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 79071000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 79071000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 79071000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 79071000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 79071000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 79071000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.416424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.416424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.416424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8652.987525 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622533 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997176 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20039030 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623045 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.346565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 49459250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997176 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1621547 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997026 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20035701 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622059 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.352017 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 50992250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997026 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11994437 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11994437 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8042382 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8042382 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20036819 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20036819 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20036819 # number of overall hits -system.cpu.dcache.overall_hits::total 20036819 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309601 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309601 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315672 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315672 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1625273 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1625273 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1625273 # number of overall misses -system.cpu.dcache.overall_misses::total 1625273 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18886188795 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18886188795 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10748063695 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10748063695 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29634252490 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29634252490 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29634252490 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29634252490 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13304038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13304038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8358054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8358054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21662092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21662092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21662092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21662092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037769 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037769 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075028 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075028 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075028 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075028 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14421.330462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14421.330462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34048.200965 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34048.200965 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18233.399860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18233.399860 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11993197 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11993197 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8040328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8040328 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20033525 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20033525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20033525 # number of overall hits +system.cpu.dcache.overall_hits::total 20033525 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308312 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308312 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315974 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315974 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624286 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624286 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624286 # number of overall misses +system.cpu.dcache.overall_misses::total 1624286 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18913909300 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18913909300 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11002078938 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11002078938 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29915988238 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29915988238 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29915988238 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29915988238 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13301509 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13301509 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8356302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8356302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21657811 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21657811 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21657811 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21657811 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18417.931471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18417.931471 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -933,46 +949,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539374 # number of writebacks -system.cpu.dcache.writebacks::total 1539374 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309601 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309601 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315672 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315672 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625273 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625273 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625273 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625273 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16253560205 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16253560205 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10061381305 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10061381305 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26314941510 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26314941510 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26314941510 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26314941510 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537247000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537247000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098436 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098436 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037769 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037769 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12411.078034 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12411.078034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31872.897517 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31872.897517 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538973 # number of writebacks +system.cpu.dcache.writebacks::total 1538973 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308312 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308312 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315974 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315974 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1624286 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1624286 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624286 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624286 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16288101700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16288101700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10316379062 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10316379062 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26604480762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26604480762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26604480762 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26604480762 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214673000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214673000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537491500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537491500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752164500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752164500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098358 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098358 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -980,175 +996,175 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49299027 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2698843 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2698315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543210 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 360181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313477 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1586639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7593504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50772032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204036453 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 621184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 255690853 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255669733 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 304512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3835424500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 49185341 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2692945 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2692419 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 360518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313820 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5977035 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7581359 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50470144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203948077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 225856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 630272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 255274349 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255253101 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 333120 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3831866500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 498000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1193127756 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1185336258 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3058413490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054054238 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 7132250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6906500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13311250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13707250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 86950 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64733.250589 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3493106 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151616 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.039165 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86910 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64731.196890 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3488433 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151626 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.006826 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50239.194329 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.026648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3379.223326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11114.665027 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.766589 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.033461 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3445.447212 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764778 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.051563 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169596 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987751 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6706 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 780407 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280531 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2070883 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543210 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543210 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 301 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 301 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200188 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200188 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6706 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3239 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 780407 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1480719 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2271071 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6706 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3239 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 780407 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1480719 # number of overall hits -system.cpu.l2cache.overall_hits::total 2271071 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052573 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.170366 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987720 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6740 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2903 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 775712 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279207 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2064562 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1542700 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1542700 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 304 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 304 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6740 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2903 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 775712 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1479959 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2265314 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6740 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2903 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 775712 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1479959 # number of overall hits +system.cpu.l2cache.overall_hits::total 2265314 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12906 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28336 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41248 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1410 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1410 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113269 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113269 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12884 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28341 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41232 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1356 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1356 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113042 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113042 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12906 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141605 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154517 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12884 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141383 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154274 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12906 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141605 # number of overall misses -system.cpu.l2cache.overall_misses::total 154517 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 390250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1020078744 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2137913705 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3158471949 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16387856 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16387856 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7707092698 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7707092698 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 390250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1020078744 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9845006403 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10865564647 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 390250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1020078744 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9845006403 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10865564647 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6707 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3244 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 793313 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308867 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2112131 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1543210 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1543210 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1711 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1711 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313457 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313457 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6707 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3244 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 793313 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1622324 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2425588 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6707 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 793313 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1622324 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2425588 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001541 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016268 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021649 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019529 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.824079 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.824079 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361354 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.361354 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000149 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001541 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016268 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087285 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000149 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001541 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016268 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087285 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78050 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79039.109252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75448.676772 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76572.729563 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11622.592908 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11622.592908 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68042.383159 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68042.383159 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79039.109252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69524.426419 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70319.541843 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79039.109252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69524.426419 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70319.541843 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12884 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141383 # number of overall misses +system.cpu.l2cache.overall_misses::total 154274 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 136750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 347500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 979557242 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2186954200 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3166995692 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16260363 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16260363 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7957275400 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7957275400 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 136750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 347500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 979557242 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10144229600 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11124271092 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 136750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 347500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 979557242 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10144229600 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11124271092 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6742 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2908 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 788596 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307548 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2105794 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1542700 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1542700 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1660 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1660 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313794 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313794 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6742 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 788596 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621342 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2419588 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6742 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2908 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 788596 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621342 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2419588 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000297 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001719 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016338 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021675 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019580 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.816867 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.816867 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360243 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.360243 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000297 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001719 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016338 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087201 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063760 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000297 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001719 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016338 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087201 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063760 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76028.969419 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77165.738682 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76809.169868 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11991.418142 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11991.418142 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70392.202898 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70392.202898 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72107.231886 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72107.231886 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1157,90 +1173,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80082 # number of writebacks -system.cpu.l2cache.writebacks::total 80082 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80066 # number of writebacks +system.cpu.l2cache.writebacks::total 80066 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12906 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28336 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41248 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1410 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1410 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113269 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113269 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12884 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28341 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41232 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1356 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1356 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113042 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113042 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12906 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141605 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154517 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12884 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141383 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154274 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12906 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141605 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154517 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 857244756 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1780461295 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2638108551 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14985893 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14985893 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6290141302 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6290141302 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 857244756 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8070602597 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8928249853 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 857244756 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8070602597 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8928249853 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026503500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026503500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021649 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019529 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.824079 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.824079 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087285 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063703 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087285 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063703 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66422.187820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62833.896633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63957.247648 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10628.292908 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10628.292908 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55532.769796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55532.769796 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66422.187820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56993.768560 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57781.667085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66422.187820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56993.768560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57781.667085 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12884 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141383 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154274 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 111250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 818022758 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1831787800 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2650206808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14478338 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14478338 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6543285600 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6543285600 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 111250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 285000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 818022758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8375073400 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9193492408 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 111250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 285000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 818022758 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8375073400 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9193492408 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370854000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370854000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026723500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026723500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816867 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816867 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063760 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063760 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63491.365880 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64633.844960 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64275.485254 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10677.240413 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10677.240413 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.668017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.668017 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index dde2aed4b..3b67933ac 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25046000 # Number of ticks simulated -final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25485000 # Number of ticks simulated +final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22373 # Simulator instruction rate (inst/s) -host_op_rate 22372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87684145 # Simulator tick rate (ticks/s) -host_mem_usage 225308 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 27492 # Simulator instruction rate (inst/s) +host_op_rate 27490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109632626 # Simulator tick rate (ticks/s) +host_mem_usage 225100 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29952 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25031500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 469 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 753384344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 421895232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1175279576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 753384344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 421895232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1175279576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65 # Per bank write bursts +system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::2 27 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 41 # Per bank write bursts +system.physmem.perBankRdBursts::5 19 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 19 # Per bank write bursts +system.physmem.perBankRdBursts::11 25 # Per bank write bursts +system.physmem.perBankRdBursts::12 15 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 46 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 25470500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 469 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -150,48 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation -system.physmem.totQLat 1857500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests -system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 7617500 # Total cycles spent in bank access -system.physmem.avgQLat 3960.55 # Average queueing delay per request -system.physmem.avgBankLat 16242.00 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25202.56 # Average memory access latency -system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.34 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.47 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 402 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.095238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.496730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.391602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 44.05% 44.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 14 16.67% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 5.95% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 5.95% 72.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 4.76% 77.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 5.95% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.19% 84.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.38% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.19% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.19% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 2 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.19% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 2 2.38% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 1.19% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.19% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 1.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 2272250 # Total ticks spent queuing +system.physmem.totMemAccLat 12262250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7645000 # Total ticks spent accessing banks +system.physmem.avgQLat 4844.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16300.64 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26145.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1177.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1177.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.20 # Data bus utilization in percentage +system.physmem.busUtilRead 9.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 385 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53372.07 # Average gap between requests -system.membus.throughput 1195879582 # Throughput (bytes/s) +system.physmem.avgGap 54308.10 # Average gap between requests +system.physmem.pageHitRate 82.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1175279576 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -202,10 +210,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.2 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -248,7 +256,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 50093 # number of cpu cycles simulated +system.cpu.numCycles 50971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). @@ -270,12 +278,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11614 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43595 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. -system.cpu.activity 14.724612 # Percentage of cycles cpu is active +system.cpu.activity 14.470974 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -287,36 +295,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.976682 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.976682 # CPI: Total CPI of All Threads +system.cpu.ipc 0.125365 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.125365 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46047 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.660395 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47078 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.637676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46810 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.163465 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 49637 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.617174 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46513 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 8.746150 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.311081 # Cycle average of tags in use system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -329,12 +337,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24550250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24550250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24550250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24550250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -347,12 +355,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69155.633803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69155.633803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69155.633803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -373,26 +381,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20718250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20718250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1177790857 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -407,21 +415,21 @@ system.cpu.toL2Bus.data_through_bus 30016 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 508750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.093004 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.347593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -439,17 +447,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20399750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27865000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20399750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12323000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32722750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20399750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12323000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32722750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -472,17 +480,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67773.255814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78581.578947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70366.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69771.321962 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69771.321962 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,17 +510,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16625250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6283250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16625250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10237500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26862750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16625250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10237500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26862750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -524,27 +532,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55233.388704 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66139.473684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57849.747475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.493430 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -561,14 +569,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7909250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7909250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21376500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21376500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29285750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29285750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -585,19 +593,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81538.659794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81538.659794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61075.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61075.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -617,14 +625,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12502000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12502000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -633,14 +641,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 31fc74f80..0ff2f61a7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20671000 # Number of ticks simulated -final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21065000 # Number of ticks simulated +final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10783 # Simulator instruction rate (inst/s) -host_op_rate 10783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34979840 # Simulator tick rate (ticks/s) -host_mem_usage 229184 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host +host_inst_rate 31290 # Simulator instruction rate (inst/s) +host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103426086 # Simulator tick rate (ticks/s) +host_mem_usage 226120 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 31168 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20638000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 488 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 950961310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 528649418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479610729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950961310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 528649418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479610729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 488 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69 # Per bank write bursts +system.physmem.perBankRdBursts::1 34 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 43 # Per bank write bursts +system.physmem.perBankRdBursts::5 21 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 24 # Per bank write bursts +system.physmem.perBankRdBursts::12 14 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 45 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21032000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 488 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,47 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation -system.physmem.totQLat 2449250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests -system.physmem.totBusLat 2440000 # Total cycles spent in databus access -system.physmem.totBankLat 7535000 # Total cycles spent in bank access -system.physmem.avgQLat 5018.95 # Average queueing delay per request -system.physmem.avgBankLat 15440.57 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25459.53 # Average memory access latency -system.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.78 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 419 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 85 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.023529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.928934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 483.454089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 43.53% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 9.41% 52.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 10 11.76% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7 8.24% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 3.53% 76.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 2.35% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 2.35% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 4.71% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.18% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.18% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 2.35% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.18% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.18% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 3 3.53% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.18% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 1.18% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85 # Bytes accessed per row activation +system.physmem.totQLat 3258750 # Total ticks spent queuing +system.physmem.totMemAccLat 13288750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7590000 # Total ticks spent accessing banks +system.physmem.avgQLat 6677.77 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15553.28 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27231.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1482.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1482.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.58 # Data bus utilization in percentage +system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 403 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42290.98 # Average gap between requests -system.membus.throughput 1507812878 # Throughput (bytes/s) +system.physmem.avgGap 43098.36 # Average gap between requests +system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1479610729 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -201,39 +210,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu.branchPred.lookups 2888 # Number of BP lookups -system.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 619000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.cpu.branchPred.lookups 2884 # Number of BP lookups +system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups -system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups +system.cpu.branchPred.BTBHits 756 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.363636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2082 # DTB read hits +system.cpu.dtb.read_hits 2076 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2129 # DTB read accesses +system.cpu.dtb.read_accesses 2123 # DTB read accesses system.cpu.dtb.write_hits 1063 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1094 # DTB write accesses -system.cpu.dtb.data_hits 3145 # DTB hits +system.cpu.dtb.data_hits 3139 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3223 # DTB accesses -system.cpu.itb.fetch_hits 2387 # ITB hits +system.cpu.dtb.data_accesses 3217 # DTB accesses +system.cpu.itb.fetch_hits 2382 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2426 # ITB accesses +system.cpu.itb.fetch_accesses 2421 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -247,178 +256,178 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41343 # number of cpu cycles simulated +system.cpu.numCycles 42131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16592 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2888 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2764 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 1219 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15308 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1219 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 808 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2623 # Number of cycles rename is running system.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 14604 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18241 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18225 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18216 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6381 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 808 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2766 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12953 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10771 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3598 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.712698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.354769 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10572 69.95% 69.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1678 11.10% 81.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1174 7.77% 88.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 4.82% 93.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 498 3.30% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 1.79% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7236 67.18% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2397 22.25% 89.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1133 10.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10787 # Type of FU issued -system.cpu.iq.rate 0.260915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 113 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10771 # Type of FU issued +system.cpu.iq.rate 0.255655 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010398 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19167 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9598 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10870 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1583 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed @@ -427,57 +436,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1219 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 264 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13071 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2766 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 704 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3236 # number of memory reference insts executed -system.cpu.iew.exec_branches 1591 # Number of branches executed +system.cpu.iew.exec_refs 3230 # number of memory reference insts executed +system.cpu.iew.exec_branches 1588 # Number of branches executed system.cpu.iew.exec_stores 1096 # Number of stores executed -system.cpu.iew.exec_rate 0.243983 # Inst execution rate -system.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9625 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5058 # num instructions producing a value -system.cpu.iew.wb_consumers 6775 # num instructions consuming a value +system.cpu.iew.exec_rate 0.238945 # Inst execution rate +system.cpu.iew.wb_sent 9751 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9608 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5048 # num instructions producing a value +system.cpu.iew.wb_consumers 6764 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.232808 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back +system.cpu.iew.wb_rate 0.228051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.746304 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6680 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13894 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.459839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11073 79.70% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1524 10.97% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 530 3.81% 94.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.69% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.07% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 0.79% 98.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 103 0.74% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.20% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13894 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -488,26 +497,26 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26435 # The number of ROB reads -system.cpu.rob.rob_writes 27385 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26469 # The number of ROB reads +system.cpu.rob.rob_writes 27366 # The number of ROB writes +system.cpu.timesIdled 271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27018 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.488230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads -system.cpu.ipc 0.154125 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12801 # number of integer regfile reads -system.cpu.int_regfile_writes 7277 # number of integer regfile writes +system.cpu.cpi 6.611896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.611896 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12780 # number of integer regfile reads +system.cpu.int_regfile_writes 7264 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1482648944 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -522,55 +531,55 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 278500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.548856 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1893 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.028662 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits -system.cpu.icache.overall_hits::total 1898 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1893 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1893 # number of overall hits +system.cpu.icache.overall_hits::total 1893 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31381500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31381500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31381500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31381500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2382 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2382 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2382 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2382 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.205290 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.205290 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.205290 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.205290 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64174.846626 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22109000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22109000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.420292 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.632644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -638,17 +647,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21783000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29501750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21783000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13109500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21783000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13109500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34892500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -671,17 +680,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71501.024590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71501.024590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -701,17 +710,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17830500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6478250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17830500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17830500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -723,35 +732,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.351368 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits -system.cpu.dcache.overall_hits::total 2236 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits +system.cpu.dcache.overall_hits::total 2230 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -760,43 +769,43 @@ system.cpu.dcache.demand_misses::cpu.data 529 # n system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses system.cpu.dcache.overall_misses::total 529 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11435000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11435000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23196228 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23196228 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34631228 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34631228 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.089757 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.191736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.030303 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -816,30 +825,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 2906fdf0c..5e19e4b84 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11933500 # Number of ticks simulated -final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11990500 # Number of ticks simulated +final_tick 11990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3639 # Simulator instruction rate (inst/s) -host_op_rate 3638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18189727 # Simulator tick rate (ticks/s) -host_mem_usage 227880 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 47015 # Simulator instruction rate (inst/s) +host_op_rate 46988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 235942636 # Simulator tick rate (ticks/s) +host_mem_usage 225832 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 17472 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11844000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 273 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.bw_read::cpu.inst 1003461073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 453692507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1457153580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1003461073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 453692507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1457153580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 17472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 17472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 2 # Per bank write bursts +system.physmem.perBankRdBursts::3 24 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 24 # Per bank write bursts +system.physmem.perBankRdBursts::7 37 # Per bank write bursts +system.physmem.perBankRdBursts::8 61 # Per bank write bursts +system.physmem.perBankRdBursts::9 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 14 # Per bank write bursts +system.physmem.perBankRdBursts::11 9 # Per bank write bursts +system.physmem.perBankRdBursts::12 17 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 12 # Per bank write bursts +system.physmem.perBankRdBursts::15 1 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 11901000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 273 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,43 +152,51 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation -system.physmem.totQLat 1190000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests -system.physmem.totBusLat 1365000 # Total cycles spent in databus access -system.physmem.totBankLat 4180000 # Total cycles spent in bank access -system.physmem.avgQLat 4358.97 # Average queueing delay per request -system.physmem.avgBankLat 15311.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24670.33 # Average memory access latency -system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.44 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.56 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 240 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 42 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.809524 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.784505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 471.889985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 23 54.76% 54.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 1 2.38% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 3 7.14% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 1 2.38% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.76% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 2.38% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 4.76% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.38% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 2.38% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 2.38% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 2.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42 # Bytes accessed per row activation +system.physmem.totQLat 1695750 # Total ticks spent queuing +system.physmem.totMemAccLat 7213250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers +system.physmem.totBankLat 4152500 # Total ticks spent accessing banks +system.physmem.avgQLat 6211.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15210.62 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26422.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1457.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1457.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.38 # Data bus utilization in percentage +system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.60 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 231 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43384.62 # Average gap between requests -system.membus.throughput 1464113630 # Throughput (bytes/s) +system.physmem.avgGap 43593.41 # Average gap between requests +system.physmem.pageHitRate 84.62 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1457153580 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -199,10 +209,10 @@ system.membus.data_through_bus 17472 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1175 # Number of BP lookups -system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted +system.membus.respLayer1.occupancy 2551500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.3 # Layer utilization (%) +system.cpu.branchPred.lookups 1176 # Number of BP lookups +system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups system.cpu.branchPred.BTBHits 253 # Number of BTB hits @@ -218,18 +228,18 @@ system.cpu.dtb.read_hits 707 # DT system.cpu.dtb.read_misses 31 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations system.cpu.dtb.read_accesses 738 # DTB read accesses -system.cpu.dtb.write_hits 371 # DTB write hits +system.cpu.dtb.write_hits 368 # DTB write hits system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 391 # DTB write accesses -system.cpu.dtb.data_hits 1078 # DTB hits +system.cpu.dtb.write_accesses 388 # DTB write accesses +system.cpu.dtb.data_hits 1075 # DTB hits system.cpu.dtb.data_misses 51 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.dtb.data_accesses 1126 # DTB accesses +system.cpu.itb.fetch_hits 1065 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1097 # ITB accesses +system.cpu.itb.fetch_accesses 1095 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -243,96 +253,96 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23868 # number of cpu cycles simulated +system.cpu.numCycles 23982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 4347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.908161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.314945 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6511 84.34% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1156 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049037 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5584 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1065 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1062 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5897 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6679 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 4276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6670 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6663 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2508 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 955 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 468 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4960 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued +system.cpu.iq.iqInstsIssued 4040 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1384 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.523316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.238697 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6098 78.99% 78.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 566 7.33% 86.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 399 5.17% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 262 3.39% 94.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 2.58% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.57% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7720 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -368,69 +378,69 @@ system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2861 70.82% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 783 19.38% 90.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 395 9.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4046 # Type of FU issued -system.cpu.iq.rate 0.169516 # Inst issue rate +system.cpu.iq.FU_type_0::total 4040 # Type of FU issued +system.cpu.iq.rate 0.168460 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15885 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7299 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3649 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4077 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 540 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 174 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5302 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 955 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 468 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -438,43 +448,43 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 3849 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 391 # Number of stores executed -system.cpu.iew.exec_rate 0.161513 # Inst execution rate -system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1709 # num instructions producing a value -system.cpu.iew.wb_consumers 2209 # num instructions consuming a value +system.cpu.iew.exec_nop 336 # number of nop insts executed +system.cpu.iew.exec_refs 1127 # number of memory reference insts executed +system.cpu.iew.exec_branches 643 # Number of branches executed +system.cpu.iew.exec_stores 388 # Number of stores executed +system.cpu.iew.exec_rate 0.160495 # Inst execution rate +system.cpu.iew.wb_sent 3735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1708 # num instructions producing a value +system.cpu.iew.wb_consumers 2206 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152406 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.774252 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.356490 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.198597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6357 87.97% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 25 0.35% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7226 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,23 +497,23 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12303 # The number of ROB reads -system.cpu.rob.rob_writes 11127 # The number of ROB writes -system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12212 # The number of ROB reads +system.cpu.rob.rob_writes 11099 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16262 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads -system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4674 # number of integer regfile reads -system.cpu.int_regfile_writes 2826 # number of integer regfile writes +system.cpu.cpi 10.046921 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.046921 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099533 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099533 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4665 # number of integer regfile reads +system.cpu.int_regfile_writes 2823 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1457153580 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -518,55 +528,55 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 93.236237 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 816 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 816 # number of overall hits -system.cpu.icache.overall_hits::total 816 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 251 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 251 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 251 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 251 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 251 # number of overall misses -system.cpu.icache.overall_misses::total 251 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16843749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16843749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16843749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16843749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235239 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235239 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235239 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235239 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67106.569721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67106.569721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67106.569721 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 93.236237 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045526 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 815 # number of overall hits +system.cpu.icache.overall_hits::total 815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17655999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17655999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17655999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17655999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1065 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1065 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1065 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70623.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70623.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70623.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -575,48 +585,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 56 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12795749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12795749 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13162749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 122.122128 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.433851 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.688277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002851 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003727 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -628,17 +638,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12607000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4547250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17154250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12607000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6268000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18875000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12607000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6268000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18875000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4692750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17666750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6358500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19332500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6358500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19332500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -661,17 +671,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67058.510638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74545.081967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68892.570281 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69139.194139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69139.194139 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69010.638298 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76930.327869 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70950.803213 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70815.018315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70815.018315 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,17 +701,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10234500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3797750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14032250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15457500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10234500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15457500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10604500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3946250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14550750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10604500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10604500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5318000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -713,27 +723,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54438.829787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62258.196721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56406.914894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64692.622951 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58436.746988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.667407 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.667407 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011149 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011149 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits @@ -750,14 +760,14 @@ system.cpu.dcache.demand_misses::cpu.data 194 # n system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses system.cpu.dcache.overall_misses::total 194 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7226000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7226000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5211250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12437250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12437250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -774,14 +784,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63946.902655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63946.902655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64336.419753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64336.419753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64109.536082 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -806,14 +816,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6445000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6445000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -822,14 +832,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ca5a55de6..6f535bcb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19652 # Simulator instruction rate (inst/s) -host_op_rate 24522 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70593484 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 41552 # Simulator instruction rate (inst/s) +host_op_rate 51840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153628168 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -302,179 +312,179 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -482,55 +492,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -541,93 +551,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -637,42 +647,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -682,61 +692,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses +system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 397 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,124 +761,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -877,16 +887,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -895,30 +905,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index add5a91d0..1007daea2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22159 # Simulator instruction rate (inst/s) -host_op_rate 27650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79599293 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 59313 # Simulator instruction rate (inst/s) +host_op_rate 73997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219275591 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -257,179 +267,179 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -437,55 +447,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -496,93 +506,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -592,42 +602,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -637,61 +647,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses +system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 397 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -706,124 +716,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -832,16 +842,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -850,30 +860,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index aeb0e2e25..3c2a96518 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24587000 # Number of ticks simulated -final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24975000 # Number of ticks simulated +final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52979 # Simulator instruction rate (inst/s) -host_op_rate 52966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 223940501 # Simulator tick rate (ticks/s) -host_mem_usage 224928 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 84511 # Simulator instruction rate (inst/s) +host_op_rate 84494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 362882134 # Simulator tick rate (ticks/s) +host_mem_usage 254488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29120 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24519000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 455 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 455 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 0 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 8 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 12 # Per bank write bursts +system.physmem.perBankRdBursts::7 51 # Per bank write bursts +system.physmem.perBankRdBursts::8 59 # Per bank write bursts +system.physmem.perBankRdBursts::9 75 # Per bank write bursts +system.physmem.perBankRdBursts::10 36 # Per bank write bursts +system.physmem.perBankRdBursts::11 19 # Per bank write bursts +system.physmem.perBankRdBursts::12 52 # Per bank write bursts +system.physmem.perBankRdBursts::13 28 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24894000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 455 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,48 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation -system.physmem.totQLat 2305250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests -system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 8195000 # Total cycles spent in bank access -system.physmem.avgQLat 5066.48 # Average queueing delay per request -system.physmem.avgBankLat 18010.99 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28077.47 # Average memory access latency -system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.25 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.52 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 361 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation +system.physmem.totQLat 3167500 # Total ticks spent queuing +system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8112500 # Total ticks spent accessing banks +system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.11 # Data bus utilization in percentage +system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53887.91 # Average gap between requests -system.membus.throughput 1184365722 # Throughput (bytes/s) +system.physmem.avgGap 54712.09 # Average gap between requests +system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1165965966 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -202,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.1 # Layer utilization (%) +system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -234,14 +240,14 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49175 # number of cpu cycles simulated +system.cpu.numCycles 49951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File @@ -256,12 +262,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.946619 # Percentage of cycles cpu is active +system.cpu.activity 10.776561 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -273,36 +279,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads +system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -315,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -333,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +365,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -393,21 +399,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -425,17 +431,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -458,17 +464,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,17 +494,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -510,27 +516,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -547,14 +553,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7523000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7523000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21590750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21590750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -571,14 +577,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -603,14 +609,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -619,14 +625,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 423a70e1a..1c2de0612 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21805500 # Number of ticks simulated -final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21898500 # Number of ticks simulated +final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31004 # Simulator instruction rate (inst/s) -host_op_rate 31001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131093072 # Simulator tick rate (ticks/s) -host_mem_usage 229800 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 64871 # Simulator instruction rate (inst/s) +host_op_rate 64859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 275425114 # Simulator tick rate (ticks/s) +host_mem_usage 255508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30528 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21726000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 477 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 979062493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415005594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1394068087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 979062493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415005594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1394068087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 477 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 30 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 7 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 13 # Per bank write bursts +system.physmem.perBankRdBursts::7 54 # Per bank write bursts +system.physmem.perBankRdBursts::8 63 # Per bank write bursts +system.physmem.perBankRdBursts::9 77 # Per bank write bursts +system.physmem.perBankRdBursts::10 44 # Per bank write bursts +system.physmem.perBankRdBursts::11 20 # Per bank write bursts +system.physmem.perBankRdBursts::12 51 # Per bank write bursts +system.physmem.perBankRdBursts::13 29 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21819000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 477 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,47 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 2353250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests -system.physmem.totBusLat 2385000 # Total cycles spent in databus access -system.physmem.totBankLat 8676250 # Total cycles spent in bank access -system.physmem.avgQLat 4933.44 # Average queueing delay per request -system.physmem.avgBankLat 18189.20 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28122.64 # Average memory access latency -system.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.94 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.62 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 374 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.508475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.858901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.434070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 46 38.98% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 16.95% 55.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 19 16.10% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 6.78% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 7 5.93% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.54% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 3.39% 90.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 1.69% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.69% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.85% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 0.85% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.85% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.69% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 0.85% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 118 # Bytes accessed per row activation +system.physmem.totQLat 2620250 # Total ticks spent queuing +system.physmem.totMemAccLat 13667750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8662500 # Total ticks spent accessing banks +system.physmem.avgQLat 5493.19 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18160.38 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28653.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1394.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1394.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.89 # Data bus utilization in percentage +system.physmem.busUtilRead 10.89 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45547.17 # Average gap between requests -system.membus.throughput 1400013758 # Throughput (bytes/s) +system.physmem.avgGap 45742.14 # Average gap between requests +system.physmem.pageHitRate 75.26 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1394068087 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 426 # Transaction distribution system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -201,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.5 # Layer utilization (%) -system.cpu.branchPred.lookups 2187 # Number of BP lookups +system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups -system.cpu.branchPred.BTBHits 502 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups +system.cpu.branchPred.BTBHits 492 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -233,94 +240,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43612 # number of cpu cycles simulated +system.cpu.numCycles 43798 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13212 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8822 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1344 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1985 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.913456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.225567 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11219 77.74% 77.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1317 9.13% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.91% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 115 0.80% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 150 1.04% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 933 6.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3043 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3026 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2916 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2899 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13887 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8306 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14432 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.574626 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.242806 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10849 75.17% 75.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1422 9.85% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 6.17% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.83% 95.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 355 2.46% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.57% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 89 0.62% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14432 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available @@ -356,68 +363,68 @@ system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8306 # Type of FU issued -system.cpu.iq.rate 0.190452 # Inst issue rate +system.cpu.iq.FU_type_0::total 8293 # Type of FU issued +system.cpu.iq.rate 0.189347 # Inst issue rate system.cpu.iq.fu_busy_cnt 160 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31213 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall @@ -426,43 +433,43 @@ system.cpu.iew.memOrderViolationEvents 12 # Nu system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1525 # number of nop insts executed -system.cpu.iew.exec_refs 3189 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_nop 1512 # number of nop insts executed +system.cpu.iew.exec_refs 3186 # number of memory reference insts executed +system.cpu.iew.exec_branches 1344 # Number of branches executed system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.181716 # Inst execution rate -system.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7465 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.180648 # Inst execution rate +system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7455 # cumulative count of insts written-back system.cpu.iew.wb_producers 2921 # num instructions producing a value system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.171168 # insts written-back per cycle +system.cpu.iew.wb_rate 0.170213 # insts written-back per cycle system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13564 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428561 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.209396 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11162 82.29% 82.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 7.37% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 630 4.64% 94.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 315 2.32% 96.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 149 1.10% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13564 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,23 +482,23 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24237 # The number of ROB reads -system.cpu.rob.rob_writes 22398 # The number of ROB writes +system.cpu.rob.rob_reads 24172 # The number of ROB reads +system.cpu.rob.rob_writes 22333 # The number of ROB writes system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 29366 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.458495 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10746 # number of integer regfile reads -system.cpu.int_regfile_writes 5233 # number of integer regfile writes +system.cpu.cpi 8.494569 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.494569 # CPI: Total CPI of All Threads +system.cpu.ipc 0.117722 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.117722 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10743 # number of integer regfile reads +system.cpu.int_regfile_writes 5234 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1402835811 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -506,55 +513,55 @@ system.cpu.toL2Bus.data_through_bus 30720 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.632436 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits -system.cpu.icache.overall_hits::total 1531 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses -system.cpu.icache.overall_misses::total 454 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 161.632436 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078922 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078922 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits +system.cpu.icache.overall_hits::total 1514 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses +system.cpu.icache.overall_misses::total 451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -563,48 +570,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 47 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23858000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23858000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -622,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23490000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7101750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30591750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34454000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23490000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34454000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -655,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70119.402985 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78041.208791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71811.619718 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72230.607966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72230.607966 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,17 +692,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19249000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5981750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25230750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19249000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9210500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19249000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9210500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28459500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19597750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5909750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25507500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19597750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9093000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28690750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19597750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9093000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28690750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses @@ -707,27 +714,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57459.701493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65733.516484 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59227.112676 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58500.746269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64942.307692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.760563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 91.712882 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.712882 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022391 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits @@ -744,14 +751,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10243000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10243000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22828749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22828749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33071749 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33071749 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10190250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10190250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22575249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22575249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32765499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32765499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -768,19 +775,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68853.040541 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68853.040541 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62362.566298 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62362.566298 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -800,14 +807,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10987499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10987499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -816,14 +823,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index bf93774ff..800440e86 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18469500 # Number of ticks simulated -final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18905500 # Number of ticks simulated +final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33738 # Simulator instruction rate (inst/s) -host_op_rate 33735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107564291 # Simulator tick rate (ticks/s) -host_mem_usage 225768 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 83485 # Simulator instruction rate (inst/s) +host_op_rate 83467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272386071 # Simulator tick rate (ticks/s) +host_mem_usage 250488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28544 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18341000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 446 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 1167914099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 341911084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509825183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1167914099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 341911084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509825183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 446 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 70 # Per bank write bursts +system.physmem.perBankRdBursts::1 42 # Per bank write bursts +system.physmem.perBankRdBursts::2 54 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts +system.physmem.perBankRdBursts::4 53 # Per bank write bursts +system.physmem.perBankRdBursts::5 61 # Per bank write bursts +system.physmem.perBankRdBursts::6 52 # Per bank write bursts +system.physmem.perBankRdBursts::7 13 # Per bank write bursts +system.physmem.perBankRdBursts::8 8 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 2 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 4 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 18777000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 446 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 1996500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests -system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 6765000 # Total cycles spent in bank access -system.physmem.avgQLat 4476.46 # Average queueing delay per request -system.physmem.avgBankLat 15168.16 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24644.62 # Average memory access latency -system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.07 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 380 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.846154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.491272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 472.454851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 46.15% 46.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 10.26% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 8 10.26% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 5.13% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.56% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.85% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.28% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.56% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 2.56% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.56% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.28% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.28% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 2.56% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 1.28% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.28% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.28% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.28% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 2 2.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3018500 # Total ticks spent queuing +system.physmem.totMemAccLat 11958500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6710000 # Total ticks spent accessing banks +system.physmem.avgQLat 6767.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15044.84 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26812.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1509.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1509.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.80 # Data bus utilization in percentage +system.physmem.busUtilRead 11.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 368 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41123.32 # Average gap between requests -system.membus.throughput 1545466851 # Throughput (bytes/s) +system.physmem.avgGap 42100.90 # Average gap between requests +system.physmem.pageHitRate 82.51 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1509825183 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -202,10 +211,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 566000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect @@ -234,10 +243,10 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 36940 # number of cpu cycles simulated +system.cpu.numCycles 37812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7436 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken @@ -245,27 +254,27 @@ system.cpu.fetch.Cycles 2263 # Nu system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.117612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.534017 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9513 80.78% 80.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.51% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.49% 83.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.21% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.93% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.13% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.18% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059188 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.348064 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7513 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2098 # Number of cycles decode is running system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking @@ -275,7 +284,7 @@ system.cpu.decode.BranchMispred 154 # Nu system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1987 # Number of cycles rename is running @@ -298,66 +307,66 @@ system.cpu.memDep0.conflictingLoads 52 # Nu system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8904 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3486 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.487258 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8416 71.47% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.70% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 501 4.25% 91.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.87% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 61.52% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued @@ -384,21 +393,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1628 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8903 # Type of FU issued -system.cpu.iq.rate 0.241012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8904 # Type of FU issued +system.cpu.iq.rate 0.235481 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019429 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29936 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14577 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8131 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9043 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -425,43 +434,43 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8503 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3201 # number of memory reference insts executed +system.cpu.iew.exec_refs 3202 # number of memory reference insts executed system.cpu.iew.exec_branches 1351 # Number of branches executed -system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.230157 # Inst execution rate -system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8157 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4221 # num instructions producing a value -system.cpu.iew.wb_consumers 6683 # num instructions consuming a value +system.cpu.iew.exec_stores 1524 # Number of stores executed +system.cpu.iew.exec_rate 0.224876 # Inst execution rate +system.cpu.iew.wb_sent 8273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4220 # num instructions producing a value +system.cpu.iew.wb_consumers 6682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back +system.cpu.iew.wb_rate 0.215752 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631547 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.523358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.324283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.50% 78.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1007 9.10% 87.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 608 5.49% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 271 2.45% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.54% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.98% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11067 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,22 +483,22 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21366 # The number of ROB reads +system.cpu.rob.rob_reads 21334 # The number of ROB reads system.cpu.rob.rob_writes 21446 # The number of ROB writes system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 26036 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13474 # number of integer regfile reads +system.cpu.cpi 6.528315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.528315 # CPI: Total CPI of All Threads +system.cpu.ipc 0.153179 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.153179 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13476 # number of integer regfile reads system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1533521991 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -504,19 +513,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 587000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.362417 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits @@ -529,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 442 # n system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses system.cpu.icache.overall_misses::total 442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30183750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30183750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30183750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30183750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses @@ -547,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68289.027149 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -573,36 +582,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24475000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24475000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.747174 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.225208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006096 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -623,17 +632,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23046250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4132250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27178500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23046250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7769500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30815750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23046250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7769500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30815750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24063500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24063500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7664750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31728250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24063500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7664750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31728250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -656,17 +665,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66800.724638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69749.275362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,17 +695,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18694250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6525500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23130500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6423750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26143750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6423750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26143750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -708,51 +717,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.784946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015572 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits -system.cpu.dcache.overall_hits::total 2192 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits +system.cpu.dcache.overall_hits::total 2188 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses -system.cpu.dcache.overall_misses::total 431 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7365250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7365250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19851746 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19851746 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27216996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27216996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -763,20 +772,20 @@ system.cpu.dcache.overall_accesses::cpu.data 2623 system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70819.711538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59975.063444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62567.806897 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -787,12 +796,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -801,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7780248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7780248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -817,14 +826,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 68c96c714..b34a38ab7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20802500 # Number of ticks simulated -final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20892500 # Number of ticks simulated +final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86492 # Simulator instruction rate (inst/s) -host_op_rate 86452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337526822 # Simulator tick rate (ticks/s) -host_mem_usage 231936 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 70791 # Simulator instruction rate (inst/s) +host_op_rate 70777 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277537926 # Simulator tick rate (ticks/s) +host_mem_usage 260788 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27072 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20733000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 423 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24 # Per bank write bursts +system.physmem.perBankRdBursts::1 7 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 78 # Per bank write bursts +system.physmem.perBankRdBursts::6 80 # Per bank write bursts +system.physmem.perBankRdBursts::7 62 # Per bank write bursts +system.physmem.perBankRdBursts::8 35 # Per bank write bursts +system.physmem.perBankRdBursts::9 18 # Per bank write bursts +system.physmem.perBankRdBursts::10 10 # Per bank write bursts +system.physmem.perBankRdBursts::11 52 # Per bank write bursts +system.physmem.perBankRdBursts::12 12 # Per bank write bursts +system.physmem.perBankRdBursts::13 21 # Per bank write bursts +system.physmem.perBankRdBursts::14 7 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 20823000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 423 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -150,48 +152,53 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation -system.physmem.totQLat 2859500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests -system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 6490000 # Total cycles spent in bank access -system.physmem.avgQLat 6760.05 # Average queueing delay per request -system.physmem.avgBankLat 15342.79 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27102.84 # Average memory access latency -system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.55 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 358 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation +system.physmem.totQLat 3229250 # Total ticks spent queuing +system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6490000 # Total ticks spent accessing banks +system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.12 # Data bus utilization in percentage +system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 343 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49014.18 # Average gap between requests -system.membus.throughput 1301382045 # Throughput (bytes/s) +system.physmem.avgGap 49226.95 # Average gap between requests +system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1295775996 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -204,8 +211,8 @@ system.membus.data_through_bus 27072 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -216,7 +223,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41606 # number of cpu cycles simulated +system.cpu.numCycles 41786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -238,12 +245,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 15.009854 # Percentage of cycles cpu is active +system.cpu.activity 14.945197 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -255,36 +262,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -297,12 +304,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -315,12 +322,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +348,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -375,21 +382,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -410,17 +417,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -443,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +480,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -495,27 +502,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -532,14 +539,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -556,14 +563,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -588,14 +595,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -604,14 +611,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 45776fad9..b42a03bbb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19639500 # Number of ticks simulated -final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19970500 # Number of ticks simulated +final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27608 # Simulator instruction rate (inst/s) -host_op_rate 50013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100764572 # Simulator tick rate (ticks/s) -host_mem_usage 247304 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 37809 # Simulator instruction rate (inst/s) +host_op_rate 68492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140319695 # Simulator tick rate (ticks/s) +host_mem_usage 243588 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 26624 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19591000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 417 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 26496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 414 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 874890463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451866503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1326756967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 874890463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451866503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1326756967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 415 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 33 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 5 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 50 # Per bank write bursts +system.physmem.perBankRdBursts::5 44 # Per bank write bursts +system.physmem.perBankRdBursts::6 20 # Per bank write bursts +system.physmem.perBankRdBursts::7 36 # Per bank write bursts +system.physmem.perBankRdBursts::8 23 # Per bank write bursts +system.physmem.perBankRdBursts::9 73 # Per bank write bursts +system.physmem.perBankRdBursts::10 63 # Per bank write bursts +system.physmem.perBankRdBursts::11 17 # Per bank write bursts +system.physmem.perBankRdBursts::12 2 # Per bank write bursts +system.physmem.perBankRdBursts::13 17 # Per bank write bursts +system.physmem.perBankRdBursts::14 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 17 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 19922000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 415 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,300 +152,305 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation -system.physmem.totQLat 1395750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests -system.physmem.totBusLat 2085000 # Total cycles spent in databus access -system.physmem.totBankLat 7645000 # Total cycles spent in bank access -system.physmem.avgQLat 3347.12 # Average queueing delay per request -system.physmem.avgBankLat 18333.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26680.46 # Average memory access latency -system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 329 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 226.174757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.685606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.474459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 47 45.63% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 17 16.50% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 14 13.59% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 4.85% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 5 4.85% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.91% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 3.88% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.94% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.97% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.94% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.97% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.97% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2039250 # Total ticks spent queuing +system.physmem.totMemAccLat 11731750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7617500 # Total ticks spent accessing banks +system.physmem.avgQLat 4913.86 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18355.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28269.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1329.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1329.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.39 # Data bus utilization in percentage +system.physmem.busUtilRead 10.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 312 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46980.82 # Average gap between requests -system.membus.throughput 1355635327 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 340 # Transaction distribution -system.membus.trans_dist::ReadResp 339 # Transaction distribution +system.physmem.avgGap 48004.82 # Average gap between requests +system.physmem.pageHitRate 75.18 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1326756967 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 338 # Transaction distribution +system.membus.trans_dist::ReadResp 337 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26496 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu.branchPred.lookups 3060 # Number of BP lookups -system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups -system.cpu.branchPred.BTBHits 719 # Number of BTB hits +system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.4 # Layer utilization (%) +system.cpu.branchPred.lookups 3084 # Number of BP lookups +system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39280 # number of cpu cycles simulated +system.cpu.numCycles 39942 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5300 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.153353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669079 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18006 82.43% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 216 0.99% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 142 0.65% 84.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.03% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 181 0.83% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 0.92% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 1.26% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.73% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2442 11.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3343 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 31469 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077212 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.353863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11079 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3583 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11444 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.654421 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16359 74.89% 74.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1539 7.05% 81.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1092 5.00% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 724 3.31% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 698 3.20% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 576 2.64% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 581 2.66% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21845 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17094 # Type of FU issued -system.cpu.iq.rate 0.435183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17027 # Type of FU issued +system.cpu.iq.rate 0.426293 # Inst issue rate +system.cpu.iq.fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3034 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3125 # number of memory reference insts executed -system.cpu.iew.exec_branches 1615 # Number of branches executed -system.cpu.iew.exec_stores 1277 # Number of stores executed -system.cpu.iew.exec_rate 0.411965 # Inst execution rate -system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15703 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10139 # num instructions producing a value -system.cpu.iew.wb_consumers 15623 # num instructions consuming a value +system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_branches 1623 # Number of branches executed +system.cpu.iew.exec_stores 1273 # Number of stores executed +system.cpu.iew.exec_rate 0.403685 # Inst execution rate +system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15646 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10128 # num instructions producing a value +system.cpu.iew.wb_consumers 15579 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back +system.cpu.iew.wb_rate 0.391718 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 19988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344274 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16420 82.15% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1360 6.80% 88.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 589 2.95% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 713 3.57% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 364 1.82% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19988 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -456,138 +463,138 @@ system.cpu.commit.int_insts 9653 # Nu system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40219 # The number of ROB reads -system.cpu.rob.rob_writes 42582 # The number of ROB writes -system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40049 # The number of ROB reads +system.cpu.rob.rob_writes 42426 # The number of ROB writes +system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18097 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20780 # number of integer regfile reads -system.cpu.int_regfile_writes 12385 # number of integer regfile writes +system.cpu.cpi 7.424164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.424164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134695 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134695 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20727 # number of integer regfile reads +system.cpu.int_regfile_writes 12358 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8044 # number of cc regfile reads -system.cpu.cc_regfile_writes 4852 # number of cc regfile writes -system.cpu.misc_regfile_reads 7122 # number of misc regfile reads +system.cpu.cc_regfile_reads 8004 # number of cc regfile reads +system.cpu.cc_regfile_writes 4850 # number of cc regfile writes +system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution +system.cpu.toL2Bus.throughput 1333166420 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 458500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.946729 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits -system.cpu.icache.overall_hits::total 1608 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses -system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses +system.cpu.icache.overall_misses::total 371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25087750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25087750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25087750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25087750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67621.967655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67621.967655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 70 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19054250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19054250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.139100 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.139100 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69288.181818 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69288.181818 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 97 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 97 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19639000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71675.182482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71675.182482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.766589 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003992 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.016356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.750233 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits @@ -597,61 +604,61 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 340 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 338 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses -system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18767750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5075750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23843500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5461000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5461000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18767750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10536750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29304500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18767750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10536750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29304500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 67 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 342 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses +system.cpu.l2cache.overall_misses::total 415 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19353500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24357500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5417000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5417000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29774500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10421000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29774500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 275 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 275 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996364 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.985075 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.994152 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 274 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996350 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.984848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994118 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996364 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.993056 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995227 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996364 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.993056 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995227 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68495.437956 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70891.941392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76984.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.609467 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71745.783133 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71745.783133 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -660,113 +667,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4265250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19588500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4500500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4500500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15323250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8765750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24089000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15323250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8765750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24089000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.985075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15927500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4205500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20133000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4457500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4457500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15927500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8663000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15927500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8663000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24590500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55924.270073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57613.235294 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58448.051948 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58448.051948 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64700 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 83.239431 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 83.239431 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020322 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020322 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2341 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2341 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2341 # number of overall hits -system.cpu.dcache.overall_hits::total 2341 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits +system.cpu.dcache.overall_hits::total 2337 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses -system.cpu.dcache.overall_misses::total 210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9610000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9610000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5723000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5723000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15333000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15333000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15333000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15333000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses +system.cpu.dcache.overall_misses::total 209 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9408000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9408000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5676000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5676000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15084000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15084000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15084000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15084000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082302 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082302 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,38 +783,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 66 system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 12317fca2..15c806f18 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24404000 # Number of ticks simulated -final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24229500 # Number of ticks simulated +final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12749 # Simulator instruction rate (inst/s) -host_op_rate 12749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24410850 # Simulator tick rate (ticks/s) -host_mem_usage 229776 # Number of bytes of host memory used -host_seconds 1.00 # Real time elapsed on the host +host_inst_rate 81251 # Simulator instruction rate (inst/s) +host_op_rate 81244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154440285 # Simulator tick rate (ticks/s) +host_mem_usage 227736 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 974 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1636453040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 917882314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2554335355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1636453040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1636453040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 974 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 974 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 62336 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 87 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24245500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 974 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1648238717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 927134278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2575372996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1648238717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1648238717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1648238717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 927134278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2575372996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 82 # Per bank write bursts +system.physmem.perBankRdBursts::1 153 # Per bank write bursts +system.physmem.perBankRdBursts::2 77 # Per bank write bursts +system.physmem.perBankRdBursts::3 60 # Per bank write bursts +system.physmem.perBankRdBursts::4 87 # Per bank write bursts +system.physmem.perBankRdBursts::5 49 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 49 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 39 # Per bank write bursts +system.physmem.perBankRdBursts::10 30 # Per bank write bursts +system.physmem.perBankRdBursts::11 33 # Per bank write bursts +system.physmem.perBankRdBursts::12 15 # Per bank write bursts +system.physmem.perBankRdBursts::13 121 # Per bank write bursts +system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24081000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 975 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,101 +152,101 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.957672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.277128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 472.297416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 80 42.33% 42.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 30 15.87% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 19 10.05% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20 10.58% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 1.59% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 2.65% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 2.12% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 3 1.59% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 0.53% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 6 3.17% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 0.53% 91.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 0.53% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 0.53% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 1.06% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 0.53% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 1.06% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 0.53% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 1 0.53% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 0.53% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 1 0.53% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 1.06% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.53% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 1 0.53% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 1 0.53% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 1 0.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 189 # Bytes accessed per row activation -system.physmem.totQLat 8948500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 30593500 # Sum of mem lat for all requests -system.physmem.totBusLat 4870000 # Total cycles spent in databus access -system.physmem.totBankLat 16775000 # Total cycles spent in bank access -system.physmem.avgQLat 9187.37 # Average queueing delay per request -system.physmem.avgBankLat 17222.79 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31410.16 # Average memory access latency -system.physmem.avgRdBW 2554.34 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2554.34 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.96 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.25 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 785 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 271.926267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.688517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.951821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 92 42.40% 42.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 33 15.21% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 21 9.68% 67.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20 9.22% 76.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 1.38% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 8 3.69% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3 1.38% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 1.84% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 1.84% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 1.84% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 5 2.30% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 4 1.84% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 0.92% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 2 0.92% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 3 1.38% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.46% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 2 0.92% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 2 0.92% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 0.46% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 0.92% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation +system.physmem.totQLat 9442250 # Total ticks spent queuing +system.physmem.totMemAccLat 31257250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers +system.physmem.totBankLat 16940000 # Total ticks spent accessing banks +system.physmem.avgQLat 9684.36 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 17374.36 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32058.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2575.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2575.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 20.12 # Data bus utilization in percentage +system.physmem.busUtilRead 20.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 758 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 24892.71 # Average gap between requests -system.membus.throughput 2554335355 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 828 # Transaction distribution -system.membus.trans_dist::ReadResp 828 # Transaction distribution +system.physmem.avgGap 24698.46 # Average gap between requests +system.physmem.pageHitRate 77.74 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.09 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2575372996 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 829 # Transaction distribution +system.membus.trans_dist::ReadResp 829 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62336 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62400 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 9049000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 37.1 # Layer utilization (%) -system.cpu.branchPred.lookups 6717 # Number of BP lookups -system.cpu.branchPred.condPredicted 3814 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4787 # Number of BTB lookups -system.cpu.branchPred.BTBHits 874 # Number of BTB hits +system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 37.4 # Layer utilization (%) +system.cpu.branchPred.lookups 6676 # Number of BP lookups +system.cpu.branchPred.condPredicted 3773 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4746 # Number of BTB lookups +system.cpu.branchPred.BTBHits 873 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.257781 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 896 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 177 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 18.394437 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4630 # DTB read hits -system.cpu.dtb.read_misses 109 # DTB read misses +system.cpu.dtb.read_hits 4588 # DTB read hits +system.cpu.dtb.read_misses 111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4739 # DTB read accesses -system.cpu.dtb.write_hits 2007 # DTB write hits -system.cpu.dtb.write_misses 95 # DTB write misses +system.cpu.dtb.read_accesses 4699 # DTB read accesses +system.cpu.dtb.write_hits 2013 # DTB write hits +system.cpu.dtb.write_misses 87 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2102 # DTB write accesses -system.cpu.dtb.data_hits 6637 # DTB hits -system.cpu.dtb.data_misses 204 # DTB misses +system.cpu.dtb.write_accesses 2100 # DTB write accesses +system.cpu.dtb.data_hits 6601 # DTB hits +system.cpu.dtb.data_misses 198 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6841 # DTB accesses -system.cpu.itb.fetch_hits 5430 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses +system.cpu.dtb.data_accesses 6799 # DTB accesses +system.cpu.itb.fetch_hits 5373 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5485 # ITB accesses +system.cpu.itb.fetch_accesses 5430 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -259,316 +261,316 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 48809 # number of cpu cycles simulated +system.cpu.numCycles 48460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1620 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37306 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6717 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1770 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6254 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 908 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.300949 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.721933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 37136 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5373 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.686803 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22422 78.19% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 547 1.91% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 376 1.31% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 432 1.51% 82.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 434 1.51% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 433 1.51% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 459 1.60% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 528 1.84% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3045 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23330 78.94% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 457 1.55% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 520 1.76% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3046 10.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137618 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.764326 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8556 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5391 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2766 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 575 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 354 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 32748 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 724 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2766 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40726 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5410 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 972 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5017 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2276 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22579 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37089 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37071 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.766323 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40475 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9887 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5338 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 491 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2736 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2736 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41176 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5023 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30191 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37141 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13439 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 57 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6273 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3023 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6118 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3003 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1402 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 3035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26482 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12686 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8147 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28676 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.760078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341515 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26321 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 29553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.731770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.328577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19237 67.08% 67.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3397 11.85% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2648 9.23% 88.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1591 5.55% 93.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1050 3.66% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 477 1.66% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 210 0.73% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.15% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20214 68.40% 68.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3351 11.34% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2621 8.87% 88.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1590 5.38% 93.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1011 3.42% 97.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29553 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 4.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 102 58.29% 62.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66 37.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 107 57.84% 62.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69 37.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7221 65.66% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2635 23.96% 89.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1137 10.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7076 65.52% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2585 23.94% 89.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1134 10.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10998 # Type of FU issued +system.cpu.iq.FU_type_0::total 10800 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7106 65.81% 65.83% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.84% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.84% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2582 23.91% 89.77% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7137 65.92% 65.94% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2587 23.90% 89.87% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10798 # Type of FU issued -system.cpu.iq.FU_type::total 21796 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.446557 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 175 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004083 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003946 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008029 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72523 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18760 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 10826 # Type of FU issued +system.cpu.iq.FU_type::total 21626 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.446265 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 88 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 97 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 185 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73079 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18683 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21945 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21785 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1840 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1787 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 481 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1820 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 537 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1852 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 408 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2766 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 26762 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 628 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6026 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2758 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 225 # Number of branches that were predicted taken incorrectly +system.cpu.iew.iewSquashCycles 2736 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20286 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2395 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2362 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1510 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20164 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2366 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4717 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1462 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 112 # number of nop insts executed -system.cpu.iew.exec_nop::1 87 # number of nop insts executed +system.cpu.iew.exec_nop::0 109 # number of nop insts executed +system.cpu.iew.exec_nop::1 90 # number of nop insts executed system.cpu.iew.exec_nop::total 199 # number of nop insts executed -system.cpu.iew.exec_refs::0 3467 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3404 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6871 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1580 # Number of branches executed -system.cpu.iew.exec_branches::1 1582 # Number of branches executed -system.cpu.iew.exec_branches::total 3162 # Number of branches executed -system.cpu.iew.exec_stores::0 1072 # Number of stores executed -system.cpu.iew.exec_stores::1 1042 # Number of stores executed +system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3414 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6831 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1584 # Number of branches executed +system.cpu.iew.exec_branches::1 1595 # Number of branches executed +system.cpu.iew.exec_branches::total 3179 # Number of branches executed +system.cpu.iew.exec_stores::0 1066 # Number of stores executed +system.cpu.iew.exec_stores::1 1048 # Number of stores executed system.cpu.iew.exec_stores::total 2114 # Number of stores executed -system.cpu.iew.exec_rate 0.415620 # Inst execution rate -system.cpu.iew.wb_sent::0 9597 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9491 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19088 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9418 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9362 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18780 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4881 # num instructions producing a value -system.cpu.iew.wb_producers::1 4800 # num instructions producing a value -system.cpu.iew.wb_producers::total 9681 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6383 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6247 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12630 # num instructions consuming a value +system.cpu.iew.exec_rate 0.416096 # Inst execution rate +system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9370 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18703 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4798 # num instructions producing a value +system.cpu.iew.wb_producers::1 4829 # num instructions producing a value +system.cpu.iew.wb_producers::total 9627 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6319 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12566 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.192956 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.191809 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.384765 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.764687 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.768369 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766508 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.193355 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.385947 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.764203 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766115 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13991 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1133 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.446662 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.213615 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.196069 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22891 80.01% 80.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3017 10.55% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1097 3.83% 94.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 546 1.91% 96.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 330 1.15% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 253 0.88% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 201 0.70% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 61 0.21% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 214 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23745 80.53% 80.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 341 1.16% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 269 0.91% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 187 0.63% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.22% 99.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29486 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6390 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -599,102 +601,102 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131690 # The number of ROB reads -system.cpu.rob.rob_writes 56322 # The number of ROB writes -system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132694 # The number of ROB reads +system.cpu.rob.rob_writes 55968 # The number of ROB writes +system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18907 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6373 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.658716 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.659918 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.829659 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.130570 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.130550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.261120 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25473 # number of integer regfile reads -system.cpu.int_regfile_writes 14213 # number of integer regfile writes +system.cpu.cpi::0 7.603954 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.605148 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.802275 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25291 # number of integer regfile reads +system.cpu.int_regfile_writes 14128 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2559580397 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution +system.cpu.toL2Bus.throughput 2580655812 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1029500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 562500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.icache.tags.replacements::0 6 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 6 # number of replacements -system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4319 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.899361 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4375 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4375 # number of overall hits -system.cpu.icache.overall_hits::total 4375 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4319 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4319 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4319 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4319 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4319 # number of overall hits +system.cpu.icache.overall_hits::total 4319 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses system.cpu.icache.overall_misses::total 1049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69677745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69677745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69677745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69677745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69677745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69677745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5424 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5424 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5424 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5424 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5424 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5424 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193400 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193400 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193400 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193400 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193400 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193400 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66423.017159 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66423.017159 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66423.017159 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66423.017159 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2785 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69934495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69934495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69934495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5368 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5368 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5368 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5368 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195417 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195417 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195417 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195417 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195417 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195417 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66667.774071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66667.774071 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2561 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 57 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.859649 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.155172 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -710,38 +712,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 626 system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46998246 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46998246 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46998246 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46998246 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46998246 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46998246 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115413 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115413 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115413 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75077.070288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75077.070288 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46953746 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46953746 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116617 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116617 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116617 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 433.166095 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 829 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002413 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009464 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 313.001767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 120.164328 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009552 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003667 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013219 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -749,60 +751,60 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 828 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 829 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 974 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 351 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses -system.cpu.l2cache.overall_misses::total 974 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46348500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16213750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 62562250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11913750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11913750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46348500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28127500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 74476000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46348500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28127500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 74476000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 351 # number of overall misses +system.cpu.l2cache.overall_misses::total 975 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46304000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16910000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 63214000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11874500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11874500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28784500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 75088500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28784500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 75088500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 830 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 205 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 831 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 976 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 351 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 976 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 351 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997593 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74276.442308 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79479.166667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75558.272947 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81601.027397 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81601.027397 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74276.442308 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80364.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76464.065708 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74276.442308 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80364.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76464.065708 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74205.128205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82487.804878 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76253.317250 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81332.191781 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81332.191781 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77013.846154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77013.846154 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -812,157 +814,157 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 829 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38573000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13696250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52269250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10103750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10103750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38573000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 62373000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38573000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 62373000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38522500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14387500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52910000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10067500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10067500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38522500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24455000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 62977500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38522500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24455000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 62977500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61815.705128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67138.480392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63127.113527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69203.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69203.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61734.775641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70182.926829 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63823.884198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68955.479452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68955.479452 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 214.018929 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4470 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.735043 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3469 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1024 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4493 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4493 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4493 # number of overall hits -system.cpu.dcache.overall_hits::total 4493 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 706 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1030 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1030 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1030 # number of overall misses -system.cpu.dcache.overall_misses::total 1030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22955250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22955250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48876949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48876949 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 71832199 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 71832199 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 71832199 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 71832199 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3793 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 214.018929 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3448 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3448 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4470 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4470 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4470 # number of overall hits +system.cpu.dcache.overall_hits::total 4470 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 329 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 329 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1037 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1037 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1037 # number of overall misses +system.cpu.dcache.overall_misses::total 1037 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23849750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23849750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 50904202 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 50904202 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74753952 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74753952 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74753952 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74753952 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3777 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3777 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5523 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5523 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085421 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085421 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.186493 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.186493 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.186493 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.186493 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70849.537037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70849.537037 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69230.805949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69230.805949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69739.999029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69739.999029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4722 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087106 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188306 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188306 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188306 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188306 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72491.641337 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72491.641337 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71898.590395 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71898.590395 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72086.742527 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72086.742527 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4541 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.358974 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.483051 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 686 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 686 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 686 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 686 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16427250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16427250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12061996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12061996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28489246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28489246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28489246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28489246 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053783 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053783 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12022996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12022996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29145996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29145996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29145996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29145996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054276 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054276 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063371 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063371 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80525.735294 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80525.735294 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82616.410959 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82616.410959 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063737 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063737 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83526.829268 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83526.829268 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82349.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82349.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 0c812fe4f..9f174a09c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27282000 # Number of ticks simulated -final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27705000 # Number of ticks simulated +final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96636 # Simulator instruction rate (inst/s) -host_op_rate 96628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173854426 # Simulator tick rate (ticks/s) -host_mem_usage 231852 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 72386 # Simulator instruction rate (inst/s) +host_op_rate 72381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132251643 # Simulator tick rate (ticks/s) +host_mem_usage 260736 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27904 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27248500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 436 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 688395596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 318787223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1007182819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 688395596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 318787223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1007182819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 436 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97 # Per bank write bursts +system.physmem.perBankRdBursts::1 28 # Per bank write bursts +system.physmem.perBankRdBursts::2 38 # Per bank write bursts +system.physmem.perBankRdBursts::3 20 # Per bank write bursts +system.physmem.perBankRdBursts::4 16 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 29 # Per bank write bursts +system.physmem.perBankRdBursts::7 32 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 58 # Per bank write bursts +system.physmem.perBankRdBursts::15 33 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 27671500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 436 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation -system.physmem.totQLat 1525500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests -system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 6325000 # Total cycles spent in bank access -system.physmem.avgQLat 3498.85 # Average queueing delay per request -system.physmem.avgBankLat 14506.88 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23005.73 # Average memory access latency -system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.37 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 387 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.743118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 502.320204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 32.81% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 10 15.62% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 7.81% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 12.50% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 3.12% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 3.12% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.12% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.56% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.56% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.56% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.56% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.56% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 3.12% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 2 3.12% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.56% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.56% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 3.12% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 1 1.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation +system.physmem.totQLat 2393750 # Total ticks spent queuing +system.physmem.totMemAccLat 10830000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6256250 # Total ticks spent accessing banks +system.physmem.avgQLat 5490.25 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14349.20 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24839.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1007.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1007.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.87 # Data bus utilization in percentage +system.physmem.busUtilRead 7.87 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.39 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 372 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 62496.56 # Average gap between requests -system.membus.throughput 1020453046 # Throughput (bytes/s) +system.physmem.avgGap 63466.74 # Average gap between requests +system.physmem.pageHitRate 85.32 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.29 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1004872767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -204,8 +213,8 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.6 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -216,7 +225,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54565 # number of cpu cycles simulated +system.cpu.numCycles 55411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -238,12 +247,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21832 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 436 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37843 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 32.196463 # Percentage of cycles cpu is active +system.cpu.activity 31.704896 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -255,36 +264,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.654597 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads -system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.654597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.273628 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.273628 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41985 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.229846 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46058 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 16.879320 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46608 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 15.886737 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 52533 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.193915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46102 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 16.799913 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.234439 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -297,12 +306,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26803000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26803000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26803000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26803000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -315,12 +324,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70349.081365 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +350,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20772000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20772000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1009492871 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -375,21 +384,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 501000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 200.306060 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.564740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -407,17 +416,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20448500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24149750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9603750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30052250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20448500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9603750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30052250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -440,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,17 +479,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16729000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19771250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7902250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24631250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16729000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7902250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24631250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -492,27 +501,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.671839 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -531,14 +540,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4274250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4274250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25400750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25400750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29675000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29675000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -557,14 +566,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61822.916667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -589,14 +598,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9746250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9746250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -605,14 +614,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 6e72806cb..dcf709c59 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26524500 # Number of ticks simulated -final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26616500 # Number of ticks simulated +final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19767 # Simulator instruction rate (inst/s) -host_op_rate 19766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36317578 # Simulator tick rate (ticks/s) -host_mem_usage 236084 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host +host_inst_rate 75478 # Simulator instruction rate (inst/s) +host_op_rate 75473 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139143595 # Simulator tick rate (ticks/s) +host_mem_usage 260732 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30848 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26363500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 482 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 482 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 102 # Per bank write bursts +system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::2 50 # Per bank write bursts +system.physmem.perBankRdBursts::3 24 # Per bank write bursts +system.physmem.perBankRdBursts::4 19 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 35 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 57 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 61 # Per bank write bursts +system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26455500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 482 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -150,47 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation -system.physmem.totQLat 1755500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests -system.physmem.totBusLat 2410000 # Total cycles spent in databus access -system.physmem.totBankLat 6765000 # Total cycles spent in bank access -system.physmem.avgQLat 3642.12 # Average queueing delay per request -system.physmem.avgBankLat 14035.27 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22677.39 # Average memory access latency -system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 430 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation +system.physmem.totQLat 2423000 # Total ticks spent queuing +system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6778750 # Total ticks spent accessing banks +system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.05 # Data bus utilization in percentage +system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 413 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54696.06 # Average gap between requests -system.membus.throughput 1163000245 # Throughput (bytes/s) +system.physmem.avgGap 54886.93 # Average gap between requests +system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1158980332 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -201,63 +211,63 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6716 # Number of BP lookups -system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted +system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 16.9 # Layer utilization (%) +system.cpu.branchPred.lookups 6713 # Number of BP lookups +system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53050 # number of cpu cycles simulated +system.cpu.numCycles 53234 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8344 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8343 # Number of cycles decode is running system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 7952 # Number of cycles rename is running system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename @@ -282,15 +292,15 @@ system.cpu.iq.iqSquashedInstsIssued 97 # Nu system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle @@ -298,7 +308,7 @@ system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -368,10 +378,10 @@ system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 21122 # Type of FU issued -system.cpu.iq.rate 0.398153 # Inst issue rate +system.cpu.iq.rate 0.396776 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads @@ -412,35 +422,35 @@ system.cpu.iew.exec_nop 1134 # nu system.cpu.iew.exec_refs 5224 # number of memory reference insts executed system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.378398 # Inst execution rate +system.cpu.iew.exec_rate 0.377090 # Inst execution rate system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19522 # cumulative count of insts written-back system.cpu.iew.wb_producers 9120 # num instructions producing a value system.cpu.iew.wb_consumers 11235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle +system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -453,22 +463,22 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54596 # The number of ROB reads +system.cpu.rob.rob_reads 54530 # The number of ROB reads system.cpu.rob.rob_writes 50298 # The number of ROB writes -system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads -system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads +system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 32043 # number of integer regfile reads system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -483,55 +493,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits -system.cpu.icache.overall_hits::total 4873 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits +system.cpu.icache.overall_hits::total 4872 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses system.cpu.icache.overall_misses::total 507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -552,36 +562,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 337 system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -599,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) @@ -632,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -662,17 +672,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -684,27 +694,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -723,14 +733,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -749,14 +759,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked @@ -781,14 +791,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -797,14 +807,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 1df87c21b..b78a3e4ce 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 110804500 # Number of ticks simulated -final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 111025500 # Number of ticks simulated +final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91896 # Simulator instruction rate (inst/s) -host_op_rate 91896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9765210 # Simulator tick rate (ticks/s) -host_mem_usage 250112 # Number of bytes of host memory used -host_seconds 11.35 # Real time elapsed on the host -sim_insts 1042724 # Number of instructions simulated -sim_ops 1042724 # Number of ops (including micro ops) simulated +host_inst_rate 119782 # Simulator instruction rate (inst/s) +host_op_rate 119782 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12747983 # Simulator tick rate (ticks/s) +host_mem_usage 275656 # Number of bytes of host memory used +host_seconds 8.71 # Real time elapsed on the host +sim_insts 1043212 # Number of instructions simulated +sim_ops 1043212 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -34,92 +34,94 @@ system.physmem.num_reads::cpu2.data 20 # Nu system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 42176 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 110776500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 660 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.bw_read::cpu0.inst 205214117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96842617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5764442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7493774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42080423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11528883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3458665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7493774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 379876695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205214117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42080423 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3458665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 256517647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205214117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96842617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5764442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7493774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42080423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11528883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3458665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7493774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 379876695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 660 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 115 # Per bank write bursts +system.physmem.perBankRdBursts::1 39 # Per bank write bursts +system.physmem.perBankRdBursts::2 29 # Per bank write bursts +system.physmem.perBankRdBursts::3 60 # Per bank write bursts +system.physmem.perBankRdBursts::4 65 # Per bank write bursts +system.physmem.perBankRdBursts::5 27 # Per bank write bursts +system.physmem.perBankRdBursts::6 18 # Per bank write bursts +system.physmem.perBankRdBursts::7 24 # Per bank write bursts +system.physmem.perBankRdBursts::8 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 12 # Per bank write bursts +system.physmem.perBankRdBursts::12 60 # Per bank write bursts +system.physmem.perBankRdBursts::13 38 # Per bank write bursts +system.physmem.perBankRdBursts::14 17 # Per bank write bursts +system.physmem.perBankRdBursts::15 98 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 110997500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 660 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 191 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -180,100 +182,104 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation -system.physmem.totQLat 3818750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests -system.physmem.totBusLat 3300000 # Total cycles spent in databus access -system.physmem.totBankLat 11000000 # Total cycles spent in bank access -system.physmem.avgQLat 5785.98 # Average queueing delay per request -system.physmem.avgBankLat 16666.67 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27452.65 # Average memory access latency -system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 260.662252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.685653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.368727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 56 37.09% 37.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 15 9.93% 47.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 26 17.22% 64.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 5.96% 70.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 10 6.62% 76.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 7 4.64% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 2.65% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 6 3.97% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 3 1.99% 90.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 3 1.99% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation +system.physmem.totQLat 4010250 # Total ticks spent queuing +system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers +system.physmem.totBankLat 10848750 # Total ticks spent accessing banks +system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.97 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 532 # Number of row buffer hits during reads +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 509 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 167843.18 # Average gap between requests -system.membus.throughput 380634361 # Throughput (bytes/s) +system.physmem.avgGap 168178.03 # Average gap between requests +system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.34 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 379876695 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeReq 289 # Transaction distribution system.membus.trans_dist::UpgradeResp 76 # Transaction distribution -system.membus.trans_dist::ReadExReq 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 164 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use -system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use +system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000115 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000846 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000047 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits @@ -284,18 +290,18 @@ system.l2c.demand_hits::cpu1.inst 412 # nu system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1443 # number of demand (read+write) hits +system.l2c.demand_hits::total 1442 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 229 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 412 # number of overall hits system.l2c.overall_hits::cpu1.data 11 # number of overall hits system.l2c.overall_hits::cpu2.inst 349 # number of overall hits system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 421 # number of overall hits +system.l2c.overall_hits::cpu3.inst 420 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1443 # number of overall hits +system.l2c.overall_hits::total 1442 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses @@ -305,10 +311,10 @@ system.l2c.ReadReq_misses::cpu2.data 7 # nu system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 543 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses @@ -333,53 +339,53 @@ system.l2c.overall_misses::cpu2.data 20 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 24801500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 584250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 958250 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9622500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 24801500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 584250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1032750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 47788500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 24801500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 584250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1032750 # number of overall miss cycles +system.l2c.overall_miss_latency::total 47788500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) @@ -392,28 +398,28 @@ system.l2c.demand_accesses::cpu1.inst 428 # nu system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.020979 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.273552 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses @@ -429,50 +435,50 @@ system.l2c.demand_miss_rate::cpu1.inst 0.037383 # mi system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.020930 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.020979 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.318526 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.020930 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.020979 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69259.868421 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 74821.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 63361.111111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 69569.521179 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77920.212766 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68645.833333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82096.076923 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 73520.833333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 77082.053435 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71029.672107 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71029.672107 # average overall miss latency +system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69084.958217 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 70287.292818 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79854.166667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73454.198473 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70902.818991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70902.818991 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,10 +511,10 @@ system.l2c.ReadReq_mshr_misses::cpu2.data 7 # n system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses @@ -533,53 +539,53 @@ system.l2c.overall_mshr_misses::cpu2.data 20 # n system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19789750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4760500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 695750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4180000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 327500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 30342250 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20238250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4701500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 676500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4287250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 30807000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 210021 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 217519 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 170017 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 180018 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5552000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7989500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 20238250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10253500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 676500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 4287250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 369750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 870250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 38796500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 20238250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10253500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 676500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 4287250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 369750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 870250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38796500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266499 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses @@ -595,410 +601,411 @@ system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.311909 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311909 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67650 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 58236.294896 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67312.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60988.549618 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution +system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 591 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 348 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5418 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27456 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 135488 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) +system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 135424 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 52160 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1628974 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1475514 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1928994 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1199245 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1926995 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1183748 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1932245 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1115744 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 82992 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits +system.cpu0.branchPred.lookups 83087 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80860 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1219 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 80377 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78332 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 221610 # number of cpu cycles simulated +system.cpu0.numCycles 222052 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 733333 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued +system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 972038 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 734246 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 320411 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 872 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 42 19.91% 46.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 53.08% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 171308 42.29% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued -system.cpu0.iq.rate 1.824931 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued +system.cpu0.iq.rate 1.824118 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2440 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 371 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 485139 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewDispLoadInsts 155927 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78789 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76515 # number of nop insts executed -system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed -system.cpu0.iew.exec_branches 80132 # Number of branches executed -system.cpu0.iew.exec_stores 78029 # Number of stores executed -system.cpu0.iew.exec_rate 1.820098 # Inst execution rate -system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238549 # num instructions producing a value -system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value +system.cpu0.iew.exec_nop 76577 # number of nop insts executed +system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80250 # Number of branches executed +system.cpu0.iew.exec_stores 78134 # Number of stores executed +system.cpu0.iew.exec_rate 1.819295 # Inst execution rate +system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238895 # num instructions producing a value +system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 472284 # Number of instructions committed -system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472968 # Number of instructions committed +system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230857 # Number of memory references committed -system.cpu0.commit.loads 153567 # Number of loads committed +system.cpu0.commit.refs 231199 # Number of memory references committed +system.cpu0.commit.loads 153795 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79177 # Number of branches committed +system.cpu0.commit.branches 79291 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 318286 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318742 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 677374 # The number of ROB reads -system.cpu0.rob.rob_writes 971507 # The number of ROB writes -system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 396291 # Number of Instructions Simulated -system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated -system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 721592 # number of integer regfile reads -system.cpu0.int_regfile_writes 325227 # number of integer regfile writes +system.cpu0.rob.rob_reads 678234 # The number of ROB reads +system.cpu0.rob.rob_writes 972657 # The number of ROB writes +system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396861 # Number of Instructions Simulated +system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated +system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 722661 # number of integer regfile reads +system.cpu0.int_regfile_writes 325773 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads +system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits -system.cpu0.icache.overall_hits::total 5079 # number of overall hits +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits +system.cpu0.icache.overall_hits::total 5113 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1019,94 +1026,94 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits -system.cpu0.dcache.overall_hits::total 155698 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155902 # number of overall hits +system.cpu0.dcache.overall_hits::total 155902 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 420 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 420 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses -system.cpu0.dcache.overall_misses::total 955 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 965 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 965 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 965 # number of overall misses +system.cpu0.dcache.overall_misses::total 965 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13542707 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13542707 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32279504 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32279504 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 45822211 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 45822211 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 45822211 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 45822211 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77362 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 156867 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156867 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156867 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005283 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005283 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007045 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007045 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006152 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006152 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006152 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006152 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -1117,365 +1124,365 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6251507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6251507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7188729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7188729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13440236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13440236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13440236 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13440236 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002428 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002428 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002223 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002223 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002327 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002327 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 43495 # Number of BP lookups -system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits +system.cpu1.branchPred.lookups 47485 # Number of BP lookups +system.cpu1.branchPred.condPredicted 44754 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1270 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 41396 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 40599 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.074693 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 177681 # number of cpu cycles simulated +system.cpu1.numCycles 177933 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 31734 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 260080 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 47485 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 41253 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 95164 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3727 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 37889 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23379 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.480065 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.059330 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 80558 45.84% 45.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49339 28.08% 73.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7969 4.54% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3191 1.82% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 687 0.39% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 28723 16.35% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1207 0.69% 97.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 759 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3289 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 330316 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 175722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.266870 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.461674 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 38713 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 32553 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 87468 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6833 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2380 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 256418 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2380 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 39395 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 20083 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11723 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 80903 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 13463 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 254199 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 175957 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 477753 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 373133 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 162997 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12960 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1085 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 104746 49.43% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued -system.cpu1.iq.rate 1.067177 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued +system.cpu1.iq.rate 1.191033 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2380 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 699 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 251202 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 69810 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 31966 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1044 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 30958 # number of nop insts executed -system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed -system.cpu1.iew.exec_branches 40129 # Number of branches executed -system.cpu1.iew.exec_stores 26101 # Number of stores executed -system.cpu1.iew.exec_rate 1.060603 # Inst execution rate -system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 102456 # num instructions producing a value -system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value +system.cpu1.iew.exec_nop 34927 # number of nop insts executed +system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed +system.cpu1.iew.exec_branches 44131 # Number of branches executed +system.cpu1.iew.exec_stores 31196 # Number of stores executed +system.cpu1.iew.exec_rate 1.184317 # Inst execution rate +system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 116723 # num instructions producing a value +system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77636 46.89% 46.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42274 25.53% 72.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6096 3.68% 76.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8474 5.12% 81.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1557 0.94% 82.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 27207 16.43% 98.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1010 0.61% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 803 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 212432 # Number of instructions committed -system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165567 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 238705 # Number of instructions committed +system.cpu1.commit.committedOps 238705 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 83673 # Number of memory references committed -system.cpu1.commit.loads 58239 # Number of loads committed -system.cpu1.commit.membars 7917 # Number of memory barriers committed -system.cpu1.commit.branches 39308 # Number of branches committed +system.cpu1.commit.refs 97880 # Number of memory references committed +system.cpu1.commit.loads 67361 # Number of loads committed +system.cpu1.commit.membars 6845 # Number of memory barriers committed +system.cpu1.commit.branches 43327 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 145097 # Number of committed integer instructions. +system.cpu1.commit.int_insts 163326 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 803 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 388816 # The number of ROB reads -system.cpu1.rob.rob_writes 452512 # The number of ROB writes -system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 174425 # Number of Instructions Simulated -system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated -system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 315718 # number of integer regfile reads -system.cpu1.int_regfile_writes 148477 # number of integer regfile writes +system.cpu1.rob.rob_reads 415361 # The number of ROB reads +system.cpu1.rob.rob_writes 504754 # The number of ROB writes +system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 44117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 197745 # Number of Instructions Simulated +system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated +system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 358439 # number of integer regfile reads +system.cpu1.int_regfile_writes 167816 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads +system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits -system.cpu1.icache.overall_hits::total 25178 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses -system.cpu1.icache.overall_misses::total 478 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits +system.cpu1.icache.overall_hits::total 22903 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses +system.cpu1.icache.overall_misses::total 476 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1484,106 +1491,106 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits -system.cpu1.dcache.overall_hits::total 62948 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses -system.cpu1.dcache.overall_misses::total 451 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046220 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.046220 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 41736 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41736 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 30310 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 30310 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 72046 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 72046 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 72046 # number of overall hits +system.cpu1.dcache.overall_hits::total 72046 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 491 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 491 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 491 # number of overall misses +system.cpu1.dcache.overall_misses::total 491 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4404095 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4404095 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2802760 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2802760 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 563508 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 563508 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7206855 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7206855 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7206855 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7206855 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 42088 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 42088 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 30449 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 30449 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 72537 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 72537 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 72537 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 72537 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008363 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008363 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004565 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004565 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006769 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006769 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006769 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006769 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9886.105263 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9886.105263 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1592,365 +1599,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 187 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 187 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1130523 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1130523 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1329240 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1329240 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 449492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 449492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2459763 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2459763 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2459763 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2459763 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003920 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003920 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003514 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003514 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003750 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003750 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6851.654545 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6851.654545 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51236 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits +system.cpu2.branchPred.lookups 51290 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 177316 # number of cpu cycles simulated +system.cpu2.numCycles 177568 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 418050 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename +system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 6.01% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 56 19.79% 25.80% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 74.20% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114350 48.68% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued -system.cpu2.iq.rate 1.322842 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued +system.cpu2.iq.rate 1.322924 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2417 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 878 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278010 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 351 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79329 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37643 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1071 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 38706 # number of nop insts executed -system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed -system.cpu2.iew.exec_branches 47927 # Number of branches executed -system.cpu2.iew.exec_stores 36792 # Number of stores executed -system.cpu2.iew.exec_rate 1.316311 # Inst execution rate -system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131730 # num instructions producing a value -system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value +system.cpu2.iew.exec_nop 38771 # number of nop insts executed +system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed +system.cpu2.iew.exec_branches 48001 # Number of branches executed +system.cpu2.iew.exec_stores 36873 # Number of stores executed +system.cpu2.iew.exec_rate 1.316482 # Inst execution rate +system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131942 # num instructions producing a value +system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66196 40.91% 40.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46128 28.51% 69.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6098 3.77% 73.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6657 4.11% 77.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1558 0.96% 78.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32865 20.31% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 486 0.30% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1000 0.62% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 264916 # Number of instructions committed -system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161811 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 265352 # Number of instructions committed +system.cpu2.commit.committedOps 265352 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 112806 # Number of memory references committed -system.cpu2.commit.loads 76707 # Number of loads committed -system.cpu2.commit.membars 5024 # Number of memory barriers committed -system.cpu2.commit.branches 47088 # Number of branches committed +system.cpu2.commit.refs 113027 # Number of memory references committed +system.cpu2.commit.loads 76852 # Number of loads committed +system.cpu2.commit.membars 5022 # Number of memory barriers committed +system.cpu2.commit.branches 47160 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 182014 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182307 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 823 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 437936 # The number of ROB reads -system.cpu2.rob.rob_writes 557643 # The number of ROB writes -system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 222015 # Number of Instructions Simulated -system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated -system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 403571 # number of integer regfile reads -system.cpu2.int_regfile_writes 188531 # number of integer regfile writes +system.cpu2.rob.rob_reads 438409 # The number of ROB reads +system.cpu2.rob.rob_writes 558438 # The number of ROB writes +system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5563 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44482 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222382 # Number of Instructions Simulated +system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated +system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 404230 # number of integer regfile reads +system.cpu2.int_regfile_writes 188808 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits -system.cpu2.icache.overall_hits::total 19274 # number of overall hits +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits +system.cpu2.icache.overall_hits::total 19259 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses system.cpu2.icache.overall_misses::total 493 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1971,94 +1977,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9201754 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9201754 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9201754 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 9201754 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9201754 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 9201754 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021500 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021500 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9299505 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 9299505 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9299505 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 9299505 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9299505 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 9299505 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021517 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021517 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021517 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 81436 # number of overall hits -system.cpu2.dcache.overall_hits::total 81436 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 344 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 344 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 143 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 143 # number of WriteReq misses +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142582 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 35966 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 81579 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 81579 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 81579 # number of overall hits +system.cpu2.dcache.overall_hits::total 81579 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 346 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 346 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 487 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 487 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 487 # number of overall misses -system.cpu2.dcache.overall_misses::total 487 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5599802 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5599802 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3105260 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3105260 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 575007 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 575007 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8705062 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8705062 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8705062 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8705062 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 45893 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 45893 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 36030 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 36030 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 81923 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 81923 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 81923 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 81923 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007496 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.007496 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003969 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003969 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637 # average overall miss latency +system.cpu2.dcache.demand_misses::cpu2.data 485 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses +system.cpu2.dcache.overall_misses::total 485 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5531640 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5531640 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8662651 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8662651 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8662651 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8662651 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 36105 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 70 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 82064 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 82064 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 82064 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 82064 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007528 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.007528 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003850 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.814286 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2067,365 +2073,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1488769 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1488769 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1526989 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1526989 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 440994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 440994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3015758 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3015758 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3015758 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3015758 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003525 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003525 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002936 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002936 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003266 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003266 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9189.932099 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9189.932099 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7736.736842 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7736.736842 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 56317 # Number of BP lookups -system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits +system.cpu3.branchPred.lookups 52302 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49590 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1266 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 46219 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 176970 # number of cpu cycles simulated +system.cpu3.numCycles 177222 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 72377 41.17% 41.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 52818 30.04% 71.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6573 3.74% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3193 1.82% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 659 0.37% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 35007 19.91% 97.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1204 0.68% 97.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 468076 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.20% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 47 17.15% 23.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 76.64% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 115815 48.46% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued -system.cpu3.iq.rate 1.478471 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued +system.cpu3.iq.rate 1.348602 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2346 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 674 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 283043 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 80900 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 38213 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 43769 # number of nop insts executed -system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed -system.cpu3.iew.exec_branches 53091 # Number of branches executed -system.cpu3.iew.exec_stores 42613 # Number of stores executed -system.cpu3.iew.exec_rate 1.471764 # Inst execution rate -system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 148532 # num instructions producing a value -system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value +system.cpu3.iew.exec_nop 39788 # number of nop insts executed +system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed +system.cpu3.iew.exec_branches 49028 # Number of branches executed +system.cpu3.iew.exec_stores 37424 # Number of stores executed +system.cpu3.iew.exec_rate 1.342091 # Inst execution rate +system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 134044 # num instructions producing a value +system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 68017 41.05% 41.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 47143 28.45% 69.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6068 3.66% 73.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7148 4.31% 77.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1577 0.95% 78.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33420 20.17% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 508 0.31% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 998 0.60% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 820 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 297438 # Number of instructions committed -system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165699 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 270725 # Number of instructions committed +system.cpu3.commit.committedOps 270725 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 129728 # Number of memory references committed -system.cpu3.commit.loads 87775 # Number of loads committed -system.cpu3.commit.membars 4366 # Number of memory barriers committed -system.cpu3.commit.branches 52284 # Number of branches committed +system.cpu3.commit.refs 115239 # Number of memory references committed +system.cpu3.commit.loads 78487 # Number of loads committed +system.cpu3.commit.membars 5499 # Number of memory barriers committed +system.cpu3.commit.branches 48212 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 204138 # Number of committed integer instructions. +system.cpu3.commit.int_insts 185574 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 473500 # The number of ROB reads -system.cpu3.rob.rob_writes 621006 # The number of ROB writes -system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 249993 # Number of Instructions Simulated -system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated -system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 453881 # number of integer regfile reads -system.cpu3.int_regfile_writes 211087 # number of integer regfile writes +system.cpu3.rob.rob_reads 447315 # The number of ROB reads +system.cpu3.rob.rob_writes 568397 # The number of ROB writes +system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1402 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 226224 # Number of Instructions Simulated +system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated +system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 410473 # number of integer regfile reads +system.cpu3.int_regfile_writes 191401 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads +system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits -system.cpu3.icache.overall_hits::total 17724 # number of overall hits +system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits +system.cpu3.icache.overall_hits::total 20090 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2434,106 +2440,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits -system.cpu3.dcache.overall_hits::total 92475 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses -system.cpu3.dcache.overall_misses::total 484 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 83209 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 83209 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 83209 # number of overall hits +system.cpu3.dcache.overall_hits::total 83209 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 333 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 333 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 464 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses +system.cpu3.dcache.overall_misses::total 464 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 36684 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 83673 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 83673 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007087 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007087 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2542,54 +2548,54 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 181 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 212 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 212 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 212 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 212 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 252 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt index 4e4b75a44..9c1ab67e5 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 12102739985 # Simulator tick rate (ticks/s) -host_mem_usage 228608 # Number of bytes of host memory used -host_seconds 8.26 # Real time elapsed on the host +host_tick_rate 20181472495 # Simulator tick rate (ticks/s) +host_mem_usage 192916 # Number of bytes of host memory used +host_seconds 4.96 # Real time elapsed on the host system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory @@ -15,77 +15,79 @@ system.physmem.bw_read::cpu 2133311360 # To system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 213331136 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.readReqs 3333300 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3333300 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 213331200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 213331200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 217600 # Per bank write bursts +system.physmem.perBankRdBursts::1 217600 # Per bank write bursts +system.physmem.perBankRdBursts::2 217600 # Per bank write bursts +system.physmem.perBankRdBursts::3 217600 # Per bank write bursts +system.physmem.perBankRdBursts::4 210100 # Per bank write bursts +system.physmem.perBankRdBursts::5 204800 # Per bank write bursts +system.physmem.perBankRdBursts::6 204800 # Per bank write bursts +system.physmem.perBankRdBursts::7 204800 # Per bank write bursts +system.physmem.perBankRdBursts::8 204800 # Per bank write bursts +system.physmem.perBankRdBursts::9 204800 # Per bank write bursts +system.physmem.perBankRdBursts::10 204800 # Per bank write bursts +system.physmem.perBankRdBursts::11 204800 # Per bank write bursts +system.physmem.perBankRdBursts::12 204800 # Per bank write bursts +system.physmem.perBankRdBursts::13 204800 # Per bank write bursts +system.physmem.perBankRdBursts::14 204800 # Per bank write bursts +system.physmem.perBankRdBursts::15 204800 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 99999960000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3333300 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3333300 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3150208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 12820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4489 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -138,35 +140,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation -system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests -system.physmem.totBusLat 16666500000 # Total cycles spent in databus access -system.physmem.totBankLat 45939671250 # Total cycles spent in bank access -system.physmem.avgQLat 383.63 # Average queueing delay per request -system.physmem.avgBankLat 13782.04 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19165.67 # Average memory access latency -system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 38918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5478.771982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 4240.637477 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2732.249719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 284 0.73% 0.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 264 0.68% 1.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 268 0.69% 2.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 268 0.69% 2.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 266 0.68% 3.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 271 0.70% 4.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 268 0.69% 4.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 264 0.68% 5.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 268 0.69% 6.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 270 0.69% 6.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 267 0.69% 7.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 268 0.69% 8.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 268 0.69% 8.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 264 0.68% 9.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 270 0.69% 10.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.01% 10.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 268 0.69% 11.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 264 0.68% 11.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 268 0.69% 12.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 268 0.69% 13.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 267 0.69% 13.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 271 0.70% 14.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 268 0.69% 15.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 264 0.68% 15.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 268 0.69% 16.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 271 0.70% 17.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 266 0.68% 17.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 268 0.69% 18.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 268 0.69% 19.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 264 0.68% 19.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 271 0.70% 20.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.01% 20.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 268 0.69% 21.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 264 0.68% 22.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 268 0.69% 22.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 268 0.69% 23.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 267 0.69% 24.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 270 0.69% 24.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 268 0.69% 25.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 264 0.68% 26.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 268 0.69% 26.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 349 0.90% 27.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 264 0.68% 28.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 268 0.69% 29.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 268 0.69% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 264 0.68% 30.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 268 0.69% 31.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 268 0.69% 31.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 264 0.68% 32.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 268 0.69% 33.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 268 0.69% 33.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 264 0.68% 34.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 268 0.69% 35.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 268 0.69% 35.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 264 0.68% 36.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 268 0.69% 37.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 268 0.69% 38.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 264 0.68% 38.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 268 0.69% 39.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 268 0.69% 40.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 264 0.68% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 268 0.69% 41.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 267 0.69% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 264 0.68% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 268 0.69% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 267 0.69% 44.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 264 0.68% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 268 0.69% 45.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 267 0.69% 46.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 264 0.68% 46.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 268 0.69% 47.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 267 0.69% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 264 0.68% 48.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 268 0.69% 49.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 267 0.69% 50.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 264 0.68% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 268 0.69% 51.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 267 0.69% 52.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 264 0.68% 53.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 268 0.69% 53.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 267 0.69% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 264 0.68% 55.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 268 0.69% 55.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 267 0.69% 56.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 264 0.68% 57.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 268 0.69% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 268 0.69% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 264 0.68% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 268 0.69% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 268 0.69% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 264 0.68% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 268 0.69% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 268 0.69% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 264 0.68% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 268 0.69% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 268 0.69% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 264 0.68% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 268 0.69% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 13193 33.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38918 # Bytes accessed per row activation +system.physmem.totQLat 27766345550 # Total ticks spent queuing +system.physmem.totMemAccLat 88702111800 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 16666500000 # Total ticks spent in databus transfers +system.physmem.totBankLat 44269266250 # Total ticks spent accessing banks +system.physmem.avgQLat 8329.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13280.91 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26610.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2133.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2133.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 16.67 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.64 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3307200 # Number of row buffer hits during reads +system.physmem.busUtilRead 16.67 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.89 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 3294382 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 98.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 30000.29 # Average gap between requests +system.physmem.pageHitRate 98.83 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 2133311360 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3333300 # Transaction distribution system.membus.trans_dist::ReadResp 3333299 # Transaction distribution @@ -177,7 +279,7 @@ system.membus.tot_pkt_size::total 213331136 # Cu system.membus.data_through_bus 213331136 # Total data (bytes) system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 17154822550 # Layer occupancy (ticks) system.membus.respLayer0.utilization 17.2 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -231,8 +333,8 @@ system.monitor.writeBurstLengthHist::19 0 # Hi system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 2133311357.398473 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 105886.111402 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -284,20 +386,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333299 # Read request-response latency -system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency -system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency -system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency -system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 670 0.02% 99.96% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 670 0.02% 99.98% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 272 0.01% 99.99% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 138 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 46636.264419 # Read request-response latency +system.monitor.readLatencyHist::gmean 41775.198419 # Read request-response latency +system.monitor.readLatencyHist::stdev 39874.537130 # Read request-response latency +system.monitor.readLatencyHist::0-32767 0 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 3183561 95.51% 95.51% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 17049 0.51% 96.02% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 17311 0.52% 96.54% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 16920 0.51% 97.05% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.56% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 17311 0.52% 98.08% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 16917 0.51% 98.58% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.10% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 12954 0.39% 99.48% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 17175 0.52% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency @@ -418,17 +520,17 @@ system.monitor.ittReqReq::min_value 30000 # Re system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions -system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.270000 # Outstanding read transactions +system.monitor.outstandingReadsHist::gmean 1.105133 # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.135782 # Outstanding read transactions system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 100 100.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 94 94.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 0 0.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 0 0.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 3 3.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 0 0.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::6 0 0.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::7 3 3.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions |