diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/quick | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/quick')
26 files changed, 2933 insertions, 2933 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 94e787873..3181a01cf 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:42:32 -M5 revision 1633bdfc3b0a 7062 default qtip regression_update tip -M5 started Apr 10 2010 23:42:34 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:43:43 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31225500 because target called exit() +Exiting @ tick 31242000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index adbfbe35c..8b050d9d7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30166 # Simulator instruction rate (inst/s) -host_mem_usage 153332 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 146878557 # Simulator tick rate (ticks/s) +host_inst_rate 29156 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 142052352 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31225500 # Number of ticks simulated +sim_ticks 31242000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 202 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 582 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHits 94 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 314 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 125 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 957 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 895 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 751 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 721 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 345 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.predictedNotTaken 829 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 237 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Decode-Unit.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 4340 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 4354 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 447 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 165 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.069493 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 13895 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 524 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 134 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.069457 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 13850 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 6404 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 2 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 1 # Number of Multiply Requests Processed. system.cpu.RegFile-Manager.instReqsProcessed 19960 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 22.223468 # Percentage of cycles cpu is active +system.cpu.activity 22.272545 # Percentage of cycles cpu is active system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.752030 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.752030 # CPI: Total CPI of All Threads +system.cpu.cpi 9.757183 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.757183 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56342.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53342.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56336.842105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53336.842105 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5352500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5352000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5067500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56063.218391 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53063.218391 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56057.471264 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53057.471264 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4877500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4877000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4616000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10230000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10229000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9684000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9683000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025299 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.624059 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025306 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.651945 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10230000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10229000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9684000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9683000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.624059 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.651945 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -119,73 +119,73 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 7358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55544.850498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52868.421053 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7057 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16719000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.040908 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 7296 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55536.544850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6995 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16716500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.041255 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 301 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15067500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.038733 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15066000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.039062 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 24.848592 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24.630282 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7358 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency -system.cpu.icache.demand_hits 7057 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16719000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.040908 # miss rate for demand accesses +system.cpu.icache.demand_accesses 7296 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency +system.cpu.icache.demand_hits 6995 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16716500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.041255 # miss rate for demand accesses system.cpu.icache.demand_misses 301 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15067500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.038733 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15066000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.039062 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063597 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.247335 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7358 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.063623 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 130.299954 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7296 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7057 # number of overall hits -system.cpu.icache.overall_miss_latency 16719000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.040908 # miss rate for overall accesses +system.cpu.icache.overall_hits 6995 # number of overall hits +system.cpu.icache.overall_miss_latency 16716500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.041255 # miss rate for overall accesses system.cpu.icache.overall_misses 301 # number of overall misses system.cpu.icache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15067500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.038733 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15066000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.039062 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.247335 # Cycle average of tags in use -system.cpu.icache.total_refs 7057 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 130.299954 # Cycle average of tags in use +system.cpu.icache.total_refs 6995 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 7356 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 48573 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102543 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102543 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 7294 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 48568 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.102489 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.102489 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 7375 # ITB accesses +system.cpu.itb.fetch_accesses 7313 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 7358 # ITB hits +system.cpu.itb.fetch_hits 7296 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,19 +196,19 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52061.643836 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52054.794521 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3800500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3800000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52069.920844 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52065.963061 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15139000 # number of ReadReq MSHR miss cycles @@ -232,10 +232,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23535000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23533000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -245,14 +245,14 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.381905 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005537 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 181.445272 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23535000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23533000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses system.cpu.l2cache.overall_misses 452 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -264,32 +264,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.381905 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.445272 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62452 # number of cpu cycles simulated -system.cpu.runCycles 13879 # Number of cycles cpu stages are processed. +system.cpu.numCycles 62485 # number of cpu cycles simulated +system.cpu.runCycles 13917 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55077 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 7375 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.809069 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55915 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6537 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.467239 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 55982 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 55172 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 7313 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 11.703609 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 55931 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6554 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.488917 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 56015 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.359956 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60399 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.354485 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 60432 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.287325 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 56048 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.285589 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 56081 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.254275 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62452 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.248860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 62485 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1b5a762f3..409d22ab8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 0bdde157a..2c74abf7c 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:54 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 01:04:08 -M5 executing on SC2B0619 -command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:59:38 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12474500 because target called exit() +Exiting @ tick 12497500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7fffd3b0b..1208848c5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,259 +1,259 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 104903 # Simulator instruction rate (inst/s) -host_mem_usage 190976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 203948336 # Simulator tick rate (ticks/s) +host_inst_rate 84020 # Simulator instruction rate (inst/s) +host_mem_usage 204400 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 163850067 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12474500 # Number of ticks simulated +sim_ticks 12497500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2263 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2245 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12417 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515664 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.304890 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 9514 76.62% 76.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% 89.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% 93.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% 95.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% 97.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9528 76.65% 76.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1629 13.10% 89.75% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 491 3.95% 93.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 259 2.08% 95.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 156 1.25% 97.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.88% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% 99.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 49 0.39% 99.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12417 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses +system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses -system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses +system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2104 # number of overall hits -system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses -system.cpu.dcache.overall_misses 554 # number of overall misses -system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2103 # number of overall hits +system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses +system.cpu.dcache.overall_misses 544 # number of overall misses +system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use -system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use +system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2951 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2948 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2890 # DTB hits +system.cpu.dtb.data_hits 2887 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1876 # DTB read accesses +system.cpu.dtb.read_accesses 1865 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1840 # DTB read hits +system.cpu.dtb.read_hits 1829 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.write_accesses 1083 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1050 # DTB write hits +system.cpu.dtb.write_hits 1058 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched -system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 501 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched +system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 10844 81.45% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 252 1.89% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 238 1.79% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 230 1.73% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 272 2.04% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 162 1.22% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 232 1.74% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 129 0.97% 92.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 955 7.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 245 1.84% 83.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 221 1.66% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 185 1.39% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 233 1.75% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 164 1.23% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 228 1.71% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 133 1.00% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency -system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses -system.cpu.icache.demand_misses 424 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses +system.cpu.icache.demand_misses 426 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1378 # number of overall hits -system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses -system.cpu.icache.overall_misses 424 # number of overall misses -system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1366 # number of overall hits +system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses +system.cpu.icache.overall_misses 426 # number of overall misses +system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use -system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use +system.cpu.icache.total_refs 1366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1450 # Number of branches executed -system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate -system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1077 # Number of stores executed +system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1448 # Number of branches executed +system.cpu.iew.EXEC:nop 83 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate +system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1085 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6020 # num instructions consuming a value -system.cpu.iew.WB:count 8734 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back +system.cpu.iew.WB:consumers 6049 # num instructions consuming a value +system.cpu.iew.WB:count 8759 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4491 # num instructions producing a value -system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle -system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4508 # num instructions producing a value +system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle +system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores @@ -262,77 +262,77 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6254 66.92% 66.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1986 21.25% 88.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1100 11.77% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9345 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 14 13.33% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 56 53.33% 66.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% 81.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% 89.38% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% 94.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% 97.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% 98.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9142 68.58% 68.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1697 12.73% 81.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1062 7.97% 89.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 730 5.48% 94.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 359 2.69% 97.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 188 1.41% 98.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 105 0.79% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 36 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate -system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate +system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1838 # ITB accesses +system.cpu.itb.fetch_accesses 1827 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1802 # ITB hits -system.cpu.itb.fetch_misses 36 # ITB misses +system.cpu.itb.fetch_hits 1792 # ITB hits +system.cpu.itb.fetch_misses 35 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -342,31 +342,31 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -378,31 +378,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -410,32 +410,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 24950 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24996 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index c164849b4..73089a2aa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 703e5cb77..95c4493ba 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:44:06 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:10:59 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7183000 because target called exit() +Exiting @ tick 7285000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 48416d4fa..c49e5f817 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,337 +1,337 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86395 # Simulator instruction rate (inst/s) -host_mem_usage 189960 # Number of bytes of host memory used +host_inst_rate 87095 # Simulator instruction rate (inst/s) +host_mem_usage 203396 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 257307637 # Simulator tick rate (ticks/s) +host_tick_rate 263805903 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7183000 # Number of ticks simulated +sim_ticks 7285000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 198 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 684 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 674 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 447 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 859 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 463 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 916 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 178 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6197 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.415685 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 6323 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.407402 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.198077 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% 84.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% 88.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% 94.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% 97.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% 98.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% 99.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% 99.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 38 0.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 5366 84.86% 84.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 262 4.14% 89.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 338 5.35% 94.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 131 2.07% 96.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 72 1.14% 97.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 64 1.01% 98.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.51% 99.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 19 0.30% 99.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 39 0.62% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6323 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1946 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.104315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.104315 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35822.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35663.934426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 505 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3224000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.151261 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2175500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.102521 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37219.626168 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37702.702703 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3982500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1395000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.600000 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.demand_accesses 889 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36581.218274 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses -system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7206500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.221597 # miss rate for demand accesses +system.cpu.dcache.demand_misses 197 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 99 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.110236 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011202 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 45.884316 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.occ_%::0 0.011290 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 46.245716 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 889 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36581.218274 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674 # number of overall hits -system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses -system.cpu.dcache.overall_misses 193 # number of overall misses -system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_hits 692 # number of overall hits +system.cpu.dcache.overall_miss_latency 7206500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.221597 # miss rate for overall accesses +system.cpu.dcache.overall_misses 197 # number of overall misses +system.cpu.dcache.overall_mshr_hits 99 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.110236 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use -system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.245716 # Cycle average of tags in use +system.cpu.dcache.total_refs 731 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 169 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 142 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 5018 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5179 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 974 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 367 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 971 # DTB accesses +system.cpu.dtb.data_accesses 1010 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 946 # DTB hits -system.cpu.dtb.data_misses 25 # DTB misses +system.cpu.dtb.data_hits 979 # DTB hits +system.cpu.dtb.data_misses 31 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 611 # DTB read accesses +system.cpu.dtb.read_accesses 638 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 600 # DTB read hits -system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 360 # DTB write accesses +system.cpu.dtb.read_hits 623 # DTB read hits +system.cpu.dtb.read_misses 15 # DTB read misses +system.cpu.dtb.write_accesses 372 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 346 # DTB write hits -system.cpu.dtb.write_misses 14 # DTB write misses -system.cpu.fetch.Branches 859 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 747 # Number of cache lines fetched -system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 239 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.826134 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.219931 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 356 # DTB write hits +system.cpu.dtb.write_misses 16 # DTB write misses +system.cpu.fetch.Branches 916 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 789 # Number of cache lines fetched +system.cpu.fetch.Cycles 1801 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 119 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5736 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 250 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.062865 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 789 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 368 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.393659 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.857399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271719 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 5595 85.71% 85.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 36 0.55% 86.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 100 1.53% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 69 1.06% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 130 1.99% 90.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 72 1.10% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 45 0.69% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 48 0.74% 93.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 433 6.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 5707 85.31% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 48 0.72% 86.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 101 1.51% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 74 1.11% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 57 0.85% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 51 0.76% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 51 0.76% 92.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 478 7.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6528 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 6690 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 789 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36081.196581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.154696 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 555 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8443000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.296578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6391500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.229404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.066298 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency -system.cpu.icache.demand_hits 512 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses -system.cpu.icache.demand_misses 235 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 789 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36081.196581 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency +system.cpu.icache.demand_hits 555 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8443000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.296578 # miss rate for demand accesses +system.cpu.icache.demand_misses 234 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6391500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.229404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.043324 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 88.727286 # Average occupied blocks per context -system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.043805 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 89.711886 # Average occupied blocks per context +system.cpu.icache.overall_accesses 789 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36081.196581 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 512 # number of overall hits -system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses -system.cpu.icache.overall_misses 235 # number of overall misses -system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 555 # number of overall hits +system.cpu.icache.overall_miss_latency 8443000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.296578 # miss rate for overall accesses +system.cpu.icache.overall_misses 234 # number of overall misses +system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6391500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.229404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use -system.cpu.icache.total_refs 512 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 89.711886 # Cycle average of tags in use +system.cpu.icache.total_refs 555 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 584 # Number of branches executed -system.cpu.iew.EXEC:nop 286 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate -system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 360 # Number of stores executed +system.cpu.idleCycles 7881 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 607 # Number of branches executed +system.cpu.iew.EXEC:nop 310 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.241370 # Inst execution rate +system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 372 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1896 # num instructions consuming a value -system.cpu.iew.WB:count 3311 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back +system.cpu.iew.WB:consumers 1984 # num instructions consuming a value +system.cpu.iew.WB:count 3409 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.798891 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1509 # num instructions producing a value -system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle -system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1585 # num instructions producing a value +system.cpu.iew.WB:rate 0.233958 # insts written-back per cycle +system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 787 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispStoreInsts 432 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4536 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 641 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 117 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3517 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 372 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 138 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 110 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads +system.cpu.ipc 0.163819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.163819 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2506 71.31% 71.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 639 18.18% 89.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 368 10.47% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2590 71.27% 71.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 666 18.33% 89.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 377 10.37% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3514 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 3634 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009631 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.94% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 11 32.35% 35.29% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 22 64.71% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 6690 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543199 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215587 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% 77.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% 86.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% 91.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% 95.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% 97.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% 99.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% 99.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5134 76.74% 76.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 621 9.28% 86.02% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 357 5.34% 91.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 240 3.59% 94.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 184 2.75% 97.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 102 1.52% 99.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 36 0.54% 99.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.16% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6528 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate -system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 6690 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.249399 # Inst issue rate +system.cpu.iq.iqInstsAdded 4220 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3634 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 874 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 776 # ITB accesses +system.cpu.itb.fetch_accesses 818 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 747 # ITB hits +system.cpu.itb.fetch_hits 789 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,21 +351,21 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34324.380165 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 8306500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31107.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 435500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -377,10 +377,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34349.624060 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9137000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -390,14 +390,14 @@ system.cpu.l2cache.demand_mshr_misses 266 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003380 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 110.762790 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003416 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 111.924793 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34349.624060 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9137000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -409,32 +409,31 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 111.924793 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 411 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 14367 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 787 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 432 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 14571 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IdleCycles 5259 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5438 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4848 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3462 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 895 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 367 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 16 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1694 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 80 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index aa3193437..12732e5e1 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 23 2010 00:25:27 -M5 revision ba1ff0a71710+ 7040+ default tip -M5 started Mar 23 2010 00:25:28 -M5 executing on zooks +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 6c70d7ee8..76dc624e3 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30626 # Simulator instruction rate (inst/s) -host_mem_usage 154136 # Number of bytes of host memory used +host_inst_rate 30301 # Simulator instruction rate (inst/s) +host_mem_usage 205096 # Number of bytes of host memory used host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 153245779 # Simulator tick rate (ticks/s) +host_tick_rate 151651964 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated sim_ticks 29206500 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.BTBHits 0 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 641 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBLookups 499 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.Branch-Predictor.condIncorrect 666 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index a93b6565a..a56ef0667 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -412,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index f2820f9aa..0c4704bfb 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:23 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 14060500 because target called exit() +Exiting @ tick 14021500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index e79cbdaa4..ab93396d9 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82851 # Simulator instruction rate (inst/s) -host_mem_usage 191760 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 224354167 # Simulator tick rate (ticks/s) +host_inst_rate 60574 # Simulator instruction rate (inst/s) +host_mem_usage 205208 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 163793003 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14060500 # Number of ticks simulated +sim_ticks 14021500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 572 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1960 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1900 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 751 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1593 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2416 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 404 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1589 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2405 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 65 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14561 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.400110 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.121131 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14488 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.402126 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.127822 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 11999 82.41% 82.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1213 8.33% 90.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 529 3.63% 94.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 291 2.00% 96.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 294 2.02% 98.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 71 0.49% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 37 0.25% 99.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 65 0.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11934 82.37% 82.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1210 8.35% 90.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 523 3.61% 94.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 292 2.02% 96.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 294 2.03% 98.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 67 0.46% 98.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 37 0.26% 99.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 69 0.48% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14561 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14488 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed system.cpu.commit.COM:loads 1164 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2089 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 620 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 6017 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5972 # The number of squashed insts skipped by commit system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 5.440511 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.440511 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2321 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34074.626866 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36043.956044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2187 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4566000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.057734 # miss rate for ReadReq accesses +system.cpu.cpi 5.425421 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.425421 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2310 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34156.716418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36032.967033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2176 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4577000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.058009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3280000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039207 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039394 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency @@ -73,56 +73,56 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.226950 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.148936 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3246 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2815 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12754500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.132779 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 3235 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2804 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12765500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.133230 # miss rate for demand accesses system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 5586000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.047913 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 91.308954 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022304 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.357241 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 3235 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2815 # number of overall hits -system.cpu.dcache.overall_miss_latency 12754500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.132779 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2804 # number of overall hits +system.cpu.dcache.overall_miss_latency 12765500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.133230 # miss rate for overall accesses system.cpu.dcache.overall_misses 431 # number of overall misses system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 5586000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.047913 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.308954 # Cycle average of tags in use -system.cpu.dcache.total_refs 2852 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.357241 # Cycle average of tags in use +system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 519 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 139 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 139 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14436 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10077 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3965 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1080 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 521 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 14337 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 10064 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3903 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1073 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -133,151 +133,151 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2416 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2220 # Number of cache lines fetched -system.cpu.fetch.Cycles 6371 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 355 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15622 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 767 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085911 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2220 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.555508 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15641 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.998785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.252974 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2405 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2216 # Number of cache lines fetched +system.cpu.fetch.Cycles 6303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 358 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 15547 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 763 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085758 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2216 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.554379 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.999100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.261901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 11507 73.57% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1847 11.81% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 223 1.43% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 141 0.90% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 312 1.99% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 120 0.77% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 308 1.97% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 254 1.62% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 929 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11491 73.84% 73.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1812 11.64% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 195 1.25% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 140 0.90% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 320 2.06% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 114 0.73% 90.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 289 1.86% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 259 1.66% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 941 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15641 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35681.279621 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34902.735562 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1798 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15057500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.190090 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 15561 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35687.203791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34908.814590 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1794 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15060000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.190433 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11483000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.148198 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 11485000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.148466 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.465046 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.452888 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2220 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency -system.cpu.icache.demand_hits 1798 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15057500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.190090 # miss rate for demand accesses +system.cpu.icache.demand_accesses 2216 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency +system.cpu.icache.demand_hits 1794 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15060000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.190433 # miss rate for demand accesses system.cpu.icache.demand_misses 422 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11483000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.148198 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 11485000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.148466 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076179 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 156.015053 # Average occupied blocks per context -system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.076241 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.140617 # Average occupied blocks per context +system.cpu.icache.overall_accesses 2216 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1798 # number of overall hits -system.cpu.icache.overall_miss_latency 15057500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.190090 # miss rate for overall accesses +system.cpu.icache.overall_hits 1794 # number of overall hits +system.cpu.icache.overall_miss_latency 15060000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.190433 # miss rate for overall accesses system.cpu.icache.overall_misses 422 # number of overall misses system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11483000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.148198 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 11485000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.148466 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.015053 # Cycle average of tags in use -system.cpu.icache.total_refs 1798 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 156.140617 # Cycle average of tags in use +system.cpu.icache.total_refs 1794 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1253 # Number of branches executed -system.cpu.iew.EXEC:nop 1830 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.295249 # Inst execution rate -system.cpu.iew.EXEC:refs 3456 # number of memory reference insts executed +system.cpu.idleCycles 12483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1268 # Number of branches executed +system.cpu.iew.EXEC:nop 1827 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.295643 # Inst execution rate +system.cpu.iew.EXEC:refs 3444 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1049 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4132 # num instructions consuming a value -system.cpu.iew.WB:count 7536 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.703291 # average fanout of values written-back +system.cpu.iew.WB:consumers 4139 # num instructions consuming a value +system.cpu.iew.WB:count 7538 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704035 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2906 # num instructions producing a value -system.cpu.iew.WB:rate 0.267975 # insts written-back per cycle -system.cpu.iew.WB:sent 7618 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 681 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2914 # num instructions producing a value +system.cpu.iew.WB:rate 0.268792 # insts written-back per cycle +system.cpu.iew.WB:sent 7625 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 679 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2806 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2797 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 963 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11847 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2407 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 549 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8303 # Number of executed instructions +system.cpu.iew.iewDispatchedInsts 11802 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2395 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8291 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1080 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1073 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1642 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1633 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 409 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.183806 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.183806 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.184318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184318 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5184 58.56% 58.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2595 29.32% 87.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.02% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5173 58.55% 58.55% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2589 29.30% 87.96% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.04% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8852 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8835 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018301 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.018336 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available @@ -292,31 +292,31 @@ system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # at system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.565948 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.209939 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217819 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 11653 74.50% 74.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1757 11.23% 85.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 814 5.20% 90.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 738 4.72% 95.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 342 2.19% 97.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 199 1.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.58% 99.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.20% 99.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 11605 74.58% 74.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1745 11.21% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 791 5.08% 90.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 727 4.67% 95.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 340 2.18% 97.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 213 1.37% 99.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 93 0.60% 99.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.314771 # Inst issue rate -system.cpu.iq.iqInstsAdded 10005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8852 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.315041 # Inst issue rate +system.cpu.iq.iqInstsAdded 9963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8835 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4214 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 36 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2680 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -337,12 +337,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.221154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12953500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) @@ -364,30 +364,30 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14519500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 210.151573 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006418 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 210.308968 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses system.cpu.l2cache.overall_misses 466 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14519500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -395,27 +395,27 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 210.151573 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 210.308968 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2806 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2797 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28122 # number of cpu cycles simulated +system.cpu.numCycles 28044 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10468 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 10455 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15900 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13681 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8420 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3575 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1080 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 15765 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13587 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8333 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3513 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1073 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5010 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:UndoneMaps 4923 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 496 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 508240960..5fbc0ed64 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -359,7 +359,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 4c710c177..3ef273e4f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 13202840. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 15924344. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 85fc6bc9f..9691f5f7c 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:07 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:43:42 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:43:45 +M5 executing on zizzer command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11960500 because target called exit() +Exiting @ tick 11864500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 4d658aa1d..1e1223443 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 51828 # Simulator instruction rate (inst/s) -host_mem_usage 189300 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 106468871 # Simulator tick rate (ticks/s) +host_inst_rate 50476 # Simulator instruction rate (inst/s) +host_mem_usage 202684 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 102996710 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11960500 # Number of ticks simulated +sim_ticks 11864500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 734 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1942 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 389 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1971 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2303 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 188 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 387 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1757 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2100 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1038 # Number of branches committed system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10831 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.535500 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.248160 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 8265 76.31% 76.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1142 10.54% 86.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 659 6.08% 92.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 268 2.47% 95.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 226 2.09% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 118 1.09% 98.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 80 0.74% 99.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 22 0.20% 99.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 8225 76.26% 76.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1129 10.47% 86.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 673 6.24% 92.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 258 2.39% 95.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 226 2.10% 97.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 120 1.11% 98.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 82 0.76% 99.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 21 0.19% 99.53% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10831 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:loads 962 # Number of loads committed system.cpu.commit.COM:membars 7 # Number of memory barriers committed system.cpu.commit.COM:refs 2008 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 243 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3801 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.124483 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.124483 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1436 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33320.224719 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34437.500000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1347 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2965500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061978 # miss rate for ReadReq accesses +system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1928500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.038997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33497.150997 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35861.538462 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11757500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2331000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.048077 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2482 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33461.363636 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2042 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14723000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.177276 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4259500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.048751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016127 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.056188 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2482 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33461.363636 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2042 # number of overall hits -system.cpu.dcache.overall_miss_latency 14723000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.177276 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2050 # number of overall hits +system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses system.cpu.dcache.overall_misses 440 # number of overall misses system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4259500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.048751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.056188 # Cycle average of tags in use -system.cpu.dcache.total_refs 2085 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use +system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1201 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 148 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 256 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10901 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7556 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2000 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 615 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -134,190 +134,190 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2303 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1463 # Number of cache lines fetched -system.cpu.fetch.Cycles 3604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12241 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 411 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.096271 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1463 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 922 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.511705 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.069457 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched +system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 9306 81.30% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 148 1.29% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 183 1.60% 84.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 143 1.25% 85.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 197 1.72% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 135 1.18% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 371 3.24% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 95 0.83% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 868 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 161 1.42% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 189 1.66% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 155 1.37% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 202 1.78% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 136 1.20% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 272 2.40% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 77 0.68% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11446 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1463 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36616.094987 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34771.212121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1084 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13877500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.259057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 379 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11474500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.225564 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.284848 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.325301 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1463 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36616.094987 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency -system.cpu.icache.demand_hits 1084 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13877500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.259057 # miss rate for demand accesses -system.cpu.icache.demand_misses 379 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 49 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11474500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.225564 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses +system.cpu.icache.demand_misses 386 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077734 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 159.198376 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1463 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36616.094987 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1084 # number of overall hits -system.cpu.icache.overall_miss_latency 13877500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.259057 # miss rate for overall accesses -system.cpu.icache.overall_misses 379 # number of overall misses -system.cpu.icache.overall_mshr_hits 49 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11474500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.225564 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses +system.cpu.icache.overall_hits 1104 # number of overall hits +system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses +system.cpu.icache.overall_misses 386 # number of overall misses +system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 159.198376 # Cycle average of tags in use -system.cpu.icache.total_refs 1084 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use +system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12476 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1260 # Number of branches executed +system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1261 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.324680 # Inst execution rate -system.cpu.iew.EXEC:refs 2768 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1280 # Number of stores executed +system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate +system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1315 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5977 # num instructions consuming a value -system.cpu.iew.WB:count 7563 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.643801 # average fanout of values written-back +system.cpu.iew.WB:consumers 5889 # num instructions consuming a value +system.cpu.iew.WB:count 7582 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3848 # num instructions producing a value -system.cpu.iew.WB:rate 0.316152 # insts written-back per cycle -system.cpu.iew.WB:sent 7622 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1815 # Number of dispatched load instructions +system.cpu.iew.WB:producers 3806 # num instructions producing a value +system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle +system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1394 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9586 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 320 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7767 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9185 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7791 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 615 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 42 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 853 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 348 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 64 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.242455 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.242455 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 719 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 404 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5153 63.72% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1611 19.92% 83.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1321 16.33% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8087 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017435 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8089 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 153 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018915 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.80% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 67 47.52% 55.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 63 44.68% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.19% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11446 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.706535 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384911 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 8157 71.27% 71.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1172 10.24% 81.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 822 7.18% 88.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 530 4.63% 93.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 377 3.29% 96.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 216 1.89% 98.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 120 1.05% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 43 0.38% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 8066 71.03% 71.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1182 10.41% 81.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 820 7.22% 88.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 507 4.46% 93.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 388 3.42% 96.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 218 1.92% 98.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 121 1.07% 99.53% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 46 0.41% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11446 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.338057 # Inst issue rate -system.cpu.iq.iqInstsAdded 9564 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8087 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate +system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3408 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2985 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3586 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -328,28 +328,28 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34697.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1512000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.084656 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12978000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.979275 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 378 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11777000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34235.294118 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 582000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles @@ -357,69 +357,69 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.022161 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34374.413146 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981567 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 426 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13289000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13361000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981651 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 180.652204 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34374.413146 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981567 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 426 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13289000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 426 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13361000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981651 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 428 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 361 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 180.652204 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1815 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1394 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23922 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 356 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 23730 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7745 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 222 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 17199 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10376 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 9321 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1877 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 615 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 273 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4314 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 580 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 571 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index dcbe2d23b..5b9e4a123 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -377,7 +377,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 660b124b5..356c9b63f 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:20:32 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:54:47 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14251500 because target called exit() +Exiting @ tick 14406500 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 016b2b2d7..113c3ed26 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 95914 # Simulator instruction rate (inst/s) -host_mem_usage 191488 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 106648956 # Simulator tick rate (ticks/s) +host_inst_rate 76100 # Simulator instruction rate (inst/s) +host_mem_usage 204896 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 85690748 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14251500 # Number of ticks simulated +sim_ticks 14406500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 4733 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5548 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 801 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4845 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 174 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1651 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3171 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5637 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 690 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches::0 1051 # Number of branches committed system.cpu.commit.COM:branches::1 1051 # Number of branches committed system.cpu.commit.COM:branches::total 2102 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 135 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 23178 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.552550 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.284564 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 16881 73.92% 73.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% 87.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% 93.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% 95.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 326 1.43% 97.14% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 268 1.17% 98.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74% 99.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 122 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 17373 74.95% 74.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 2862 12.35% 87.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1369 5.91% 93.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 536 2.31% 95.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 355 1.53% 97.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 284 1.23% 98.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 169 0.73% 99.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 95 0.41% 99.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 135 0.58% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 22838 # Number of insts commited each cycle -system.cpu.commit.COM:count::0 6403 # Number of instructions committed -system.cpu.commit.COM:count::1 6404 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 23178 # Number of insts commited each cycle +system.cpu.commit.COM:count::0 6404 # Number of instructions committed +system.cpu.commit.COM:count::1 6403 # Number of instructions committed system.cpu.commit.COM:count::total 12807 # Number of instructions committed system.cpu.commit.COM:loads::0 1185 # Number of loads committed system.cpu.commit.COM:loads::1 1185 # Number of loads committed @@ -55,118 +55,118 @@ system.cpu.commit.COM:refs::total 4100 # Nu system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1214 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit -system.cpu.committedInsts::0 6386 # Number of Instructions Simulated -system.cpu.committedInsts::1 6387 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 11211 # The number of squashed insts skipped by commit +system.cpu.committedInsts::0 6387 # Number of Instructions Simulated +system.cpu.committedInsts::1 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35473.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.087898 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052484 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses +system.cpu.cpi::0 4.511351 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.512058 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.255852 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 35613.003096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35613.003096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36812.195122 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3630 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::0 11503000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11503000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081710 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 323 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::0 118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.051859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::0 205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33703.947368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33528.289474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33528.289474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36083.333333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::0 25481500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25481500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::0 6278500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6278500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.282051 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.demand_accesses 5683 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 34150.046168 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34256.561086 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34150.046168 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 4600 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::0 36984500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.195402 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_miss_latency::total 36984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.190568 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1083 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::0 704 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::0 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::total 704 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::0 13825000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency::total 13825000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.066690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067197 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066690 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::0 379 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 379 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.054614 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 223.700041 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.occ_%::0 0.054473 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 223.120996 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5683 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 34150.046168 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34256.561086 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34150.046168 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4550 # number of overall hits -system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles +system.cpu.dcache.overall_hits 4600 # number of overall hits +system.cpu.dcache.overall_miss_latency::0 36984500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.195402 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1105 # number of overall misses -system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits +system.cpu.dcache.overall_miss_latency::total 36984500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.190568 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1083 # number of overall misses +system.cpu.dcache.overall_mshr_hits::0 704 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::0 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_hits::total 704 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::0 13825000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency::total 13825000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.066690 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067197 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066690 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::0 379 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 379 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -176,153 +176,153 @@ system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use -system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 223.120996 # Cycle average of tags in use +system.cpu.dcache.total_refs 4662 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks::0 0 # number of writebacks system.cpu.dcache.writebacks::1 0 # number of writebacks system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 6300 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 451 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 595 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 27842 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 34006 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4930 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2198 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 677 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 6328 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 6155 # DTB hits -system.cpu.dtb.data_misses 145 # DTB misses +system.cpu.dtb.data_hits 6178 # DTB hits +system.cpu.dtb.data_misses 150 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 4144 # DTB read accesses +system.cpu.dtb.read_accesses 4160 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 4056 # DTB read hits +system.cpu.dtb.read_hits 4072 # DTB read hits system.cpu.dtb.read_misses 88 # DTB read misses -system.cpu.dtb.write_accesses 2156 # DTB write accesses +system.cpu.dtb.write_accesses 2168 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2099 # DTB write hits -system.cpu.dtb.write_misses 57 # DTB write misses -system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched -system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 22904 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 2106 # DTB write hits +system.cpu.dtb.write_misses 62 # DTB write misses +system.cpu.fetch.Branches 5637 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4152 # Number of cache lines fetched +system.cpu.fetch.Cycles 9523 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 615 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 31429 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1766 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.195634 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4152 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1491 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.090754 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 23259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.351262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.751825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 17622 76.94% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 416 1.82% 78.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 353 1.54% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 477 2.08% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 425 1.86% 84.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 349 1.52% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 442 1.93% 87.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 261 1.14% 88.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2559 11.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 17946 77.16% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 425 1.83% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 330 1.42% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 452 1.94% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 406 1.75% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 353 1.52% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 452 1.94% 87.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 273 1.17% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2622 11.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35793.697979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.204474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150498 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 23259 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 4152 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 35658.767773 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35658.767773 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35482.171799 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3308 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::0 30096000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30096000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.203276 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 844 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits::0 227 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency::0 21892500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21892500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.148603 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148603 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::0 617 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 617 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.361426 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.demand_accesses 4152 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 35658.767773 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35793.697979 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency::total 35658.767773 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 3308 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::0 30096000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.204474 # miss rate for demand accesses -system.cpu.icache.demand_misses 841 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_miss_latency::total 30096000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.203276 # miss rate for demand accesses +system.cpu.icache.demand_misses 844 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits::0 227 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency::0 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency::0 21892500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency::total 21892500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.148603 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.150498 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_rate::total 0.148603 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::0 617 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 617 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.156877 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 321.284131 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.occ_%::0 0.156062 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 319.614812 # Average occupied blocks per context +system.cpu.icache.overall_accesses 4152 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 35658.767773 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35793.697979 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency::total 35658.767773 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3272 # number of overall hits -system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles +system.cpu.icache.overall_hits 3308 # number of overall hits +system.cpu.icache.overall_miss_latency::0 30096000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.204474 # miss rate for overall accesses -system.cpu.icache.overall_misses 841 # number of overall misses -system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits +system.cpu.icache.overall_miss_latency::total 30096000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.203276 # miss rate for overall accesses +system.cpu.icache.overall_misses 844 # number of overall misses +system.cpu.icache.overall_mshr_hits::0 227 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency::0 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_hits::total 227 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency::0 21892500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency::total 21892500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.148603 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.150498 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_rate::total 0.148603 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::0 617 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 617 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -332,198 +332,198 @@ system.cpu.icache.overall_mshr_uncacheable_misses::total 0 system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 617 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use -system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 319.614812 # Cycle average of tags in use +system.cpu.icache.total_refs 3308 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks::0 0 # number of writebacks system.cpu.icache.writebacks::1 0 # number of writebacks system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches::0 1573 # Number of branches executed -system.cpu.iew.EXEC:branches::1 1587 # Number of branches executed -system.cpu.iew.EXEC:branches::total 3160 # Number of branches executed -system.cpu.iew.EXEC:nop::0 70 # number of nop insts executed -system.cpu.iew.EXEC:nop::1 65 # number of nop insts executed +system.cpu.idleCycles 5555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches::0 1592 # Number of branches executed +system.cpu.iew.EXEC:branches::1 1585 # Number of branches executed +system.cpu.iew.EXEC:branches::total 3177 # Number of branches executed +system.cpu.iew.EXEC:nop::0 69 # number of nop insts executed +system.cpu.iew.EXEC:nop::1 66 # number of nop insts executed system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate -system.cpu.iew.EXEC:refs::0 3132 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::1 3189 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::total 6321 # number of memory reference insts executed -system.cpu.iew.EXEC:stores::0 1090 # Number of stores executed -system.cpu.iew.EXEC:stores::1 1085 # Number of stores executed -system.cpu.iew.EXEC:stores::total 2175 # Number of stores executed +system.cpu.iew.EXEC:rate 0.670750 # Inst execution rate +system.cpu.iew.EXEC:refs::0 3218 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::1 3132 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::total 6350 # number of memory reference insts executed +system.cpu.iew.EXEC:stores::0 1105 # Number of stores executed +system.cpu.iew.EXEC:stores::1 1082 # Number of stores executed +system.cpu.iew.EXEC:stores::total 2187 # Number of stores executed system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed -system.cpu.iew.WB:consumers::0 5984 # num instructions consuming a value -system.cpu.iew.WB:consumers::1 5917 # num instructions consuming a value -system.cpu.iew.WB:consumers::total 11901 # num instructions consuming a value -system.cpu.iew.WB:count::0 9221 # cumulative count of insts written-back -system.cpu.iew.WB:count::1 9205 # cumulative count of insts written-back -system.cpu.iew.WB:count::total 18426 # cumulative count of insts written-back -system.cpu.iew.WB:fanout::0 0.776404 # average fanout of values written-back -system.cpu.iew.WB:fanout::1 0.776407 # average fanout of values written-back -system.cpu.iew.WB:fanout::total 1.552811 # average fanout of values written-back +system.cpu.iew.WB:consumers::0 6017 # num instructions consuming a value +system.cpu.iew.WB:consumers::1 5962 # num instructions consuming a value +system.cpu.iew.WB:consumers::total 11979 # num instructions consuming a value +system.cpu.iew.WB:count::0 9293 # cumulative count of insts written-back +system.cpu.iew.WB:count::1 9238 # cumulative count of insts written-back +system.cpu.iew.WB:count::total 18531 # cumulative count of insts written-back +system.cpu.iew.WB:fanout::0 0.773143 # average fanout of values written-back +system.cpu.iew.WB:fanout::1 0.773398 # average fanout of values written-back +system.cpu.iew.WB:fanout::total 1.546541 # average fanout of values written-back system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers::0 4646 # num instructions producing a value -system.cpu.iew.WB:producers::1 4594 # num instructions producing a value -system.cpu.iew.WB:producers::total 9240 # num instructions producing a value -system.cpu.iew.WB:rate::0 0.323498 # insts written-back per cycle -system.cpu.iew.WB:rate::1 0.322937 # insts written-back per cycle -system.cpu.iew.WB:rate::total 0.646436 # insts written-back per cycle -system.cpu.iew.WB:sent::0 9324 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::1 9340 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::total 18664 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts::0 2042 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2104 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4146 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers::0 4652 # num instructions producing a value +system.cpu.iew.WB:producers::1 4611 # num instructions producing a value +system.cpu.iew.WB:producers::total 9263 # num instructions producing a value +system.cpu.iew.WB:rate::0 0.322517 # insts written-back per cycle +system.cpu.iew.WB:rate::1 0.320608 # insts written-back per cycle +system.cpu.iew.WB:rate::total 0.643125 # insts written-back per cycle +system.cpu.iew.WB:sent::0 9430 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::1 9343 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::total 18773 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1399 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1055 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 5029 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 731 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2605 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 24098 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts::0 2113 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2050 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1224 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 19327 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 2198 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 71 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1385 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 471 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly -system.cpu.ipc::0 0.224039 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.224074 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.1.squashedLoads 1274 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 404 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 135 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1143 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 256 # Number of branches that were predicted taken incorrectly +system.cpu.ipc::0 0.221663 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.221628 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.443291 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6830 67.10% 67.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2173 21.35% 88.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1171 11.50% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6901 66.76% 66.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2273 21.99% 88.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1158 11.20% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 10179 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 10337 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntAlu 6842 67.01% 67.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemRead 2230 21.84% 88.89% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemWrite 1134 11.11% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntAlu 6867 67.23% 67.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemRead 2182 21.36% 88.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemWrite 1160 11.36% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::total 10211 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::total 10214 # Type of FU issued system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntAlu 13672 67.05% 67.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemRead 4403 21.59% 88.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemWrite 2305 11.30% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntAlu 13768 66.99% 67.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemRead 4455 21.68% 88.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemWrite 2318 11.28% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::total 20390 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt::0 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::total 172 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::1 0.004169 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::total 0.008436 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type::total 20551 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt::0 79 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::total 167 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate::0 0.003844 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::1 0.004282 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::total 0.008126 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 13 7.56% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 96 55.81% 63.37% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 63 36.63% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 9 5.39% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 95 56.89% 62.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 63 37.72% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 23259 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.883572 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.458526 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% 61.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% 76.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% 86.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% 92.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% 96.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% 98.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 14576 62.67% 62.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 3197 13.75% 76.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 2342 10.07% 86.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 1327 5.71% 92.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 883 3.80% 95.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 568 2.44% 98.43% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 270 1.16% 99.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 71 0.31% 99.89% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 25 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 22904 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate -system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 23259 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.713230 # Inst issue rate +system.cpu.iq.iqInstsAdded 23917 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 20551 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9939 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5669 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4162 # ITB accesses +system.cpu.itb.fetch_accesses 4210 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 4113 # ITB hits -system.cpu.itb.fetch_misses 49 # ITB misses +system.cpu.itb.fetch_hits 4152 # ITB hits +system.cpu.itb.fetch_misses 58 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -533,116 +533,116 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34623.287671 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34623.287671 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31544.520548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency::0 5055000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5055000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4605500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4605500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34555.285541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 822 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34548.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34548.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31393.902439 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency::0 28329500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28329500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997567 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 820 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25743000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25743000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997567 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997567 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::0 820 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31392.857143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency::0 966000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 966000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 879000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 879000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002525 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::0 34559.523810 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34568.627451 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34559.523810 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::0 33384500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997940 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency::total 33384500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997934 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::0 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30348500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency::total 30348500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997934 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::0 966 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.013297 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 435.713880 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.occ_%::0 0.013217 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 433.083390 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::0 34559.523810 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34568.627451 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34559.523810 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::0 33384500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997940 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 969 # number of overall misses +system.cpu.l2cache.overall_miss_latency::total 33384500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997934 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 966 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::0 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30348500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 30348500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997934 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::0 966 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -652,42 +652,43 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 433.083390 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks::0 0 # number of writebacks system.cpu.l2cache.writebacks::1 0 # number of writebacks system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1282 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 58 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 32 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1303 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28504 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2570 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 27 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 5 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2459 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1269 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 28814 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2841 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 34469 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1383 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 850 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 33146 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 26493 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19854 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4562 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2198 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1440 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10688 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3428 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 0cc32d77e..927a68251 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index a6f645c41..8a865dd25 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:00 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:45:56 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:47:29 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 27756500 because target called exit() +Exiting @ tick 27640500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d92dfc078..bf26975cc 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,336 +1,336 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 72869 # Simulator instruction rate (inst/s) -host_mem_usage 190800 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 139786869 # Simulator tick rate (ticks/s) +host_inst_rate 58626 # Simulator instruction rate (inst/s) +host_mem_usage 204232 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 112030496 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27756500 # Number of ticks simulated +sim_ticks 27640500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 4398 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 9844 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 4205 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 9185 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11413 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 11413 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 2913 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11479 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 11479 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 42766 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.354838 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 0.957636 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 42520 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.356891 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 0.964493 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 34594 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 4804 11.23% 92.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 1741 4.07% 96.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 720 1.68% 97.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 413 0.97% 98.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 144 0.34% 99.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 196 0.46% 99.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 51 0.12% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 103 0.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 34367 80.83% 80.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 4806 11.30% 92.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1719 4.04% 96.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 713 1.68% 97.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 414 0.97% 98.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 146 0.34% 99.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 193 0.45% 99.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 48 0.11% 99.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 114 0.27% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 42520 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 3674 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2913 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 19910 # The number of squashed insts skipped by commit system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses +system.cpu.cpi 3.826009 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.826009 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35228.070175 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3728 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4016000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2311500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016918 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31248.306998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35612.745098 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13843000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3632500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 32.222973 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses -system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 5284 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32062.836625 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4727 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17859000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.105413 # miss rate for demand accesses +system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 390 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5944000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031605 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026530 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 108.665251 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.026503 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 108.555093 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5284 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32062.836625 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4728 # number of overall hits -system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses -system.cpu.dcache.overall_misses 558 # number of overall misses -system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 4727 # number of overall hits +system.cpu.dcache.overall_miss_latency 17859000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.105413 # miss rate for overall accesses +system.cpu.dcache.overall_misses 557 # number of overall misses +system.cpu.dcache.overall_mshr_hits 390 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5944000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031605 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use -system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 108.555093 # Cycle average of tags in use +system.cpu.dcache.total_refs 4769 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched -system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3018 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 47090 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.236929 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.372442 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 7141 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 51862 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 20451 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14795 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4325 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 11479 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7330 # Number of cache lines fetched +system.cpu.fetch.Cycles 23798 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 830 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 58419 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.207644 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4205 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.056745 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 46845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.247070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.396969 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 30448 64.66% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 7532 15.99% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1217 2.58% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 1059 2.25% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 1060 2.25% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1193 2.53% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 711 1.51% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 327 0.69% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3543 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 30399 64.89% 64.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 7442 15.89% 80.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1110 2.37% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 985 2.10% 85.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 1044 2.23% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1211 2.59% 90.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 663 1.42% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 335 0.72% 92.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3656 7.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47090 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 46845 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 7330 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33618.691589 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34870.473538 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6795 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 17986000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.072988 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 12518500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.048977 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.980447 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency -system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses +system.cpu.icache.demand_accesses 7330 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33618.691589 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency +system.cpu.icache.demand_hits 6795 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 17986000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.072988 # miss rate for demand accesses system.cpu.icache.demand_misses 535 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 12518500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.048977 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.110760 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 226.836007 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.110625 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 226.560324 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7330 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33618.691589 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6821 # number of overall hits -system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses +system.cpu.icache.overall_hits 6795 # number of overall hits +system.cpu.icache.overall_miss_latency 17986000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.072988 # miss rate for overall accesses system.cpu.icache.overall_misses 535 # number of overall misses system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 12518500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.048977 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use -system.cpu.icache.total_refs 6821 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 226.560324 # Cycle average of tags in use +system.cpu.icache.total_refs 6795 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 4842 # Number of branches executed -system.cpu.iew.EXEC:nop 2091 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate -system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2454 # Number of stores executed +system.cpu.idleCycles 8437 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4838 # Number of branches executed +system.cpu.iew.EXEC:nop 2088 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.449477 # Inst execution rate +system.cpu.iew.EXEC:refs 6429 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2469 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 13039 # num instructions consuming a value +system.cpu.iew.WB:consumers 13103 # num instructions consuming a value system.cpu.iew.WB:count 23891 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back +system.cpu.iew.WB:fanout 0.824239 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 10787 # num instructions producing a value -system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle -system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 10800 # num instructions producing a value +system.cpu.iew.WB:rate 0.432166 # insts written-back per cycle +system.cpu.iew.WB:sent 24095 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3199 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 4967 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions +system.cpu.iew.iewDispSquashedInsts 3043 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3406 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewExecLoadInsts 3960 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4355 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 24848 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 4325 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 36 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 2741 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1958 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 814 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2385 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.261369 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.261369 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 21395 73.22% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 4720 16.15% 89.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 3105 10.63% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 21370 73.18% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 4722 16.17% 89.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 3111 10.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 29220 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 29203 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 177 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006061 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40 23.12% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 20 11.56% 34.68% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 113 65.32% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 44 24.86% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 20 11.30% 36.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 113 63.84% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 46845 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.623396 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.283288 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% 72.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% 84.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% 90.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% 95.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% 97.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% 98.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% 99.46% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 33954 72.48% 72.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 5459 11.65% 84.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 3016 6.44% 90.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 2133 4.55% 95.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 995 2.12% 97.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 695 1.48% 98.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 336 0.72% 99.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 214 0.46% 99.91% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 47090 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate -system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 46845 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.528255 # Inst issue rate +system.cpu.iq.iqInstsAdded 32305 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29203 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15689 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 12321 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.590361 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31313.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2855000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2599000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34219.047619 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.761905 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14372000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13022000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34342.105263 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 652500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles @@ -345,31 +345,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34248.508946 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 17227000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15621000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.007680 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 251.642612 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.007671 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 251.347828 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34248.508946 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 17227000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses system.cpu.l2cache.overall_misses 503 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15621000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -377,31 +377,31 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 251.347828 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 3415 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 55514 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 4967 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 3406 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 55282 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 31 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 22239 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenameLookups 74814 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 42611 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:RunCycles 13163 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4325 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 313 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializeStallCycles 6774 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5153 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 824 # count of temporary serializing insts renamed system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 2fffc58e2..e7279bca8 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -317,7 +317,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 1d66e4129..e80cf75e8 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,34 +5,34 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:02 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:45:56 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:45:58 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 1, Thread 3] Got lock [Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 @@ -41,26 +41,26 @@ Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 Iteration 4 completed -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 Iteration 5 completed -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 Iteration 7 completed [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 @@ -69,19 +69,19 @@ Iteration 7 completed [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 220484500 because target called exit() +Exiting @ tick 217002500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 75d6c02bb..a59d4f21a 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,943 +1,942 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 38759 # Simulator instruction rate (inst/s) -host_mem_usage 200852 # Number of bytes of host memory used -host_seconds 11.32 # Real time elapsed on the host -host_tick_rate 19469095 # Simulator tick rate (ticks/s) +host_inst_rate 71817 # Simulator instruction rate (inst/s) +host_mem_usage 214292 # Number of bytes of host memory used +host_seconds 6.05 # Real time elapsed on the host +host_tick_rate 35890036 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 438923 # Number of instructions simulated -sim_seconds 0.000220 # Number of seconds simulated -sim_ticks 220484500 # Number of ticks simulated +sim_insts 434213 # Number of instructions simulated +sim_seconds 0.000217 # Number of seconds simulated +sim_ticks 217002500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 54549 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 70955 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 52073 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 66680 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 31037 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 79925 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 79925 # Number of BP lookups +system.cpu0.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 81408 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 81408 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 25657 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 567 # number cycles where commit BW limit reached +system.cpu0.commit.COM:branches 25190 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 355685 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.364783 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 0.822342 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0-1 269749 75.84% 75.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1-2 56588 15.91% 91.75% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2-3 24519 6.89% 98.64% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3-4 1287 0.36% 99.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4-5 786 0.22% 99.23% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5-6 567 0.16% 99.38% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6-7 1608 0.45% 99.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 567 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0-1 262750 75.72% 75.72% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1-2 55494 15.99% 91.71% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2-3 23803 6.86% 98.57% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3-4 1293 0.37% 98.94% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4-5 820 0.24% 99.18% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5-6 559 0.16% 99.34% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6-7 1671 0.48% 99.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7-8 40 0.01% 99.83% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 355685 # Number of insts commited each cycle -system.cpu0.commit.COM:count 129748 # Number of instructions committed -system.cpu0.commit.COM:loads 30551 # Number of loads committed -system.cpu0.commit.COM:membars 8310 # Number of memory barriers committed -system.cpu0.commit.COM:refs 41937 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle +system.cpu0.commit.COM:count 127984 # Number of instructions committed +system.cpu0.commit.COM:loads 30137 # Number of loads committed +system.cpu0.commit.COM:membars 7796 # Number of memory barriers committed +system.cpu0.commit.COM:refs 41570 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 31037 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 129748 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 9029 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 140741 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 104996 # Number of Instructions Simulated -system.cpu0.committedInsts_total 104996 # Number of Instructions Simulated -system.cpu0.cpi 3.832270 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.832270 # CPI: Total CPI of All Threads -system.cpu0.dcache.ReadReq_accesses 29224 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 18192.118227 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 15806.818182 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 29021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 3693000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.006946 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 203 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 2782000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.006022 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 176 # number of ReadReq MSHR misses -system.cpu0.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 21093.220339 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 22239.583333 # average SwapReq mshr miss latency +system.cpu0.commit.branchMispredicts 30422 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 127984 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 104211 # Number of Instructions Simulated +system.cpu0.committedInsts_total 104211 # Number of Instructions Simulated +system.cpu0.cpi 3.794734 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.794734 # CPI: Total CPI of All Threads +system.cpu0.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 28373 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 209 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses +system.cpu0.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 1244500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_rate 0.808219 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_misses 59 # number of SwapReq misses +system.cpu0.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_misses 57 # number of SwapReq misses system.cpu0.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits -system.cpu0.dcache.SwapReq_mshr_miss_latency 1067500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.657534 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_misses 48 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 11313 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 23258.064516 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 14768.867925 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 11189 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 2884000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.010961 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu0.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 11234 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 128 # number of WriteReq misses system.cpu0.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 1565500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 735.966667 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 708.483871 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 40537 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 20113.149847 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 40210 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 6577000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.008067 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 327 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 4347500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.006957 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 282 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_accesses 39944 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 39607 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 337 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.055235 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 28.280349 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 40537 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 20113.149847 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 39944 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 40210 # number of overall hits -system.cpu0.dcache.overall_miss_latency 6577000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.008067 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 327 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 4347500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.006957 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 282 # number of overall MSHR misses +system.cpu0.dcache.overall_hits 39607 # number of overall hits +system.cpu0.dcache.overall_miss_latency 7104000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 337 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 53 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 284 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu0.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 28.280349 # Cycle average of tags in use -system.cpu0.dcache.total_refs 22079 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 29.152957 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21963 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 1 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 31385 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:DecodedInsts 367055 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 175688 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 148454 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 34938 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:UnblockCycles 158 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 79925 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 83600 # Number of cache lines fetched -system.cpu0.fetch.Cycles 244044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 9987 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 413648 # Number of instructions fetch has processed -system.cpu0.fetch.SquashCycles 31188 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.198634 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 83600 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 54549 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 1.028021 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 399788 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.034668 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.929402 # Number of instructions fetched each cycle (Total) +system.cpu0.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 144226 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking +system.cpu0.fetch.Branches 81408 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 81347 # Number of cache lines fetched +system.cpu0.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 412447 # Number of instructions fetch has processed +system.cpu0.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.205860 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 1.042974 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0-1 239369 59.87% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1-2 86666 21.68% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2-3 18970 4.75% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3-4 18363 4.59% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4-5 2993 0.75% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5-6 13233 3.31% 94.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6-7 1665 0.42% 95.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7-8 2406 0.60% 95.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 16123 4.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 399788 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses 83600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14035.763411 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11552.755906 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 82873 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 10204000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.008696 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 727 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7336000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.007596 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 635 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 80599 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 748 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 130.508661 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.avg_refs 127.530063 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 83600 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14035.763411 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency -system.cpu0.icache.demand_hits 82873 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 10204000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.008696 # miss rate for demand accesses -system.cpu0.icache.demand_misses 727 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7336000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.007596 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_accesses 81347 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency +system.cpu0.icache.demand_hits 80599 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.009195 # miss rate for demand accesses +system.cpu0.icache.demand_misses 748 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.187347 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 95.921890 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 83600 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14035.763411 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.191179 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 97.883584 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 81347 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 82873 # number of overall hits -system.cpu0.icache.overall_miss_latency 10204000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.008696 # miss rate for overall accesses -system.cpu0.icache.overall_misses 727 # number of overall misses -system.cpu0.icache.overall_mshr_hits 92 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7336000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.007596 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.icache.overall_hits 80599 # number of overall hits +system.cpu0.icache.overall_miss_latency 14184500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.009195 # miss rate for overall accesses +system.cpu0.icache.overall_misses 748 # number of overall misses +system.cpu0.icache.overall_mshr_hits 116 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 632 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 524 # number of replacements -system.cpu0.icache.sampled_refs 635 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 522 # number of replacements +system.cpu0.icache.sampled_refs 632 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 95.921890 # Cycle average of tags in use -system.cpu0.icache.total_refs 82873 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 97.883584 # Cycle average of tags in use +system.cpu0.icache.total_refs 80599 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 2585 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 37656 # Number of branches executed -system.cpu0.iew.EXEC:nop 48476 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.417965 # Inst execution rate -system.cpu0.iew.EXEC:refs 49837 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 13176 # Number of stores executed +system.cpu0.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 37149 # Number of branches executed +system.cpu0.iew.EXEC:nop 47058 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.419532 # Inst execution rate +system.cpu0.iew.EXEC:refs 49104 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 13043 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 81944 # num instructions consuming a value -system.cpu0.iew.WB:count 164449 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.932149 # average fanout of values written-back +system.cpu0.iew.WB:consumers 81150 # num instructions consuming a value +system.cpu0.iew.WB:count 162295 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.931855 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 76384 # num instructions producing a value -system.cpu0.iew.WB:rate 0.408698 # insts written-back per cycle -system.cpu0.iew.WB:sent 164672 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 31697 # Number of branch mispredicts detected at execute +system.cpu0.iew.WB:producers 75620 # num instructions producing a value +system.cpu0.iew.WB:rate 0.410403 # insts written-back per cycle +system.cpu0.iew.WB:sent 162544 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute system.cpu0.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 41051 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 9374 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 4077 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 22447 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 270509 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 36661 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 34703 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 168178 # Number of executed instructions +system.cpu0.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 36061 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 165905 # Number of executed instructions system.cpu0.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 34938 # Number of cycles IEW is squashing +system.cpu0.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 7417 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 646 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 10500 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 11061 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 646 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 856 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 30841 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.260942 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.260942 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 698 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.263523 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.263523 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 142871 70.42% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 46166 22.76% 93.18% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13844 6.82% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 202881 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 23 13.29% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 11 6.36% 19.65% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 139 80.35% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 399788 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.507471 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.960639 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 279763 69.98% 69.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 72065 18.03% 88.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 24983 6.25% 94.25% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14756 3.69% 97.94% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5406 1.35% 99.30% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2153 0.54% 99.83% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 473 0.12% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 157 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 32 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 272942 69.93% 69.93% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 69416 17.79% 87.72% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 25173 6.45% 94.16% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14490 3.71% 97.88% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5424 1.39% 99.27% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2186 0.56% 99.83% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 485 0.12% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 162 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 399788 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.504211 # Inst issue rate -system.cpu0.iq.iqInstsAdded 204299 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 202881 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 17734 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 79448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.506068 # Inst issue rate +system.cpu0.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 200126 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 8705 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 34402 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.memDep0.conflictingLoads 7616 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 83 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 41051 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 22447 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 402373 # number of cpu cycles simulated -system.cpu0.rename.RENAME:CommittedMaps 87918 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IdleCycles 188663 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:RenameLookups 464430 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 298607 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 213629 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 135723 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 34938 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 563 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 125711 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 30736 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 9619 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 36235 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 9747 # count of temporary serializing insts renamed -system.cpu0.timesIdled 284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.memDep0.conflictingLoads 7669 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 92 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 395453 # number of cpu cycles simulated +system.cpu0.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle +system.cpu0.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 131636 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed +system.cpu0.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 53615 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 73516 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 48405 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 65841 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 30904 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 87311 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 87311 # Number of BP lookups +system.cpu1.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 82266 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 82266 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 25648 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 570 # number cycles where commit BW limit reached +system.cpu1.commit.COM:branches 25082 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 355192 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.364749 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 0.823293 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0-1 269483 75.87% 75.87% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1-2 56385 15.87% 91.74% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2-3 24471 6.89% 98.63% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3-4 1296 0.36% 99.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4-5 793 0.22% 99.22% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5-6 569 0.16% 99.38% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6-7 1611 0.45% 99.84% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 570 0.16% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0-1 257870 74.41% 74.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1-2 60023 17.32% 91.73% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2-3 23680 6.83% 98.57% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3-4 1288 0.37% 98.94% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4-5 802 0.23% 99.17% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5-6 567 0.16% 99.33% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6-7 1691 0.49% 99.82% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7-8 39 0.01% 99.83% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 355192 # Number of insts commited each cycle -system.cpu1.commit.COM:count 129556 # Number of instructions committed -system.cpu1.commit.COM:loads 30466 # Number of loads committed -system.cpu1.commit.COM:membars 8390 # Number of memory barriers committed -system.cpu1.commit.COM:refs 41763 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle +system.cpu1.commit.COM:count 132317 # Number of instructions committed +system.cpu1.commit.COM:loads 32415 # Number of loads committed +system.cpu1.commit.COM:membars 5314 # Number of memory barriers committed +system.cpu1.commit.COM:refs 46218 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 30904 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 129556 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 9104 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 142883 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 104728 # Number of Instructions Simulated -system.cpu1.committedInsts_total 104728 # Number of Instructions Simulated -system.cpu1.cpi 3.839040 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 3.839040 # CPI: Total CPI of All Threads -system.cpu1.dcache.ReadReq_accesses 29199 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 17894.736842 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 15858.433735 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 29009 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 3400000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.006507 # miss rate for ReadReq accesses +system.cpu1.commit.branchMispredicts 32660 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 132317 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 111128 # Number of Instructions Simulated +system.cpu1.committedInsts_total 111128 # Number of Instructions Simulated +system.cpu1.cpi 3.555675 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 3.555675 # CPI: Total CPI of All Threads +system.cpu1.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 28295 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses 190 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 24 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 2632500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.005685 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 166 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 22592.592593 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 24604.651163 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 1220000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.794118 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_miss_latency 1058000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.632353 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_misses 43 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 11229 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 23876.984127 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15889.908257 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 11103 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 3008500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.011221 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 126 # number of WriteReq misses +system.cpu1.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses +system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_misses 53 # number of SwapReq misses +system.cpu1.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 13609 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 129 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1732000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.009707 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 709.516129 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 810.166667 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 40428 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 20280.063291 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 40112 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 6408500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.007816 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 316 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4364500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.006802 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_accesses 42223 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 41904 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 319 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.053563 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 27.424102 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 40428 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 20280.063291 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 42223 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 40112 # number of overall hits -system.cpu1.dcache.overall_miss_latency 6408500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.007816 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 316 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4364500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.006802 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 275 # number of overall MSHR misses +system.cpu1.dcache.overall_hits 41904 # number of overall hits +system.cpu1.dcache.overall_miss_latency 6082500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 319 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 52 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 27.424102 # Cycle average of tags in use -system.cpu1.dcache.total_refs 21995 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 28.067737 # Cycle average of tags in use +system.cpu1.dcache.total_refs 24305 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 31080 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:DecodedInsts 370792 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 175773 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 148188 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 35250 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 145919 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing system.cpu1.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking -system.cpu1.fetch.Branches 87311 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 83559 # Number of cache lines fetched -system.cpu1.fetch.Cycles 243794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 9908 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 428254 # Number of instructions fetch has processed -system.cpu1.fetch.SquashCycles 31054 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.217162 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 83559 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 53615 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.065163 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 399545 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.071854 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.991830 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.Branches 82266 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 80954 # Number of cache lines fetched +system.cpu1.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 435938 # Number of instructions fetch has processed +system.cpu1.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.208197 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 1.103263 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0-1 239335 59.90% 59.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1-2 86108 21.55% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2-3 18621 4.66% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3-4 13625 3.41% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4-5 2965 0.74% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5-6 17436 4.36% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6-7 2130 0.53% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7-8 2391 0.60% 95.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 16934 4.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 399545 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses 83559 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 13800.273598 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11301.412873 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 82828 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 10088000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.008748 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 731 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 7199000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.007623 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 637 # number of ReadReq MSHR misses +system.cpu1.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 80218 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 736 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 130.028257 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 125.536776 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 83559 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 13800.273598 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency -system.cpu1.icache.demand_hits 82828 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 10088000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.008748 # miss rate for demand accesses -system.cpu1.icache.demand_misses 731 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 94 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 7199000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.007623 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 637 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_accesses 80954 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency +system.cpu1.icache.demand_hits 80218 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.009092 # miss rate for demand accesses +system.cpu1.icache.demand_misses 736 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.183643 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 94.025224 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 83559 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 13800.273598 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.188794 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 96.662446 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 80954 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 82828 # number of overall hits -system.cpu1.icache.overall_miss_latency 10088000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.008748 # miss rate for overall accesses -system.cpu1.icache.overall_misses 731 # number of overall misses -system.cpu1.icache.overall_mshr_hits 94 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 7199000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.007623 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 637 # number of overall MSHR misses +system.cpu1.icache.overall_hits 80218 # number of overall hits +system.cpu1.icache.overall_miss_latency 10255000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.009092 # miss rate for overall accesses +system.cpu1.icache.overall_misses 736 # number of overall misses +system.cpu1.icache.overall_mshr_hits 97 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 639 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 525 # number of replacements -system.cpu1.icache.sampled_refs 637 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 527 # number of replacements +system.cpu1.icache.sampled_refs 639 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 94.025224 # Cycle average of tags in use -system.cpu1.icache.total_refs 82828 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 96.662446 # Cycle average of tags in use +system.cpu1.icache.total_refs 80218 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 2510 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 37542 # Number of branches executed -system.cpu1.iew.EXEC:nop 48922 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.416853 # Inst execution rate -system.cpu1.iew.EXEC:refs 49631 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 13081 # Number of stores executed +system.cpu1.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 39408 # Number of branches executed +system.cpu1.iew.EXEC:nop 47237 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.449348 # Inst execution rate +system.cpu1.iew.EXEC:refs 53769 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 15425 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 81643 # num instructions consuming a value -system.cpu1.iew.WB:count 163892 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.931911 # average fanout of values written-back +system.cpu1.iew.WB:consumers 88234 # num instructions consuming a value +system.cpu1.iew.WB:count 173934 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.937246 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 76084 # num instructions producing a value -system.cpu1.iew.WB:rate 0.407636 # insts written-back per cycle -system.cpu1.iew.WB:sent 164117 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 31560 # Number of branch mispredicts detected at execute +system.cpu1.iew.WB:producers 82697 # num instructions producing a value +system.cpu1.iew.WB:rate 0.440189 # insts written-back per cycle +system.cpu1.iew.WB:sent 174194 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 41822 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 9263 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 4013 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 22260 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 272458 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 36550 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 35100 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 167598 # Number of executed instructions +system.cpu1.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 38344 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 177553 # Number of executed instructions system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 35250 # Number of cycles IEW is squashing +system.cpu1.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 7331 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 641 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 11356 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 10963 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 641 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 844 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 30716 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.260482 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.260482 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 701 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.281241 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.281241 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 142808 70.45% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 46141 22.76% 93.22% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 13749 6.78% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 202698 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 23 13.29% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 11 6.36% 19.65% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 139 80.35% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 399545 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.507322 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.960841 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 279804 70.03% 70.03% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 71581 17.92% 87.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 25282 6.33% 94.27% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 14650 3.67% 97.94% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.36% 99.30% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2146 0.54% 99.83% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 473 0.12% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 157 0.04% 99.99% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 32 0.01% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 270914 69.00% 69.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 66150 16.85% 85.85% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 30383 7.74% 93.59% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 16859 4.29% 97.88% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.38% 99.26% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2202 0.56% 99.83% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 491 0.13% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 161 0.04% 99.99% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 399545 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.504155 # Inst issue rate -system.cpu1.iq.iqInstsAdded 205352 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 202698 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 18184 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 81269 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 9080 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 37464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.memDep0.conflictingLoads 8438 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 93 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 41822 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 22260 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 402055 # number of cpu cycles simulated -system.cpu1.rename.RENAME:CommittedMaps 87658 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IdleCycles 188598 # Number of cycles rename is idle +system.cpu1.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.542923 # Inst issue rate +system.cpu1.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 214528 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.memDep0.conflictingLoads 10938 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 96 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 395135 # number of cpu cycles simulated +system.cpu1.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:RenameLookups 466261 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 302877 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 213560 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 135600 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 35250 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 564 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 125902 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 30430 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 9493 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 36017 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 9618 # count of temporary serializing insts renamed -system.cpu1.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 130989 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed +system.cpu1.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.BTBHits 44906 # Number of BTB hits -system.cpu2.BPredUnit.BTBLookups 70035 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 44089 # Number of BTB hits +system.cpu2.BPredUnit.BTBLookups 68672 # Number of BTB lookups system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu2.BPredUnit.condIncorrect 43027 # Number of conditional branches incorrect -system.cpu2.BPredUnit.condPredicted 71789 # Number of conditional branches predicted -system.cpu2.BPredUnit.lookups 71789 # Number of BP lookups +system.cpu2.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect +system.cpu2.BPredUnit.condPredicted 70853 # Number of conditional branches predicted +system.cpu2.BPredUnit.lookups 70853 # Number of BP lookups system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.commit.COM:branches 23667 # Number of branches committed -system.cpu2.commit.COM:bw_lim_events 171 # number cycles where commit BW limit reached +system.cpu2.commit.COM:branches 23275 # Number of branches committed +system.cpu2.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.commit.COM:committed_per_cycle::samples 377940 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::mean 0.368394 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::stdev 0.672472 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::0-1 268475 71.04% 71.04% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::1-2 84750 22.42% 93.46% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::2-3 22813 6.04% 99.50% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::3-4 683 0.18% 99.68% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::4-5 329 0.09% 99.76% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::5-6 229 0.06% 99.83% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::6-7 453 0.12% 99.94% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::7-8 37 0.01% 99.95% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::8 171 0.05% 100.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::0-1 264099 71.08% 71.08% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::1-2 83154 22.38% 93.46% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::2-3 22390 6.03% 99.48% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::3-4 687 0.18% 99.67% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::4-5 334 0.09% 99.76% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::5-6 230 0.06% 99.82% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::6-7 452 0.12% 99.94% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::7-8 34 0.01% 99.95% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::total 377940 # Number of insts commited each cycle -system.cpu2.commit.COM:count 139231 # Number of instructions committed -system.cpu2.commit.COM:loads 42546 # Number of loads committed +system.cpu2.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle +system.cpu2.commit.COM:count 136879 # Number of instructions committed +system.cpu2.commit.COM:loads 41762 # Number of loads committed system.cpu2.commit.COM:membars 84 # Number of memory barriers committed -system.cpu2.commit.COM:refs 64325 # Number of memory references committed +system.cpu2.commit.COM:refs 63149 # Number of memory references committed system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.branchMispredicts 43027 # The number of times a branch was mispredicted -system.cpu2.commit.commitCommittedInsts 139231 # The number of committed instructions +system.cpu2.commit.branchMispredicts 42322 # The number of times a branch was mispredicted +system.cpu2.commit.commitCommittedInsts 136879 # The number of committed instructions system.cpu2.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.commitSquashedInsts 182418 # The number of squashed insts skipped by commit -system.cpu2.committedInsts 118749 # Number of Instructions Simulated -system.cpu2.committedInsts_total 118749 # Number of Instructions Simulated -system.cpu2.cpi 3.713463 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.713463 # CPI: Total CPI of All Threads -system.cpu2.dcache.ReadReq_accesses 24971 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 30599.025974 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 23979.820628 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 24663 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 9424500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.012334 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 308 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_miss_latency 5347500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.008930 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 223 # number of ReadReq MSHR misses +system.cpu2.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit +system.cpu2.committedInsts 116789 # Number of Instructions Simulated +system.cpu2.committedInsts_total 116789 # Number of Instructions Simulated +system.cpu2.cpi 3.716155 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.716155 # CPI: Total CPI of All Threads +system.cpu2.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 24347 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 318 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu2.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 15538.461538 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 12538.461538 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 404000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 326000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 21737 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 45735.701906 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 39151.515152 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 21160 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 26389500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.026545 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 20768 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_misses 577 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_hits 379 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_miss_latency 7752000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009109 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 198 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 168.806818 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 162.931818 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 46708 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 40467.796610 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 45823 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 35814000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.018948 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 885 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 464 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 13099500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.009013 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 421 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_accesses 46010 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 45115 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 895 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.285109 # Average percentage of cache occupancy -system.cpu2.dcache.occ_%::1 -0.006965 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 145.975885 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -3.566137 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 46708 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 40467.796610 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 46010 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 45823 # number of overall hits -system.cpu2.dcache.overall_miss_latency 35814000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.018948 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 885 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 464 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 13099500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.009013 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 421 # number of overall MSHR misses +system.cpu2.dcache.overall_hits 45115 # number of overall hits +system.cpu2.dcache.overall_miss_latency 36067000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 895 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 467 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 428 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.dcache.replacements 10 # number of replacements system.cpu2.dcache.sampled_refs 176 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 142.409748 # Cycle average of tags in use -system.cpu2.dcache.total_refs 29710 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 141.792519 # Cycle average of tags in use +system.cpu2.dcache.total_refs 28676 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 6 # number of writebacks -system.cpu2.decode.DECODE:BlockedCycles 54269 # Number of cycles decode is blocked -system.cpu2.decode.DECODE:DecodedInsts 458617 # Number of instructions handled by decode -system.cpu2.decode.DECODE:IdleCycles 166605 # Number of cycles decode is idle -system.cpu2.decode.DECODE:RunCycles 156987 # Number of cycles decode is running -system.cpu2.decode.DECODE:SquashCycles 44866 # Number of cycles decode is squashing -system.cpu2.decode.DECODE:UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu2.fetch.Branches 71789 # Number of branches that fetch encountered -system.cpu2.fetch.CacheLines 88443 # Number of cache lines fetched -system.cpu2.fetch.Cycles 246728 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.IcacheSquashes 21058 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.Insts 464576 # Number of instructions fetch has processed -system.cpu2.fetch.SquashCycles 43179 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.162798 # Number of branch fetches per cycle -system.cpu2.fetch.icacheStallCycles 88443 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.predictedBranches 44906 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.053532 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 422806 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.098792 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.122739 # Number of instructions fetched each cycle (Total) +system.cpu2.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked +system.cpu2.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode +system.cpu2.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle +system.cpu2.decode.DECODE:RunCycles 154431 # Number of cycles decode is running +system.cpu2.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing +system.cpu2.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking +system.cpu2.fetch.Branches 70853 # Number of branches that fetch encountered +system.cpu2.fetch.CacheLines 87025 # Number of cache lines fetched +system.cpu2.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.Insts 457882 # Number of instructions fetch has processed +system.cpu2.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing +system.cpu2.fetch.branchRate 0.163254 # Number of branch fetches per cycle +system.cpu2.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken +system.cpu2.fetch.rate 1.055013 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0-1 264558 62.57% 62.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1-2 88255 20.87% 83.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2-3 1011 0.24% 83.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3-4 21518 5.09% 88.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4-5 1067 0.25% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5-6 21230 5.02% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6-7 652 0.15% 94.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7-8 705 0.17% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 23810 5.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0-1 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1-2 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2-3 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3-4 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4-5 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5-6 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6-7 680 0.16% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7-8 710 0.17% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 422806 # Number of instructions fetched each cycle (Total) -system.cpu2.icache.ReadReq_accesses 88443 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 37054.535017 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35099.253731 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 87572 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 32274500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.009848 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 871 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_miss_latency 23516500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.007576 # mshr miss rate for ReadReq accesses +system.cpu2.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total) +system.cpu2.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 86155 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 870 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 130.899851 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 128.781764 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 88443 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 37054.535017 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency -system.cpu2.icache.demand_hits 87572 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 32274500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.009848 # miss rate for demand accesses -system.cpu2.icache.demand_misses 871 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 23516500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.007576 # mshr miss rate for demand accesses +system.cpu2.icache.demand_accesses 87025 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency +system.cpu2.icache.demand_hits 86155 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.009997 # miss rate for demand accesses +system.cpu2.icache.demand_misses 870 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.526897 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 269.771036 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 88443 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 37054.535017 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.526442 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 269.538121 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 87025 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 87572 # number of overall hits -system.cpu2.icache.overall_miss_latency 32274500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.009848 # miss rate for overall accesses -system.cpu2.icache.overall_misses 871 # number of overall misses -system.cpu2.icache.overall_mshr_hits 201 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 23516500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.007576 # mshr miss rate for overall accesses +system.cpu2.icache.overall_hits 86155 # number of overall hits +system.cpu2.icache.overall_miss_latency 32248500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.009997 # miss rate for overall accesses +system.cpu2.icache.overall_misses 870 # number of overall misses +system.cpu2.icache.overall_mshr_hits 200 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_misses 670 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.icache.replacements 363 # number of replacements system.cpu2.icache.sampled_refs 669 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 269.771036 # Cycle average of tags in use -system.cpu2.icache.total_refs 87572 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 269.538121 # Cycle average of tags in use +system.cpu2.icache.total_refs 86155 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idleCycles 18164 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.iew.EXEC:branches 45174 # Number of branches executed -system.cpu2.iew.EXEC:nop 60963 # number of nop insts executed -system.cpu2.iew.EXEC:rate 0.434102 # Inst execution rate -system.cpu2.iew.EXEC:refs 67735 # number of memory reference insts executed -system.cpu2.iew.EXEC:stores 22705 # Number of stores executed +system.cpu2.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.iew.EXEC:branches 44503 # Number of branches executed +system.cpu2.iew.EXEC:nop 59775 # number of nop insts executed +system.cpu2.iew.EXEC:rate 0.434987 # Inst execution rate +system.cpu2.iew.EXEC:refs 66647 # number of memory reference insts executed +system.cpu2.iew.EXEC:stores 22312 # Number of stores executed system.cpu2.iew.EXEC:swp 0 # number of swp insts executed -system.cpu2.iew.WB:consumers 96501 # num instructions consuming a value -system.cpu2.iew.WB:count 189859 # cumulative count of insts written-back -system.cpu2.iew.WB:fanout 0.973959 # average fanout of values written-back +system.cpu2.iew.WB:consumers 95172 # num instructions consuming a value +system.cpu2.iew.WB:count 187212 # cumulative count of insts written-back +system.cpu2.iew.WB:fanout 0.972912 # average fanout of values written-back system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.iew.WB:producers 93988 # num instructions producing a value -system.cpu2.iew.WB:rate 0.430549 # insts written-back per cycle -system.cpu2.iew.WB:sent 190138 # cumulative count of insts sent to commit -system.cpu2.iew.branchMispredicts 43334 # Number of branch mispredicts detected at execute +system.cpu2.iew.WB:producers 92594 # num instructions producing a value +system.cpu2.iew.WB:rate 0.431358 # insts written-back per cycle +system.cpu2.iew.WB:sent 187507 # cumulative count of insts sent to commit +system.cpu2.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute system.cpu2.iew.iewBlockCycles 24 # Number of cycles IEW is blocking -system.cpu2.iew.iewDispLoadInsts 46475 # Number of dispatched load instructions -system.cpu2.iew.iewDispNonSpecInsts 21048 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewDispSquashedInsts 2818 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispStoreInsts 43788 # Number of dispatched store instructions -system.cpu2.iew.iewDispatchedInsts 321686 # Number of instructions dispatched to IQ -system.cpu2.iew.iewExecLoadInsts 45030 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 43684 # Number of squashed instructions skipped in execute -system.cpu2.iew.iewExecutedInsts 191426 # Number of executed instructions +system.cpu2.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions +system.cpu2.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions +system.cpu2.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ +system.cpu2.iew.iewExecLoadInsts 44335 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecutedInsts 188787 # Number of executed instructions system.cpu2.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.iewSquashCycles 44866 # Number of cycles IEW is squashing +system.cpu2.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing system.cpu2.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 19969 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 186 # Number of memory ordering violations +system.cpu2.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 3929 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 22009 # Number of stores squashed -system.cpu2.iew.memOrderViolationEvents 186 # Number of memory order violations -system.cpu2.iew.predictedNotTakenIncorrect 868 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.predictedTakenIncorrect 42466 # Number of branches that were predicted taken incorrectly -system.cpu2.ipc 0.269290 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.269290 # IPC: Total IPC of All Threads +system.cpu2.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed +system.cpu2.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed +system.cpu2.iew.memOrderViolationEvents 197 # Number of memory order violations +system.cpu2.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly +system.cpu2.ipc 0.269095 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.269095 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntAlu 166509 70.82% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemRead 45663 19.42% 90.24% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22938 9.76% 100.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::total 235110 # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued system.cpu2.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested -system.cpu2.iq.ISSUE:fu_busy_rate 0.000566 # FU busy rate (busy events/executed inst) +system.cpu2.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst) system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available @@ -952,576 +951,577 @@ system.cpu2.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # at system.cpu2.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:issued_per_cycle::samples 422806 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.556071 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.945329 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::0-1 286677 67.80% 67.80% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::1-2 67298 15.92% 83.72% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::2-3 43645 10.32% 94.04% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::3-4 22116 5.23% 99.27% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1740 0.41% 99.69% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::5-6 920 0.22% 99.90% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::6-7 282 0.07% 99.97% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::7-8 102 0.02% 99.99% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0-1 281858 67.78% 67.78% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1-2 66212 15.92% 83.70% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2-3 42876 10.31% 94.01% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3-4 21783 5.24% 99.25% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1770 0.43% 99.67% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::5-6 926 0.22% 99.90% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::6-7 279 0.07% 99.96% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::7-8 123 0.03% 99.99% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::total 422806 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:rate 0.533166 # Inst issue rate -system.cpu2.iq.iqInstsAdded 239551 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqInstsIssued 235110 # Number of instructions issued -system.cpu2.iq.iqNonSpecInstsAdded 21172 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqSquashedInstsExamined 99184 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedNonSpecRemoved 20613 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.iqSquashedOperandsExamined 15669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.memDep0.conflictingLoads 20136 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 109 # Number of conflicting stores. -system.cpu2.memDep0.insertedLoads 46475 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 43788 # Number of stores inserted to the mem dependence unit. -system.cpu2.numCycles 440970 # number of cpu cycles simulated +system.cpu2.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:rate 0.534016 # Inst issue rate +system.cpu2.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqInstsIssued 231766 # Number of instructions issued +system.cpu2.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.memDep0.conflictingLoads 19721 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 107 # Number of conflicting stores. +system.cpu2.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit. +system.cpu2.numCycles 434006 # number of cpu cycles simulated system.cpu2.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking -system.cpu2.rename.RENAME:CommittedMaps 97924 # Number of HB maps that are committed -system.cpu2.rename.RENAME:IdleCycles 188399 # Number of cycles rename is idle +system.cpu2.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed +system.cpu2.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle system.cpu2.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RENAME:RenameLookups 512581 # Number of register rename lookups that rename has made -system.cpu2.rename.RENAME:RenamedInsts 328892 # Number of instructions processed by rename -system.cpu2.rename.RENAME:RenamedOperands 245007 # Number of destination operands rename has renamed -system.cpu2.rename.RENAME:RunCycles 135302 # Number of cycles rename is running -system.cpu2.rename.RENAME:SquashCycles 44866 # Number of cycles rename is squashing -system.cpu2.rename.RENAME:UnblockCycles 350 # Number of cycles rename is unblocking -system.cpu2.rename.RENAME:UndoneMaps 147083 # Number of HB maps that are undone due to squashing -system.cpu2.rename.RENAME:serializeStallCycles 53857 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RENAME:serializingInsts 21162 # count of serializing insts renamed -system.cpu2.rename.RENAME:skidInsts 84753 # count of insts added to the skid buffer -system.cpu2.rename.RENAME:tempSerializingInsts 21158 # count of temporary serializing insts renamed +system.cpu2.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made +system.cpu2.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename +system.cpu2.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed +system.cpu2.rename.RENAME:RunCycles 133139 # Number of cycles rename is running +system.cpu2.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing +system.cpu2.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking +system.cpu2.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing +system.cpu2.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed +system.cpu2.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer +system.cpu2.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed system.cpu2.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.BTBHits 51243 # Number of BTB hits -system.cpu3.BPredUnit.BTBLookups 69683 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 53713 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 65870 # Number of BTB lookups system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu3.BPredUnit.condIncorrect 32692 # Number of conditional branches incorrect -system.cpu3.BPredUnit.condPredicted 78569 # Number of conditional branches predicted -system.cpu3.BPredUnit.lookups 78569 # Number of BP lookups +system.cpu3.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect +system.cpu3.BPredUnit.condPredicted 83669 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 83669 # Number of BP lookups system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu3.commit.COM:branches 25257 # Number of branches committed -system.cpu3.commit.COM:bw_lim_events 568 # number cycles where commit BW limit reached +system.cpu3.commit.COM:branches 25470 # Number of branches committed +system.cpu3.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.commit.COM:committed_per_cycle::samples 351415 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::mean 0.376558 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::stdev 0.826419 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::0-1 262526 74.71% 74.71% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::1-2 59947 17.06% 91.76% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::2-3 24097 6.86% 98.62% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::3-4 1297 0.37% 98.99% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::4-5 787 0.22% 99.21% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::5-6 568 0.16% 99.38% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::6-7 1611 0.46% 99.83% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::8 568 0.16% 100.00% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::0-1 266836 76.21% 76.21% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::1-2 54270 15.50% 91.71% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::2-3 24066 6.87% 98.58% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::3-4 1288 0.37% 98.95% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::4-5 810 0.23% 99.18% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::5-6 561 0.16% 99.34% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::6-7 1684 0.48% 99.82% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::7-8 40 0.01% 99.84% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::total 351415 # Number of insts commited each cycle -system.cpu3.commit.COM:count 132328 # Number of instructions committed -system.cpu3.commit.COM:loads 32245 # Number of loads committed -system.cpu3.commit.COM:membars 5830 # Number of memory barriers committed -system.cpu3.commit.COM:refs 45707 # Number of memory references committed +system.cpu3.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle +system.cpu3.commit.COM:count 127311 # Number of instructions committed +system.cpu3.commit.COM:loads 29520 # Number of loads committed +system.cpu3.commit.COM:membars 8970 # Number of memory barriers committed +system.cpu3.commit.COM:refs 40059 # Number of memory references committed system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.branchMispredicts 32692 # The number of times a branch was mispredicted -system.cpu3.commit.commitCommittedInsts 132328 # The number of committed instructions -system.cpu3.commit.commitNonSpecStalls 6543 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.commitSquashedInsts 149632 # The number of squashed insts skipped by commit -system.cpu3.committedInsts 110450 # Number of Instructions Simulated -system.cpu3.committedInsts_total 110450 # Number of Instructions Simulated -system.cpu3.cpi 3.645957 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 3.645957 # CPI: Total CPI of All Threads -system.cpu3.dcache.ReadReq_accesses 28797 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 19788.770053 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 16721.212121 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 28610 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 3700500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.006494 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 187 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_miss_latency 2759000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.005730 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 21918.181818 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22138.297872 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 1205500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.820896 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_hits 8 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_miss_latency 1040500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.701493 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_misses 47 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 13395 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 23007.751938 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14729.729730 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 13266 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 2968000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.009630 # miss rate for WriteReq accesses +system.cpu3.commit.branchMispredicts 29792 # The number of times a branch was mispredicted +system.cpu3.commit.commitCommittedInsts 127311 # The number of committed instructions +system.cpu3.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit +system.cpu3.committedInsts 102085 # Number of Instructions Simulated +system.cpu3.committedInsts_total 102085 # Number of Instructions Simulated +system.cpu3.cpi 3.876926 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 3.876926 # CPI: Total CPI of All Threads +system.cpu3.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 28662 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 204 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 10338 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 129 # number of WriteReq misses system.cpu3.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_miss_latency 1635000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008287 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 804.066667 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 701.333333 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 42192 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 21102.848101 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 41876 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 6668500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.007490 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 316 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 4394000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.006542 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 276 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_accesses 39333 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 39000 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 333 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.056978 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 29.172631 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 42192 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 21102.848101 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 39333 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 41876 # number of overall hits -system.cpu3.dcache.overall_miss_latency 6668500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.007490 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 316 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 40 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 4394000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.006542 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 276 # number of overall MSHR misses +system.cpu3.dcache.overall_hits 39000 # number of overall hits +system.cpu3.dcache.overall_miss_latency 6895500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 333 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 47 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 286 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 29.172631 # Cycle average of tags in use -system.cpu3.dcache.total_refs 24122 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 27.232391 # Cycle average of tags in use +system.cpu3.dcache.total_refs 21040 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.decode.DECODE:BlockedCycles 35128 # Number of cycles decode is blocked -system.cpu3.decode.DECODE:DecodedInsts 388171 # Number of instructions handled by decode -system.cpu3.decode.DECODE:IdleCycles 168108 # Number of cycles decode is idle -system.cpu3.decode.DECODE:RunCycles 148027 # Number of cycles decode is running -system.cpu3.decode.DECODE:SquashCycles 36551 # Number of cycles decode is squashing -system.cpu3.decode.DECODE:UnblockCycles 152 # Number of cycles decode is unblocking -system.cpu3.fetch.Branches 78569 # Number of branches that fetch encountered -system.cpu3.fetch.CacheLines 81998 # Number of cache lines fetched -system.cpu3.fetch.Cycles 239499 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.IcacheSquashes 12083 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.Insts 427102 # Number of instructions fetch has processed -system.cpu3.fetch.SquashCycles 32841 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.195107 # Number of branch fetches per cycle -system.cpu3.fetch.icacheStallCycles 81998 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.predictedBranches 51243 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.060607 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 397135 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.075458 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.013935 # Number of instructions fetched each cycle (Total) +system.cpu3.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked +system.cpu3.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode +system.cpu3.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle +system.cpu3.decode.DECODE:RunCycles 144955 # Number of cycles decode is running +system.cpu3.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing +system.cpu3.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking +system.cpu3.fetch.Branches 83669 # Number of branches that fetch encountered +system.cpu3.fetch.CacheLines 82467 # Number of cache lines fetched +system.cpu3.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.Insts 410532 # Number of instructions fetch has processed +system.cpu3.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing +system.cpu3.fetch.branchRate 0.211405 # Number of branch fetches per cycle +system.cpu3.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken +system.cpu3.fetch.rate 1.037284 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0-1 239656 60.35% 60.35% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1-2 85048 21.42% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2-3 14012 3.53% 85.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3-4 17951 4.52% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4-5 2990 0.75% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5-6 15291 3.85% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6-7 1676 0.42% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7-8 2382 0.60% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 18129 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0-1 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1-2 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2-3 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3-4 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4-5 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5-6 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6-7 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7-8 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 397135 # Number of instructions fetched each cycle (Total) -system.cpu3.icache.ReadReq_accesses 81998 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 19529.880478 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 16592.417062 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 81245 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 14706000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.009183 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 753 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_miss_latency 10503000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.007720 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 633 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu3.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total) +system.cpu3.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 81734 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 733 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 128.349131 # Average number of references to valid blocks. -system.cpu3.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu3.icache.avg_refs 128.512579 # Average number of references to valid blocks. +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 81998 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 19529.880478 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency -system.cpu3.icache.demand_hits 81245 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 14706000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.009183 # miss rate for demand accesses -system.cpu3.icache.demand_misses 753 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 10503000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.007720 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 633 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_accesses 82467 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency +system.cpu3.icache.demand_hits 81734 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.008888 # miss rate for demand accesses +system.cpu3.icache.demand_misses 733 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.192956 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 98.793514 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 81998 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 19529.880478 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.182938 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 93.664377 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 82467 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 81245 # number of overall hits -system.cpu3.icache.overall_miss_latency 14706000 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.009183 # miss rate for overall accesses -system.cpu3.icache.overall_misses 753 # number of overall misses -system.cpu3.icache.overall_mshr_hits 120 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 10503000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.007720 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 633 # number of overall MSHR misses +system.cpu3.icache.overall_hits 81734 # number of overall hits +system.cpu3.icache.overall_miss_latency 10621000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.008888 # miss rate for overall accesses +system.cpu3.icache.overall_misses 733 # number of overall misses +system.cpu3.icache.overall_mshr_hits 97 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 636 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 522 # number of replacements -system.cpu3.icache.sampled_refs 633 # Sample count of references to valid blocks. +system.cpu3.icache.replacements 524 # number of replacements +system.cpu3.icache.sampled_refs 636 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 98.793514 # Cycle average of tags in use -system.cpu3.icache.total_refs 81245 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 93.664377 # Cycle average of tags in use +system.cpu3.icache.total_refs 81734 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idleCycles 5561 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.iew.EXEC:branches 39289 # Number of branches executed -system.cpu3.iew.EXEC:nop 47300 # number of nop insts executed -system.cpu3.iew.EXEC:rate 0.440007 # Inst execution rate -system.cpu3.iew.EXEC:refs 53548 # number of memory reference insts executed -system.cpu3.iew.EXEC:stores 15235 # Number of stores executed +system.cpu3.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.iew.EXEC:branches 36547 # Number of branches executed +system.cpu3.iew.EXEC:nop 47873 # number of nop insts executed +system.cpu3.iew.EXEC:rate 0.410224 # Inst execution rate +system.cpu3.iew.EXEC:refs 47615 # number of memory reference insts executed +system.cpu3.iew.EXEC:stores 12164 # Number of stores executed system.cpu3.iew.EXEC:swp 0 # number of swp insts executed -system.cpu3.iew.WB:consumers 87751 # num instructions consuming a value -system.cpu3.iew.WB:count 173492 # cumulative count of insts written-back -system.cpu3.iew.WB:fanout 0.936696 # average fanout of values written-back +system.cpu3.iew.WB:consumers 78764 # num instructions consuming a value +system.cpu3.iew.WB:count 158732 # cumulative count of insts written-back +system.cpu3.iew.WB:fanout 0.929676 # average fanout of values written-back system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.iew.WB:producers 82196 # num instructions producing a value -system.cpu3.iew.WB:rate 0.430826 # insts written-back per cycle -system.cpu3.iew.WB:sent 173712 # cumulative count of insts sent to commit -system.cpu3.iew.branchMispredicts 33345 # Number of branch mispredicts detected at execute +system.cpu3.iew.WB:producers 73225 # num instructions producing a value +system.cpu3.iew.WB:rate 0.401065 # insts written-back per cycle +system.cpu3.iew.WB:sent 158983 # cumulative count of insts sent to commit +system.cpu3.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu3.iew.iewDispLoadInsts 42639 # Number of dispatched load instructions -system.cpu3.iew.iewDispNonSpecInsts 11434 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewDispSquashedInsts 4085 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispStoreInsts 26562 # Number of dispatched store instructions -system.cpu3.iew.iewDispatchedInsts 281979 # Number of instructions dispatched to IQ -system.cpu3.iew.iewExecLoadInsts 38313 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 36396 # Number of squashed instructions skipped in execute -system.cpu3.iew.iewExecutedInsts 177189 # Number of executed instructions +system.cpu3.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions +system.cpu3.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions +system.cpu3.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ +system.cpu3.iew.iewExecLoadInsts 35451 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 162357 # Number of executed instructions system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.iewSquashCycles 36551 # Number of cycles IEW is squashing +system.cpu3.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing system.cpu3.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 9499 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 639 # Number of memory ordering violations +system.cpu3.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 10394 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 13100 # Number of stores squashed -system.cpu3.iew.memOrderViolationEvents 639 # Number of memory order violations -system.cpu3.iew.predictedNotTakenIncorrect 830 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.predictedTakenIncorrect 32515 # Number of branches that were predicted taken incorrectly -system.cpu3.ipc 0.274276 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.274276 # IPC: Total IPC of All Threads +system.cpu3.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed +system.cpu3.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed +system.cpu3.iew.memOrderViolationEvents 694 # Number of memory order violations +system.cpu3.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly +system.cpu3.ipc 0.257936 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.257936 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntAlu 152352 71.33% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemRead 45332 21.22% 92.56% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemWrite 15901 7.44% 100.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::total 213585 # Type of FU issued -system.cpu3.iq.ISSUE:fu_busy_cnt 168 # FU busy when requested -system.cpu3.iq.ISSUE:fu_busy_rate 0.000787 # FU busy rate (busy events/executed inst) +system.cpu3.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued +system.cpu3.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested +system.cpu3.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst) system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntAlu 18 10.71% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemRead 11 6.55% 17.26% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemWrite 139 82.74% 100.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:issued_per_cycle::samples 397135 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.537815 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.988033 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::0-1 274584 69.14% 69.14% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::1-2 68377 17.22% 86.36% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::2-3 29162 7.34% 93.70% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::3-4 16815 4.23% 97.94% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5405 1.36% 99.30% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2141 0.54% 99.84% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::6-7 468 0.12% 99.95% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::7-8 158 0.04% 99.99% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::8 25 0.01% 100.00% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0-1 276221 70.31% 70.31% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1-2 71375 18.17% 88.48% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2-3 23368 5.95% 94.42% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3-4 13587 3.46% 97.88% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5437 1.38% 99.27% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2194 0.56% 99.83% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::6-7 490 0.12% 99.95% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::7-8 161 0.04% 99.99% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::total 397135 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:rate 0.530388 # Inst issue rate -system.cpu3.iq.iqInstsAdded 217367 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqInstsIssued 213585 # Number of instructions issued -system.cpu3.iq.iqNonSpecInstsAdded 17312 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqSquashedInstsExamined 84893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedNonSpecRemoved 10769 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.iqSquashedOperandsExamined 34030 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.memDep0.conflictingLoads 9667 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 80 # Number of conflicting stores. -system.cpu3.memDep0.insertedLoads 42639 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 26562 # Number of stores inserted to the mem dependence unit. -system.cpu3.numCycles 402696 # number of cpu cycles simulated -system.cpu3.rename.RENAME:CommittedMaps 93774 # Number of HB maps that are committed -system.cpu3.rename.RENAME:IdleCycles 183092 # Number of cycles rename is idle -system.cpu3.rename.RENAME:RenameLookups 489966 # Number of register rename lookups that rename has made -system.cpu3.rename.RENAME:RenamedInsts 307555 # Number of instructions processed by rename -system.cpu3.rename.RENAME:RenamedOperands 229124 # Number of destination operands rename has renamed -system.cpu3.rename.RENAME:RunCycles 133281 # Number of cycles rename is running -system.cpu3.rename.RENAME:SquashCycles 36551 # Number of cycles rename is squashing -system.cpu3.rename.RENAME:UnblockCycles 561 # Number of cycles rename is unblocking -system.cpu3.rename.RENAME:UndoneMaps 135350 # Number of HB maps that are undone due to squashing -system.cpu3.rename.RENAME:serializeStallCycles 34481 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RENAME:serializingInsts 11653 # count of serializing insts renamed -system.cpu3.rename.RENAME:skidInsts 44534 # count of insts added to the skid buffer -system.cpu3.rename.RENAME:tempSerializingInsts 11782 # count of temporary serializing insts renamed -system.cpu3.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) +system.cpu3.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:rate 0.495050 # Inst issue rate +system.cpu3.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqInstsIssued 195929 # Number of instructions issued +system.cpu3.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.memDep0.conflictingLoads 6760 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 87 # Number of conflicting stores. +system.cpu3.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit. +system.cpu3.numCycles 395776 # number of cpu cycles simulated +system.cpu3.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed +system.cpu3.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle +system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made +system.cpu3.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename +system.cpu3.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed +system.cpu3.rename.RENAME:RunCycles 133245 # Number of cycles rename is running +system.cpu3.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing +system.cpu3.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking +system.cpu3.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing +system.cpu3.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed +system.cpu3.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer +system.cpu3.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed +system.cpu3.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.l2c.ReadExReq_accesses::0 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 572875 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 572875 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 73132.978723 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 528807.692308 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1747690.671031 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40316.793893 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6874500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_miss_latency::0 528730.769231 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 572791.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 73122.340426 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 572791.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1747436.442990 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40312.977099 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 6873500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::0 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::2 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5281500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 10.916667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_latency 5281000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 10.076923 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 1.393617 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 10.076923 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 646 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 653 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::2 752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 647 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2699 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 4142500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 7249375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 63451.859956 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 325814.606742 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 11781141.466698 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39997.282609 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits::0 642 # number of ReadReq hits +system.l2c.ReadReq_accesses::3 650 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2701 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 362318.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 4830916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 63425.601751 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 2229653.846154 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 7486314.864571 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits::0 566 # number of ReadReq hits system.l2c.ReadReq_hits::1 647 # number of ReadReq hits system.l2c.ReadReq_hits::2 295 # number of ReadReq hits -system.l2c.ReadReq_hits::3 558 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2142 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 28997500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.010786 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006144 # miss rate for ReadReq accesses +system.l2c.ReadReq_hits::3 637 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 28985500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.123839 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.009188 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::2 0.607713 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.137558 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.762201 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 7 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::3 0.020000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.760740 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 80 # number of ReadReq misses +system.l2c.ReadReq_misses::1 6 # number of ReadReq misses system.l2c.ReadReq_misses::2 457 # number of ReadReq misses -system.l2c.ReadReq_misses::3 89 # number of ReadReq misses -system.l2c.ReadReq_misses::total 557 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 22078500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.850539 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.847926 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_misses::3 13 # number of ReadReq misses +system.l2c.ReadReq_misses::total 556 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 22080000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.854489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.845329 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 0.734043 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 0.853168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.285677 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 0.849231 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.283092 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 53 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::3 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 114 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 68894.736842 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::total 117 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 62333.333333 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 59500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 25173.076923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 24698.113208 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::3 62333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 215901.147099 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40039.473684 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 208864.779874 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40038.461538 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 52 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 53 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::3 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 114 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 4564500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 6 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 5.181818 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 2.192308 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 5.428571 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 18.802697 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 114 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::total 117 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4684500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 5.318182 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 2.207547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 18.668586 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 3.998131 # Average number of references to valid blocks. +system.l2c.avg_refs 4.003738 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 661 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 663 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 659 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 665 # number of demand (read+write) accesses system.l2c.demand_accesses::2 846 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 660 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2830 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 1888000 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 2242000 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 65103.448276 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 351686.274510 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 4546789.722786 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency -system.l2c.demand_hits::0 642 # number of demand (read+write) hits +system.l2c.demand_accesses::3 662 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2832 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 385580.645161 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1992166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 65079.854809 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3877187.166637 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency +system.l2c.demand_hits::0 566 # number of demand (read+write) hits system.l2c.demand_hits::1 647 # number of demand (read+write) hits system.l2c.demand_hits::2 295 # number of demand (read+write) hits -system.l2c.demand_hits::3 558 # number of demand (read+write) hits -system.l2c.demand_hits::total 2142 # number of demand (read+write) hits -system.l2c.demand_miss_latency 35872000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.028744 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.024133 # miss rate for demand accesses +system.l2c.demand_hits::3 637 # number of demand (read+write) hits +system.l2c.demand_hits::total 2145 # number of demand (read+write) hits +system.l2c.demand_miss_latency 35859000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.141123 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.027068 # miss rate for demand accesses system.l2c.demand_miss_rate::2 0.651300 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.154545 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.858723 # miss rate for demand accesses -system.l2c.demand_misses::0 19 # number of demand (read+write) misses -system.l2c.demand_misses::1 16 # number of demand (read+write) misses +system.l2c.demand_miss_rate::3 0.037764 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.857255 # miss rate for demand accesses +system.l2c.demand_misses::0 93 # number of demand (read+write) misses +system.l2c.demand_misses::1 18 # number of demand (read+write) misses system.l2c.demand_misses::2 551 # number of demand (read+write) misses -system.l2c.demand_misses::3 102 # number of demand (read+write) misses -system.l2c.demand_misses::total 688 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 27360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 1.033283 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.030166 # mshr miss rate for demand accesses +system.l2c.demand_misses::3 25 # number of demand (read+write) misses +system.l2c.demand_misses::total 687 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 27361000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 1.036419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.027068 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 0.807329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.034848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 3.905626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.031722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 3.902537 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.000042 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000041 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.005574 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.001194 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000088 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 2.720574 # Average occupied blocks per context -system.l2c.occ_blocks::1 2.658049 # Average occupied blocks per context -system.l2c.occ_blocks::2 365.307630 # Average occupied blocks per context -system.l2c.occ_blocks::3 78.263554 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.734616 # Average occupied blocks per context -system.l2c.overall_accesses::0 661 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 663 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.001067 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000056 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.005570 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000152 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 69.921003 # Average occupied blocks per context +system.l2c.occ_blocks::1 3.643564 # Average occupied blocks per context +system.l2c.occ_blocks::2 365.031703 # Average occupied blocks per context +system.l2c.occ_blocks::3 9.942146 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.939892 # Average occupied blocks per context +system.l2c.overall_accesses::0 659 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 665 # number of overall (read+write) accesses system.l2c.overall_accesses::2 846 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 660 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2830 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 1888000 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 2242000 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 65103.448276 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 351686.274510 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 4546789.722786 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency +system.l2c.overall_accesses::3 662 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2832 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 385580.645161 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1992166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 65079.854809 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3877187.166637 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 642 # number of overall hits +system.l2c.overall_hits::0 566 # number of overall hits system.l2c.overall_hits::1 647 # number of overall hits system.l2c.overall_hits::2 295 # number of overall hits -system.l2c.overall_hits::3 558 # number of overall hits -system.l2c.overall_hits::total 2142 # number of overall hits -system.l2c.overall_miss_latency 35872000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.028744 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.024133 # miss rate for overall accesses +system.l2c.overall_hits::3 637 # number of overall hits +system.l2c.overall_hits::total 2145 # number of overall hits +system.l2c.overall_miss_latency 35859000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.141123 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.027068 # miss rate for overall accesses system.l2c.overall_miss_rate::2 0.651300 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.154545 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.858723 # miss rate for overall accesses -system.l2c.overall_misses::0 19 # number of overall misses -system.l2c.overall_misses::1 16 # number of overall misses +system.l2c.overall_miss_rate::3 0.037764 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.857255 # miss rate for overall accesses +system.l2c.overall_misses::0 93 # number of overall misses +system.l2c.overall_misses::1 18 # number of overall misses system.l2c.overall_misses::2 551 # number of overall misses -system.l2c.overall_misses::3 102 # number of overall misses -system.l2c.overall_misses::total 688 # number of overall misses -system.l2c.overall_mshr_hits 5 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 27360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 1.033283 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.030166 # mshr miss rate for overall accesses +system.l2c.overall_misses::3 25 # number of overall misses +system.l2c.overall_misses::total 687 # number of overall misses +system.l2c.overall_mshr_hits 4 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 27361000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 1.036419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.027068 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 0.807329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.034848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 3.905626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.031722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 3.902537 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 683 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements system.l2c.sampled_refs 535 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 454.684423 # Cycle average of tags in use -system.l2c.total_refs 2139 # Total number of references to valid blocks. +system.l2c.tagsinuse 454.478308 # Cycle average of tags in use +system.l2c.total_refs 2142 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks |