diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/quick | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick')
168 files changed, 24127 insertions, 23700 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index fc8ce75af..b967ed849 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -118,6 +118,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer @@ -155,10 +156,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -172,6 +173,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -184,15 +186,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -404,9 +407,9 @@ timings=system.cpu.executeFuncUnits.funcUnits4.timings [system.cpu.executeFuncUnits.funcUnits4.opClasses] type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] type=MinorOpClass @@ -426,116 +429,126 @@ opClass=FloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] type=MinorOpClass eventq_index=0 -opClass=FloatMult +opClass=FloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] type=MinorOpClass eventq_index=0 -opClass=FloatDiv +opClass=FloatMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] type=MinorOpClass eventq_index=0 -opClass=FloatSqrt +opClass=FloatMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] type=MinorOpClass eventq_index=0 -opClass=SimdAdd +opClass=FloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] type=MinorOpClass eventq_index=0 -opClass=SimdAddAcc +opClass=FloatSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] type=MinorOpClass eventq_index=0 -opClass=SimdAlu +opClass=SimdAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] type=MinorOpClass eventq_index=0 -opClass=SimdCmp +opClass=SimdAddAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] type=MinorOpClass eventq_index=0 -opClass=SimdCvt +opClass=SimdAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] type=MinorOpClass eventq_index=0 -opClass=SimdMisc +opClass=SimdCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] type=MinorOpClass eventq_index=0 -opClass=SimdMult +opClass=SimdCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] type=MinorOpClass eventq_index=0 -opClass=SimdMultAcc +opClass=SimdMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] type=MinorOpClass eventq_index=0 -opClass=SimdShift +opClass=SimdMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] type=MinorOpClass eventq_index=0 -opClass=SimdShiftAcc +opClass=SimdMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] type=MinorOpClass eventq_index=0 -opClass=SimdSqrt +opClass=SimdShift [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAdd +opClass=SimdShiftAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAlu +opClass=SimdSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCmp +opClass=SimdFloatAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCvt +opClass=SimdFloatAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] type=MinorOpClass eventq_index=0 -opClass=SimdFloatDiv +opClass=SimdFloatCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMisc +opClass=SimdFloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMult +opClass=SimdFloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMultAcc +opClass=SimdFloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] type=MinorOpClass eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 opClass=SimdFloatSqrt [system.cpu.executeFuncUnits.funcUnits4.timings] @@ -569,9 +582,9 @@ timings=system.cpu.executeFuncUnits.funcUnits5.timings [system.cpu.executeFuncUnits.funcUnits5.opClasses] type=MinorOpClassSet -children=opClasses0 opClasses1 +children=opClasses0 opClasses1 opClasses2 opClasses3 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] type=MinorOpClass @@ -583,6 +596,16 @@ type=MinorOpClass eventq_index=0 opClass=MemWrite +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + [system.cpu.executeFuncUnits.funcUnits5.timings] type=MinorFUTiming children=opClasses @@ -635,10 +658,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -652,6 +675,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -664,15 +688,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -691,8 +716,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -703,8 +726,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -767,10 +788,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -784,6 +805,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -796,15 +818,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -840,7 +863,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -849,14 +872,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout index 6a285f351..0722728b6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:42:59 -gem5 executing on e108600-lin, pid 17319 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54225 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 32719500 because target called exit() +Exiting @ tick 32617500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 218cf1458..4b0e86c1b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,878 +1,878 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32617500 # Number of ticks simulated -final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159604 # Simulator instruction rate (inst/s) -host_op_rate 186772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1129633158 # Simulator tick rate (ticks/s) -host_mem_usage 268376 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 4605 # Number of instructions simulated -sim_ops 5391 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory -system.physmem.bytes_read::total 26880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 420 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 420 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 91 # Per bank write bursts -system.physmem.perBankRdBursts::1 52 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 21 # Per bank write bursts -system.physmem.perBankRdBursts::5 41 # Per bank write bursts -system.physmem.perBankRdBursts::6 36 # Per bank write bursts -system.physmem.perBankRdBursts::7 12 # Per bank write bursts -system.physmem.perBankRdBursts::8 5 # Per bank write bursts -system.physmem.perBankRdBursts::9 6 # Per bank write bursts -system.physmem.perBankRdBursts::10 27 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 9 # Per bank write bursts -system.physmem.perBankRdBursts::13 8 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32519500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 420 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 5148000 # Total ticks spent queuing -system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.44 # Data bus utilization in percentage -system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 346 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 77427.38 # Average gap between requests -system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ) -system.physmem_0.averagePower 616.275926 # Core power per rank (mW) -system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states -system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ) -system.physmem_1.averagePower 557.213152 # Core power per rank (mW) -system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1965 # Number of BP lookups -system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups -system.cpu.branchPred.BTBHits 324 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 129 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 65235 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4605 # Number of instructions committed -system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.166124 # CPI: cycles per instruction -system.cpu.ipc 0.070591 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction -system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction -system.cpu.op_class_0::MemWrite 922 17.10% 99.70% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 176 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses -system.cpu.dcache.overall_misses::total 176 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7434500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7434500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5464500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5464500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12899000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12899000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12899000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12899000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2072 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2072 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2072 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2072 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.094047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68206.422018 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68206.422018 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81559.701493 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81559.701493 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73289.772727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73289.772727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3488000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3488000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10549000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10549000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10549000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10549000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68553.398058 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68553.398058 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81116.279070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81116.279070 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4895 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits -system.cpu.icache.overall_hits::total 1966 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses -system.cpu.icache.overall_misses::total 321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4 # number of writebacks -system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses -system.cpu.l2cache.overall_misses::total 428 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 377 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 420 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 420 # Request fanout histogram -system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) 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+system.cpu.toL2Bus.trans_dist::ReadExReq 43 +system.cpu.toL2Bus.trans_dist::ReadExResp 43 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 +system.cpu.toL2Bus.pkt_count::total 938 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 +system.cpu.toL2Bus.pkt_size::total 30144 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 467 +system.cpu.toL2Bus.snoop_fanout::mean 0.100642 +system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% +system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 467 +system.cpu.toL2Bus.reqLayer0.occupancy 239500 +system.cpu.toL2Bus.reqLayer0.utilization 0.7 +system.cpu.toL2Bus.respLayer0.occupancy 481500 +system.cpu.toL2Bus.respLayer0.utilization 1.5 +system.cpu.toL2Bus.respLayer1.occupancy 222992 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 420 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 +system.membus.trans_dist::ReadResp 377 +system.membus.trans_dist::ReadExReq 43 +system.membus.trans_dist::ReadExResp 43 +system.membus.trans_dist::ReadSharedReq 377 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 +system.membus.pkt_count::total 840 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 +system.membus.pkt_size::total 26880 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 420 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 420 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 420 +system.membus.reqLayer0.occupancy 489000 +system.membus.reqLayer0.utilization 1.5 +system.membus.respLayer1.occupancy 2233000 +system.membus.respLayer1.utilization 6.8 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index ff436d924..64046a027 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=system.cpu.checker clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -206,6 +207,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.checker.tracer updateOnError=true @@ -276,8 +278,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -288,8 +288,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -356,10 +354,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -373,6 +371,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -385,15 +384,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -517,10 +517,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -532,11 +532,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -545,18 +559,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -706,24 +727,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -739,6 +767,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -760,10 +802,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -777,6 +819,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -789,15 +832,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -816,8 +860,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -828,8 +870,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -892,10 +932,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -909,6 +949,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -921,15 +962,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -965,7 +1007,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -974,14 +1016,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr index 57447a9b7..1f8287d96 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr @@ -2,3 +2,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index e9b447feb..122f716a7 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:42:58 -gem5 executing on e108600-lin, pid 17311 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:05:15 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55322 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 18422500 because target called exit() +Exiting @ tick 18517500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index b3c6058a4..306010dfa 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,1273 +1,1273 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18517500 # Number of ticks simulated -final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74881 # Simulator instruction rate (inst/s) -host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 301872470 # Simulator tick rate (ticks/s) -host_mem_usage 270416 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 396 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 89 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 35 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 10 # Per bank write bursts -system.physmem.perBankRdBursts::13 6 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18432000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 396 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 5212000 # Total ticks spent queuing -system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.69 # Data bus utilization in percentage -system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 329 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46545.45 # Average gap between requests -system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) -system.physmem_0.averagePower 659.559336 # Core power per rank (mW) -system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states -system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) -system.physmem_1.averagePower 567.626569 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2820 # Number of BP lookups -system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups -system.cpu.branchPred.BTBHits 844 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 5391 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 37036 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2138 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 40 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8207 # Type of FU issued -system.cpu.iq.rate 0.221595 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3007 # number of memory reference insts executed -system.cpu.iew.exec_branches 1490 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.212901 # Inst execution rate -system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7470 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3518 # num instructions producing a value -system.cpu.iew.wb_consumers 6872 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4592 # Number of instructions committed -system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1965 # Number of memory references committed -system.cpu.commit.loads 1027 # Number of loads committed -system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1008 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4624 # Number of committed integer instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22825 # The number of ROB reads -system.cpu.rob.rob_writes 21580 # The number of ROB writes -system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4592 # Number of Instructions Simulated -system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads -system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7779 # number of integer regfile reads -system.cpu.int_regfile_writes 4297 # number of integer regfile writes -system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28140 # number of cc regfile reads -system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 3029 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits -system.cpu.dcache.overall_hits::total 2137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses 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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags 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(read+write) misses -system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses -system.cpu.icache.overall_misses::total 395 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks 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misses -system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23439000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23439000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 213.492112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.098485 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.462705 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 74.029407 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006515 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3924 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3924 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 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-system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 354 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.3 # Layer utilization (%) +sim_seconds 0.000019 +sim_ticks 18517500 +final_tick 18517500 +sim_freq 1000000000000 +host_inst_rate 45460 +host_op_rate 53229 +host_tick_rate 183240261 +host_mem_usage 280812 +host_seconds 0.10 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 +system.physmem.bytes_read::cpu.inst 17600 +system.physmem.bytes_read::cpu.data 7744 +system.physmem.bytes_read::total 25344 +system.physmem.bytes_inst_read::cpu.inst 17600 +system.physmem.bytes_inst_read::total 17600 +system.physmem.num_reads::cpu.inst 275 +system.physmem.num_reads::cpu.data 121 +system.physmem.num_reads::total 396 +system.physmem.bw_read::cpu.inst 950452275 +system.physmem.bw_read::cpu.data 418199001 +system.physmem.bw_read::total 1368651276 +system.physmem.bw_inst_read::cpu.inst 950452275 +system.physmem.bw_inst_read::total 950452275 +system.physmem.bw_total::cpu.inst 950452275 +system.physmem.bw_total::cpu.data 418199001 +system.physmem.bw_total::total 1368651276 +system.physmem.readReqs 396 +system.physmem.writeReqs 0 +system.physmem.readBursts 396 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 25344 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 25344 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 89 +system.physmem.perBankRdBursts::1 45 +system.physmem.perBankRdBursts::2 20 +system.physmem.perBankRdBursts::3 43 +system.physmem.perBankRdBursts::4 18 +system.physmem.perBankRdBursts::5 32 +system.physmem.perBankRdBursts::6 35 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 4 +system.physmem.perBankRdBursts::9 8 +system.physmem.perBankRdBursts::10 28 +system.physmem.perBankRdBursts::11 42 +system.physmem.perBankRdBursts::12 10 +system.physmem.perBankRdBursts::13 6 +system.physmem.perBankRdBursts::14 0 +system.physmem.perBankRdBursts::15 6 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 18432000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 396 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 204 +system.physmem.rdQLenPdf::1 121 +system.physmem.rdQLenPdf::2 52 +system.physmem.rdQLenPdf::3 14 +system.physmem.rdQLenPdf::4 4 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 59 +system.physmem.bytesPerActivate::mean 406.779661 +system.physmem.bytesPerActivate::gmean 269.610222 +system.physmem.bytesPerActivate::stdev 346.645206 +system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% +system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% +system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% +system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% +system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% +system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% 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0.00% +system.membus.snoop_fanout::0 396 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 396 +system.membus.reqLayer0.occupancy 484000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2091500 +system.membus.respLayer1.utilization 11.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 3cdf3afd3..72771fa1e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -626,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -638,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -807,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -816,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index d64ac9ed3..9ae67891c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 19:03:48 -gem5 started Nov 29 2016 19:06:55 -gem5 executing on zizzer, pid 5766 -command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:08:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55753 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 20302000 because target called exit() +Exiting @ tick 20302000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6ea38295f..f88830f40 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,1179 +1,1179 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20302000 # Number of ticks simulated -final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93691 # Simulator instruction rate (inst/s) -host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 414022055 # Simulator tick rate (ticks/s) -host_mem_usage 265936 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 914195646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 400354645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1399665058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 914195646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 914195646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 914195646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 400354645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1399665058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 103 # Per bank write bursts -system.physmem.perBankRdBursts::1 48 # Per bank write bursts -system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 45 # Per bank write bursts -system.physmem.perBankRdBursts::4 19 # Per bank write bursts -system.physmem.perBankRdBursts::5 37 # Per bank write bursts -system.physmem.perBankRdBursts::6 46 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 27 # Per bank write bursts -system.physmem.perBankRdBursts::11 47 # Per bank write bursts -system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 8 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20260500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 295.844737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.802892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6135000 # Total ticks spent queuing -system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.96 # Data bus utilization in percentage -system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 373 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45529.21 # Average gap between requests -system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) -system.physmem_0.averagePower 656.916882 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states -system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) -system.physmem_1.averagePower 566.475803 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16880000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 620500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2792000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups -system.cpu.branchPred.BTBHits 446 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40605 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5171 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4182 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7227 # Type of FU issued -system.cpu.iq.rate 0.177983 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2443 # number of memory reference insts executed -system.cpu.iew.exec_branches 1299 # Number of branches executed -system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.168033 # Inst execution rate -system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6639 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2983 # num instructions producing a value -system.cpu.iew.wb_consumers 5430 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4592 # Number of instructions committed -system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1965 # Number of memory references committed -system.cpu.commit.loads 1027 # Number of loads committed -system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1008 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4624 # Number of committed integer instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23224 # The number of ROB reads -system.cpu.rob.rob_writes 16731 # The number of ROB writes -system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4592 # Number of Instructions Simulated -system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads -system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6850 # number of integer regfile reads -system.cpu.int_regfile_writes 3795 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24229 # number of cc regfile reads -system.cpu.cc_regfile_writes 2927 # number of cc regfile writes -system.cpu.misc_regfile_reads 2559 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits -system.cpu.dcache.overall_hits::total 1903 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses -system.cpu.dcache.overall_misses::total 361 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2264 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # 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3532 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits -system.cpu.icache.overall_hits::total 3532 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for 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cycles access was blocked -system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 44 # number of writebacks -system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000793 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001709 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7676 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7676 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 11 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 19 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 11 # number of overall hits -system.cpu.l2cache.overall_hits::total 19 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 291 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 291 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 103 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 103 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 133 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 424 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 133 # number of overall misses -system.cpu.l2cache.overall_misses::total 424 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.923611 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.957111 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 98 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 98 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 128 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 69 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 512 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.134766 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 414 # Transaction distribution -system.membus.trans_dist::ReadExReq 30 # Transaction distribution -system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 445 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 445 # Request fanout histogram -system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +sim_seconds 0.000020 +sim_ticks 20302000 +final_tick 20302000 +sim_freq 1000000000000 +host_inst_rate 45535 +host_op_rate 53318 +host_tick_rate 201173118 +host_mem_usage 277864 +host_seconds 0.10 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 +system.physmem.bytes_read::cpu.inst 18560 +system.physmem.bytes_read::cpu.data 8128 +system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 +system.physmem.bytes_read::total 28416 +system.physmem.bytes_inst_read::cpu.inst 18560 +system.physmem.bytes_inst_read::total 18560 +system.physmem.num_reads::cpu.inst 290 +system.physmem.num_reads::cpu.data 127 +system.physmem.num_reads::cpu.l2cache.prefetcher 27 +system.physmem.num_reads::total 444 +system.physmem.bw_read::cpu.inst 914195646 +system.physmem.bw_read::cpu.data 400354645 +system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 +system.physmem.bw_read::total 1399665058 +system.physmem.bw_inst_read::cpu.inst 914195646 +system.physmem.bw_inst_read::total 914195646 +system.physmem.bw_total::cpu.inst 914195646 +system.physmem.bw_total::cpu.data 400354645 +system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 +system.physmem.bw_total::total 1399665058 +system.physmem.readReqs 445 +system.physmem.writeReqs 0 +system.physmem.readBursts 445 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 28480 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 28480 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 103 +system.physmem.perBankRdBursts::1 48 +system.physmem.perBankRdBursts::2 19 +system.physmem.perBankRdBursts::3 45 +system.physmem.perBankRdBursts::4 19 +system.physmem.perBankRdBursts::5 37 +system.physmem.perBankRdBursts::6 46 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 4 +system.physmem.perBankRdBursts::9 8 +system.physmem.perBankRdBursts::10 27 +system.physmem.perBankRdBursts::11 47 +system.physmem.perBankRdBursts::12 17 +system.physmem.perBankRdBursts::13 8 +system.physmem.perBankRdBursts::14 0 +system.physmem.perBankRdBursts::15 7 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 20260500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 445 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 241 +system.physmem.rdQLenPdf::1 136 +system.physmem.rdQLenPdf::2 36 +system.physmem.rdQLenPdf::3 17 +system.physmem.rdQLenPdf::4 5 +system.physmem.rdQLenPdf::5 2 +system.physmem.rdQLenPdf::6 2 +system.physmem.rdQLenPdf::7 2 +system.physmem.rdQLenPdf::8 2 +system.physmem.rdQLenPdf::9 2 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 62 +system.physmem.bytesPerActivate::mean 435.612903 +system.physmem.bytesPerActivate::gmean 295.844737 +system.physmem.bytesPerActivate::stdev 352.802892 +system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% 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+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 +system.cpu.toL2Bus.pkt_count::total 930 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 +system.cpu.toL2Bus.pkt_size::total 31168 +system.cpu.toL2Bus.snoops 69 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 512 +system.cpu.toL2Bus.snoop_fanout::mean 0.134766 +system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% +system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% +system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 512 +system.cpu.toL2Bus.reqLayer0.occupancy 289000 +system.cpu.toL2Bus.reqLayer0.utilization 1.4 +system.cpu.toL2Bus.respLayer0.occupancy 448999 +system.cpu.toL2Bus.respLayer0.utilization 2.2 +system.cpu.toL2Bus.respLayer1.occupancy 216995 +system.cpu.toL2Bus.respLayer1.utilization 1.1 +system.membus.snoop_filter.tot_requests 445 +system.membus.snoop_filter.hit_single_requests 35 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 +system.membus.trans_dist::ReadResp 414 +system.membus.trans_dist::ReadExReq 30 +system.membus.trans_dist::ReadExResp 30 +system.membus.trans_dist::ReadSharedReq 415 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 +system.membus.pkt_count::total 889 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 +system.membus.pkt_size::total 28416 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 445 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 445 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 445 +system.membus.reqLayer0.occupancy 554444 +system.membus.reqLayer0.utilization 2.7 +system.membus.respLayer1.occupancy 2338250 +system.membus.respLayer1.utilization 11.5 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index be532b0c0..3b9285ab6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -131,6 +132,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.checker.tracer updateOnError=false @@ -200,8 +202,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -212,8 +212,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -340,8 +338,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -352,8 +348,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -414,7 +408,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -423,14 +417,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -454,6 +449,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -465,7 +461,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -473,6 +469,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -481,6 +484,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -488,7 +492,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr index 2b0e974b5..d46032821 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a4f08df89..6f0847911 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:49:47 -gem5 executing on e108600-lin, pid 23301 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54232 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2695000 because target called exit() +Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index cf15c6ad1..d2c8b968b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,384 +1,384 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2695000 # Number of ticks simulated -final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 707147 # Simulator instruction rate (inst/s) -host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 413753949 # Simulator tick rate (ticks/s) -host_mem_usage 259056 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22911 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory -system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 0 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5391 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4592 # Number of instructions committed -system.cpu.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7572 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5597 # Transaction distribution -system.membus.trans_dist::ReadResp 5608 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6532 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2695000 +final_tick 2695000 +sim_freq 1000000000000 +host_inst_rate 413531 +host_op_rate 483368 +host_tick_rate 241807981 +host_mem_usage 270560 +host_seconds 0.01 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 +system.physmem.bytes_read::cpu.inst 18420 +system.physmem.bytes_read::cpu.data 4491 +system.physmem.bytes_read::total 22911 +system.physmem.bytes_inst_read::cpu.inst 18420 +system.physmem.bytes_inst_read::total 18420 +system.physmem.bytes_written::cpu.data 3648 +system.physmem.bytes_written::total 3648 +system.physmem.num_reads::cpu.inst 4605 +system.physmem.num_reads::cpu.data 1003 +system.physmem.num_reads::total 5608 +system.physmem.num_writes::cpu.data 924 +system.physmem.num_writes::total 924 +system.physmem.bw_read::cpu.inst 6834879406 +system.physmem.bw_read::cpu.data 1666419295 +system.physmem.bw_read::total 8501298701 +system.physmem.bw_inst_read::cpu.inst 6834879406 +system.physmem.bw_inst_read::total 6834879406 +system.physmem.bw_write::cpu.data 1353617811 +system.physmem.bw_write::total 1353617811 +system.physmem.bw_total::cpu.inst 6834879406 +system.physmem.bw_total::cpu.data 3020037106 +system.physmem.bw_total::total 9854916512 +system.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu_clk_domain.clock 500 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 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+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.pwrStateResidencyTicks::ON 2695000 +system.cpu.numCycles 5391 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4592 +system.cpu.committedOps 5378 +system.cpu.num_int_alu_accesses 4624 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 203 +system.cpu.num_conditional_control_insts 722 +system.cpu.num_int_insts 4624 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 7572 +system.cpu.num_int_register_writes 2728 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 16175 +system.cpu.num_cc_register_writes 2432 +system.cpu.num_mem_refs 1965 +system.cpu.num_load_insts 1027 +system.cpu.num_store_insts 938 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5391 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1008 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3419 63.42% 63.42% +system.cpu.op_class::IntMult 4 0.07% 63.49% +system.cpu.op_class::IntDiv 0 0.00% 63.49% +system.cpu.op_class::FloatAdd 0 0.00% 63.49% +system.cpu.op_class::FloatCmp 0 0.00% 63.49% +system.cpu.op_class::FloatCvt 0 0.00% 63.49% +system.cpu.op_class::FloatMult 0 0.00% 63.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% +system.cpu.op_class::FloatDiv 0 0.00% 63.49% +system.cpu.op_class::FloatMisc 0 0.00% 63.49% +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdAdd 0 0.00% 63.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% +system.cpu.op_class::SimdAlu 0 0.00% 63.49% +system.cpu.op_class::SimdCmp 0 0.00% 63.49% +system.cpu.op_class::SimdCvt 0 0.00% 63.49% +system.cpu.op_class::SimdMisc 0 0.00% 63.49% +system.cpu.op_class::SimdMult 0 0.00% 63.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% +system.cpu.op_class::SimdShift 0 0.00% 63.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% +system.cpu.op_class::MemRead 1027 19.05% 82.60% +system.cpu.op_class::MemWrite 922 17.10% 99.70% +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5391 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 +system.membus.trans_dist::ReadReq 5597 +system.membus.trans_dist::ReadResp 5608 +system.membus.trans_dist::WriteReq 913 +system.membus.trans_dist::WriteResp 913 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 +system.membus.pkt_count::total 13064 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 +system.membus.pkt_size::total 26559 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6532 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6532 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6532 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 8f8064fa0..c1120b4bf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 813c1fdca..ffacc8975 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23087 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:58:26 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54584 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2695000 because target called exit() +Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 18ea66efd..9a08bb729 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,260 +1,260 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2695000 # Number of ticks simulated -final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 709054 # Simulator instruction rate (inst/s) -host_op_rate 829008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 414799236 # Simulator tick rate (ticks/s) -host_mem_usage 257780 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22911 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory -system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5391 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4592 # Number of instructions committed -system.cpu.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7572 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5597 # Transaction distribution -system.membus.trans_dist::ReadResp 5608 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6532 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2695000 +final_tick 2695000 +sim_freq 1000000000000 +host_inst_rate 427927 +host_op_rate 500175 +host_tick_rate 250203319 +host_mem_usage 269284 +host_seconds 0.01 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 +system.physmem.bytes_read::cpu.inst 18420 +system.physmem.bytes_read::cpu.data 4491 +system.physmem.bytes_read::total 22911 +system.physmem.bytes_inst_read::cpu.inst 18420 +system.physmem.bytes_inst_read::total 18420 +system.physmem.bytes_written::cpu.data 3648 +system.physmem.bytes_written::total 3648 +system.physmem.num_reads::cpu.inst 4605 +system.physmem.num_reads::cpu.data 1003 +system.physmem.num_reads::total 5608 +system.physmem.num_writes::cpu.data 924 +system.physmem.num_writes::total 924 +system.physmem.bw_read::cpu.inst 6834879406 +system.physmem.bw_read::cpu.data 1666419295 +system.physmem.bw_read::total 8501298701 +system.physmem.bw_inst_read::cpu.inst 6834879406 +system.physmem.bw_inst_read::total 6834879406 +system.physmem.bw_write::cpu.data 1353617811 +system.physmem.bw_write::total 1353617811 +system.physmem.bw_total::cpu.inst 6834879406 +system.physmem.bw_total::cpu.data 3020037106 +system.physmem.bw_total::total 9854916512 +system.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 13 +system.cpu.pwrStateResidencyTicks::ON 2695000 +system.cpu.numCycles 5391 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4592 +system.cpu.committedOps 5378 +system.cpu.num_int_alu_accesses 4624 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 203 +system.cpu.num_conditional_control_insts 722 +system.cpu.num_int_insts 4624 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 7572 +system.cpu.num_int_register_writes 2728 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 16175 +system.cpu.num_cc_register_writes 2432 +system.cpu.num_mem_refs 1965 +system.cpu.num_load_insts 1027 +system.cpu.num_store_insts 938 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5391 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1008 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3419 63.42% 63.42% +system.cpu.op_class::IntMult 4 0.07% 63.49% +system.cpu.op_class::IntDiv 0 0.00% 63.49% +system.cpu.op_class::FloatAdd 0 0.00% 63.49% +system.cpu.op_class::FloatCmp 0 0.00% 63.49% +system.cpu.op_class::FloatCvt 0 0.00% 63.49% +system.cpu.op_class::FloatMult 0 0.00% 63.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% +system.cpu.op_class::FloatDiv 0 0.00% 63.49% +system.cpu.op_class::FloatMisc 0 0.00% 63.49% +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdAdd 0 0.00% 63.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% +system.cpu.op_class::SimdAlu 0 0.00% 63.49% +system.cpu.op_class::SimdCmp 0 0.00% 63.49% +system.cpu.op_class::SimdCvt 0 0.00% 63.49% +system.cpu.op_class::SimdMisc 0 0.00% 63.49% +system.cpu.op_class::SimdMult 0 0.00% 63.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% +system.cpu.op_class::SimdShift 0 0.00% 63.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% +system.cpu.op_class::MemRead 1027 19.05% 82.60% +system.cpu.op_class::MemWrite 922 17.10% 99.70% +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5391 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 +system.membus.trans_dist::ReadReq 5597 +system.membus.trans_dist::ReadResp 5608 +system.membus.trans_dist::WriteReq 913 +system.membus.trans_dist::WriteResp 913 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 +system.membus.pkt_count::total 13064 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 +system.membus.pkt_size::total 26559 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6532 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6532 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6532 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index b1081da03..4f88d60dc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 4f7f76cdc..b914fe569 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23085 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:13:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56989 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 28298500 because target called exit() +Exiting @ tick 28648500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 3c58db434..76c17a485 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,630 +1,630 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28648500 # Number of ticks simulated -final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 484095 # Simulator instruction rate (inst/s) -host_op_rate 564461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3030833923 # Simulator tick rate (ticks/s) -host_mem_usage 267516 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4566 # Number of instructions simulated -sim_ops 5330 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 22400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 57297 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4566 # Number of instructions committed -system.cpu.committedOps 5330 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7538 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits -system.cpu.dcache.overall_hits::total 1764 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits -system.cpu.icache.overall_hits::total 4365 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses -system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits -system.cpu.l2cache.overall_hits::total 32 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses -system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 307 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 350 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.1 # Layer utilization (%) +sim_seconds 0.000029 +sim_ticks 28648500 +final_tick 28648500 +sim_freq 1000000000000 +host_inst_rate 277751 +host_op_rate 323869 +host_tick_rate 1739012040 +host_mem_usage 279272 +host_seconds 0.02 +sim_insts 4566 +sim_ops 5330 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 +system.physmem.bytes_read::cpu.inst 14400 +system.physmem.bytes_read::cpu.data 8000 +system.physmem.bytes_read::total 22400 +system.physmem.bytes_inst_read::cpu.inst 14400 +system.physmem.bytes_inst_read::total 14400 +system.physmem.num_reads::cpu.inst 225 +system.physmem.num_reads::cpu.data 125 +system.physmem.num_reads::total 350 +system.physmem.bw_read::cpu.inst 502644117 +system.physmem.bw_read::cpu.data 279246732 +system.physmem.bw_read::total 781890849 +system.physmem.bw_inst_read::cpu.inst 502644117 +system.physmem.bw_inst_read::total 502644117 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+system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 +system.cpu.toL2Bus.trans_dist::ReadResp 339 +system.cpu.toL2Bus.trans_dist::WritebackClean 1 +system.cpu.toL2Bus.trans_dist::ReadExReq 43 +system.cpu.toL2Bus.trans_dist::ReadExResp 43 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 +system.cpu.toL2Bus.pkt_count::total 765 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 +system.cpu.toL2Bus.pkt_size::total 24512 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 382 +system.cpu.toL2Bus.snoop_fanout::mean 0.083770 +system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% +system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 382 +system.cpu.toL2Bus.reqLayer0.occupancy 192500 +system.cpu.toL2Bus.reqLayer0.utilization 0.7 +system.cpu.toL2Bus.respLayer0.occupancy 361500 +system.cpu.toL2Bus.respLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer1.occupancy 211500 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 350 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 +system.membus.trans_dist::ReadResp 307 +system.membus.trans_dist::ReadExReq 43 +system.membus.trans_dist::ReadExResp 43 +system.membus.trans_dist::ReadSharedReq 307 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 +system.membus.pkt_count::total 700 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 +system.membus.pkt_size::total 22400 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 350 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 350 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 350 +system.membus.reqLayer0.occupancy 355500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 1750000 +system.membus.respLayer1.utilization 6.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 70198a6d7..c234169e9 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -66,7 +66,7 @@ UnifiedTLB=true activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -140,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -716,7 +717,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -725,14 +726,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 5b262649f..a796e3972 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:37:43 -gem5 started Nov 29 2016 18:37:59 -gem5 executing on zizzer, pid 53433 -command line: /z/powerjg/gem5-upstream/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing +gem5 compiled Apr 3 2017 19:22:30 +gem5 started Apr 3 2017 19:22:48 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 103796 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 21268000 because target called exit() +Exiting @ tick 21189000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 804710aed..189de9f2f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,1012 +1,1012 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21189000 # Number of ticks simulated -final_tick 21189000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143245 # Simulator instruction rate (inst/s) -host_op_rate 143198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 523712790 # Simulator tick rate (ticks/s) -host_mem_usage 249592 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 5792 # Number of instructions simulated -sim_ops 5792 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1029968380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308084383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1338052763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1029968380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308084383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1338052763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 444 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71 # Per bank write bursts -system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 55 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 53 # Per bank write bursts -system.physmem.perBankRdBursts::5 61 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 9 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 1 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 0 # Per bank write bursts -system.physmem.perBankRdBursts::13 0 # Per bank write bursts -system.physmem.perBankRdBursts::14 4 # Per bank write bursts -system.physmem.perBankRdBursts::15 0 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21128500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 444 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.631579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.894378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.912685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 5920000 # Total ticks spent queuing -system.physmem.totMemAccLat 14245000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13333.33 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32083.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1341.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1341.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.48 # Data bus utilization in percentage -system.physmem.busUtilRead 10.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 358 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47586.71 # Average gap between requests -system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2870280 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3925590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5657820 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 38400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14532315 # Total energy per rank (pJ) -system.physmem_0.averagePower 685.810052 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12505250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 100250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8146250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12405000 # Time in different power states -system.physmem_1.actEnergy 85680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 34155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 759810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1412160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6380010 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10913295 # Total energy per rank (pJ) -system.physmem_1.averagePower 515.021000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 13660000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3594000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1229000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13991250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2458 # Number of BP lookups -system.cpu.branchPred.condPredicted 2033 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2104 # Number of BTB lookups -system.cpu.branchPred.BTBHits 724 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.410646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 228 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 36 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 18 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 117 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21189000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42379 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7639 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13455 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2458 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1865 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.075368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.471061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10164 81.23% 81.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 163 1.30% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 210 1.68% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 146 1.17% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 1.97% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.18% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 304 2.43% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.26% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 972 7.77% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058000 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.317492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2933 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1957 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 791 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11520 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7386 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 930 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1556 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11074 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1496 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9775 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17991 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4777 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 402 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1923 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8807 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4477 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.703884 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.500750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9387 75.02% 75.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 964 7.70% 82.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 667 5.33% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 467 3.73% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 439 3.51% 95.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 290 2.32% 97.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 213 1.70% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 56 0.45% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 29 0.23% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12512 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.22% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 87 45.08% 51.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83 43.01% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 11 5.70% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5542 62.93% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1815 20.61% 83.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1422 16.15% 99.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8807 # Type of FU issued -system.cpu.iq.rate 0.207815 # Inst issue rate -system.cpu.iq.fu_busy_cnt 193 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021914 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14716 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8133 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8961 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 962 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 818 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1923 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8488 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1719 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 319 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3083 # number of memory reference insts executed -system.cpu.iew.exec_branches 1364 # Number of branches executed -system.cpu.iew.exec_stores 1364 # Number of stores executed -system.cpu.iew.exec_rate 0.200288 # Inst execution rate -system.cpu.iew.wb_sent 8262 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8160 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4466 # num instructions producing a value -system.cpu.iew.wb_consumers 7207 # num instructions consuming a value -system.cpu.iew.wb_rate 0.192548 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.619675 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4479 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.351526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9643 81.66% 81.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 845 7.16% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 531 4.50% 93.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.82% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.50% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 0.93% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 132 1.12% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 50 0.42% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.89% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11808 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5792 # Number of instructions committed -system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2007 # Number of memory references committed -system.cpu.commit.loads 961 # Number of loads committed -system.cpu.commit.membars 7 # Number of memory barriers committed -system.cpu.commit.branches 1037 # Number of branches committed -system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. -system.cpu.commit.int_insts 5698 # Number of committed integer instructions. -system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 960 16.57% 81.92% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1027 17.73% 99.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21974 # The number of ROB reads -system.cpu.rob.rob_writes 21247 # The number of ROB writes -system.cpu.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29867 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5792 # Number of Instructions Simulated -system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.316816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.316816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136671 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136671 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13468 # number of integer regfile reads -system.cpu.int_regfile_writes 7187 # number of integer regfile writes -system.cpu.fp_regfile_reads 25 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 66.953799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2204 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 104 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.192308 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 66.953799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5386 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2204 # number of overall hits -system.cpu.dcache.overall_hits::total 2204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8129500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8129500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32497996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32497996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40627496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40627496 # number of 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# average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.222222 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 332 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 332 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83068.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83068.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99882.936170 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99882.936170 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 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Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4079 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4079 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits -system.cpu.icache.overall_hits::total 1435 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 430 # number of overall misses -system.cpu.icache.overall_misses::total 430 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33426000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33426000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33426000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33426000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1865 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1865 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1865 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1865 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230563 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230563 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230563 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230563 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230563 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230563 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77734.883721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77734.883721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77734.883721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77734.883721 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 569 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 113.800000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28154000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28154000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 232.210591 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.022573 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.990617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 65.219974 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001990 # Average percentage of cache occupancy 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number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 10 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 10 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 342 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 342 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 56 # number of ReadSharedReq misses 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for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.977143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.978022 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.977143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.978022 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98308.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98308.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80520.467836 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80520.467836 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84089.285714 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84089.285714 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82848.314607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82848.314607 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 56 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32437500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24128000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8309500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32437500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.978022 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.978022 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 455 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 455 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 455 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 227500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 156000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 444 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 396 # Transaction distribution -system.membus.trans_dist::ReadExReq 47 # Transaction distribution -system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 444 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2325750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.0 # Layer utilization (%) +sim_seconds 0.000021 +sim_ticks 21189000 +final_tick 21189000 +sim_freq 1000000000000 +host_inst_rate 70012 +host_op_rate 69995 +host_tick_rate 256014000 +host_mem_usage 260844 +host_seconds 0.08 +sim_insts 5792 +sim_ops 5792 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 +system.physmem.bytes_read::cpu.inst 21824 +system.physmem.bytes_read::cpu.data 6528 +system.physmem.bytes_read::total 28352 +system.physmem.bytes_inst_read::cpu.inst 21824 +system.physmem.bytes_inst_read::total 21824 +system.physmem.num_reads::cpu.inst 341 +system.physmem.num_reads::cpu.data 102 +system.physmem.num_reads::total 443 +system.physmem.bw_read::cpu.inst 1029968380 +system.physmem.bw_read::cpu.data 308084383 +system.physmem.bw_read::total 1338052763 +system.physmem.bw_inst_read::cpu.inst 1029968380 +system.physmem.bw_inst_read::total 1029968380 +system.physmem.bw_total::cpu.inst 1029968380 +system.physmem.bw_total::cpu.data 308084383 +system.physmem.bw_total::total 1338052763 +system.physmem.readReqs 444 +system.physmem.writeReqs 0 +system.physmem.readBursts 444 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 28416 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 28416 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 71 +system.physmem.perBankRdBursts::1 42 +system.physmem.perBankRdBursts::2 55 +system.physmem.perBankRdBursts::3 58 +system.physmem.perBankRdBursts::4 53 +system.physmem.perBankRdBursts::5 61 +system.physmem.perBankRdBursts::6 52 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 9 +system.physmem.perBankRdBursts::9 28 +system.physmem.perBankRdBursts::10 1 +system.physmem.perBankRdBursts::11 0 +system.physmem.perBankRdBursts::12 0 +system.physmem.perBankRdBursts::13 0 +system.physmem.perBankRdBursts::14 4 +system.physmem.perBankRdBursts::15 0 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 21128500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 444 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 235 +system.physmem.rdQLenPdf::1 144 +system.physmem.rdQLenPdf::2 45 +system.physmem.rdQLenPdf::3 14 +system.physmem.rdQLenPdf::4 5 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 76 +system.physmem.bytesPerActivate::mean 348.631579 +system.physmem.bytesPerActivate::gmean 212.894378 +system.physmem.bytesPerActivate::stdev 337.912685 +system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% +system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% +system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% +system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% +system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% +system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% +system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% +system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% 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+system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 +system.membus.trans_dist::ReadResp 396 +system.membus.trans_dist::ReadExReq 47 +system.membus.trans_dist::ReadExResp 47 +system.membus.trans_dist::ReadSharedReq 397 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 +system.membus.pkt_count::total 887 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 +system.membus.pkt_size::total 28352 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 444 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 444 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 444 +system.membus.reqLayer0.occupancy 553000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2325750 +system.membus.respLayer1.utilization 11.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index b654cdd15..a94f4dc46 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -89,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -119,7 +120,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -128,14 +129,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -159,6 +161,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -170,7 +173,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -178,6 +181,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -186,6 +196,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -193,7 +204,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index cbf63eeba..e1a395fe5 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:27:08 -gem5 started Jul 21 2016 14:27:33 -gem5 executing on e108600-lin, pid 28000 -command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/simple-atomic +gem5 compiled Apr 3 2017 19:22:30 +gem5 started Apr 3 2017 19:22:48 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 103795 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2896000 because target called exit() +Exiting @ tick 2896000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index d149f60ec..ecd255c85 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -1,153 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2896000 # Number of ticks simulated -final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1025115 # Simulator instruction rate (inst/s) -host_op_rate 1023244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 510651564 # Simulator tick rate (ticks/s) -host_mem_usage 238048 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5793 # Number of instructions simulated -sim_ops 5793 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory -system.physmem.bytes_read::total 26892 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23172 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23172 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 4209 # Number of bytes written to this memory -system.physmem.bytes_written::total 4209 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6754 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1046 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8001381215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1284530387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9285911602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8001381215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8001381215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1453383978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1453383978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2896000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5793 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5793 # Number of instructions committed -system.cpu.committedOps 5793 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 5698 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses -system.cpu.num_func_calls 200 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 895 # number of instructions that are conditional controls -system.cpu.num_int_insts 5698 # number of integer instructions -system.cpu.num_fp_insts 22 # number of float instructions -system.cpu.num_int_register_reads 9529 # number of times the integer registers were read -system.cpu.num_int_register_writes 4996 # number of times the integer registers were written -system.cpu.num_fp_register_reads 20 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2007 # number of memory refs -system.cpu.num_load_insts 961 # Number of load instructions -system.cpu.num_store_insts 1046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5792.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1037 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3784 65.32% 65.32% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 65.32% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.32% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 65.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::MemRead 960 16.57% 81.93% # Class of executed instruction -system.cpu.op_class::MemWrite 1027 17.73% 99.65% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.67% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 19 0.33% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5793 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6754 # Transaction distribution -system.membus.trans_dist::ReadResp 6754 # Transaction distribution -system.membus.trans_dist::WriteReq 1046 # Transaction distribution -system.membus.trans_dist::WriteResp 1046 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7800 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7800 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7800 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2896000 +final_tick 2896000 +sim_freq 1000000000000 +host_inst_rate 591136 +host_op_rate 589882 +host_tick_rate 294306849 +host_mem_usage 250080 +host_seconds 0.01 +sim_insts 5793 +sim_ops 5793 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 +system.physmem.bytes_read::cpu.inst 23172 +system.physmem.bytes_read::cpu.data 3720 +system.physmem.bytes_read::total 26892 +system.physmem.bytes_inst_read::cpu.inst 23172 +system.physmem.bytes_inst_read::total 23172 +system.physmem.bytes_written::cpu.data 4209 +system.physmem.bytes_written::total 4209 +system.physmem.num_reads::cpu.inst 5793 +system.physmem.num_reads::cpu.data 961 +system.physmem.num_reads::total 6754 +system.physmem.num_writes::cpu.data 1046 +system.physmem.num_writes::total 1046 +system.physmem.bw_read::cpu.inst 8001381215 +system.physmem.bw_read::cpu.data 1284530387 +system.physmem.bw_read::total 9285911602 +system.physmem.bw_inst_read::cpu.inst 8001381215 +system.physmem.bw_inst_read::total 8001381215 +system.physmem.bw_write::cpu.data 1453383978 +system.physmem.bw_write::total 1453383978 +system.physmem.bw_total::cpu.inst 8001381215 +system.physmem.bw_total::cpu.data 2737914365 +system.physmem.bw_total::total 10739295580 +system.pwrStateResidencyTicks::UNDEFINED 2896000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 9 +system.cpu.pwrStateResidencyTicks::ON 2896000 +system.cpu.numCycles 5793 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5793 +system.cpu.committedOps 5793 +system.cpu.num_int_alu_accesses 5698 +system.cpu.num_fp_alu_accesses 22 +system.cpu.num_func_calls 200 +system.cpu.num_conditional_control_insts 895 +system.cpu.num_int_insts 5698 +system.cpu.num_fp_insts 22 +system.cpu.num_int_register_reads 9529 +system.cpu.num_int_register_writes 4996 +system.cpu.num_fp_register_reads 20 +system.cpu.num_fp_register_writes 2 +system.cpu.num_mem_refs 2007 +system.cpu.num_load_insts 961 +system.cpu.num_store_insts 1046 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5793 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1037 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3784 65.32% 65.32% +system.cpu.op_class::IntMult 0 0.00% 65.32% +system.cpu.op_class::IntDiv 0 0.00% 65.32% +system.cpu.op_class::FloatAdd 2 0.03% 65.35% +system.cpu.op_class::FloatCmp 0 0.00% 65.35% +system.cpu.op_class::FloatCvt 0 0.00% 65.35% +system.cpu.op_class::FloatMult 0 0.00% 65.35% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.35% +system.cpu.op_class::FloatDiv 0 0.00% 65.35% +system.cpu.op_class::FloatMisc 0 0.00% 65.35% +system.cpu.op_class::FloatSqrt 0 0.00% 65.35% +system.cpu.op_class::SimdAdd 0 0.00% 65.35% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% +system.cpu.op_class::SimdAlu 0 0.00% 65.35% +system.cpu.op_class::SimdCmp 0 0.00% 65.35% +system.cpu.op_class::SimdCvt 0 0.00% 65.35% +system.cpu.op_class::SimdMisc 0 0.00% 65.35% +system.cpu.op_class::SimdMult 0 0.00% 65.35% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% +system.cpu.op_class::SimdShift 0 0.00% 65.35% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% +system.cpu.op_class::SimdSqrt 0 0.00% 65.35% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% +system.cpu.op_class::MemRead 960 16.57% 81.93% +system.cpu.op_class::MemWrite 1027 17.73% 99.65% +system.cpu.op_class::FloatMemRead 1 0.02% 99.67% +system.cpu.op_class::FloatMemWrite 19 0.33% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5793 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 +system.membus.trans_dist::ReadReq 6754 +system.membus.trans_dist::ReadResp 6754 +system.membus.trans_dist::WriteReq 1046 +system.membus.trans_dist::WriteResp 1046 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 +system.membus.pkt_count::total 15600 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 +system.membus.pkt_size::total 31101 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 7800 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 7800 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 7800 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index c79232133..90a496871 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 0783a6d90..cac26c8a8 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38676 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:40 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64886 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 2694500 because target called exit() +Hello World!Exiting @ tick 2694500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 22810bda7..6ce9e512f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2694500 # Number of ticks simulated -final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 818529 # Simulator instruction rate (inst/s) -host_op_rate 815458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 411063520 # Simulator tick rate (ticks/s) -host_mem_usage 239556 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory -system.physmem.bytes_read::total 26082 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21480 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory -system.physmem.bytes_written::total 5065 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5370 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 715 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6085 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory -system.physmem.num_writes::total 673 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7971794396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1707923548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9679717944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7971794396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7971794396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1879755057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1879755057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2694500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5390 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4846 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6085 # Transaction distribution -system.membus.trans_dist::ReadResp 6085 # Transaction distribution -system.membus.trans_dist::WriteReq 673 # Transaction distribution -system.membus.trans_dist::WriteResp 673 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6758 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6758 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6758 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2694500 +final_tick 2694500 +sim_freq 1000000000000 +host_inst_rate 549051 +host_op_rate 547755 +host_tick_rate 276495662 +host_mem_usage 251832 +host_seconds 0.01 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 +system.physmem.bytes_read::cpu.inst 21480 +system.physmem.bytes_read::cpu.data 4602 +system.physmem.bytes_read::total 26082 +system.physmem.bytes_inst_read::cpu.inst 21480 +system.physmem.bytes_inst_read::total 21480 +system.physmem.bytes_written::cpu.data 5065 +system.physmem.bytes_written::total 5065 +system.physmem.num_reads::cpu.inst 5370 +system.physmem.num_reads::cpu.data 715 +system.physmem.num_reads::total 6085 +system.physmem.num_writes::cpu.data 673 +system.physmem.num_writes::total 673 +system.physmem.bw_read::cpu.inst 7971794396 +system.physmem.bw_read::cpu.data 1707923548 +system.physmem.bw_read::total 9679717944 +system.physmem.bw_inst_read::cpu.inst 7971794396 +system.physmem.bw_inst_read::total 7971794396 +system.physmem.bw_write::cpu.data 1879755057 +system.physmem.bw_write::total 1879755057 +system.physmem.bw_total::cpu.inst 7971794396 +system.physmem.bw_total::cpu.data 3587678605 +system.physmem.bw_total::total 11559473001 +system.pwrStateResidencyTicks::UNDEFINED 2694500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 2694500 +system.cpu.numCycles 5390 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5327 +system.cpu.committedOps 5327 +system.cpu.num_int_alu_accesses 4505 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 773 +system.cpu.num_int_insts 4505 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10598 +system.cpu.num_int_register_writes 4846 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1401 +system.cpu.num_load_insts 723 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5390 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1121 +system.cpu.op_class::No_OpClass 173 3.22% 3.22% +system.cpu.op_class::IntAlu 3796 70.69% 73.91% +system.cpu.op_class::IntMult 0 0.00% 73.91% +system.cpu.op_class::IntDiv 0 0.00% 73.91% +system.cpu.op_class::FloatAdd 0 0.00% 73.91% +system.cpu.op_class::FloatCmp 0 0.00% 73.91% +system.cpu.op_class::FloatCvt 0 0.00% 73.91% +system.cpu.op_class::FloatMult 0 0.00% 73.91% +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::FloatDiv 0 0.00% 73.91% +system.cpu.op_class::FloatMisc 0 0.00% 73.91% +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdAdd 0 0.00% 73.91% +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% +system.cpu.op_class::SimdAlu 0 0.00% 73.91% +system.cpu.op_class::SimdCmp 0 0.00% 73.91% +system.cpu.op_class::SimdCvt 0 0.00% 73.91% +system.cpu.op_class::SimdMisc 0 0.00% 73.91% +system.cpu.op_class::SimdMult 0 0.00% 73.91% +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdShift 0 0.00% 73.91% +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% +system.cpu.op_class::MemRead 723 13.46% 87.37% +system.cpu.op_class::MemWrite 678 12.63% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5370 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 +system.membus.trans_dist::ReadReq 6085 +system.membus.trans_dist::ReadResp 6085 +system.membus.trans_dist::WriteReq 673 +system.membus.trans_dist::WriteResp 673 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 +system.membus.pkt_count::total 13516 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 +system.membus.pkt_size::total 31147 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6758 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6758 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6758 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 7609bf228..74133b340 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -122,7 +123,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -131,14 +132,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -297,6 +299,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index f6f6f15a5..95500d55b 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -7,4 +7,5 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 36ed80c84..8d604768a 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:46:33 -gem5 executing on e108600-lin, pid 17405 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:37 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64825 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 86746 because target called exit() +Hello World!Exiting @ tick 86746 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 05934eae0..83a3d1ad4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,355 +1,355 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000087 # Number of seconds simulated -sim_ticks 86746 # Number of ticks simulated -final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 122857 # Simulator instruction rate (inst/s) -host_op_rate 122829 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1999767 # Simulator tick rate (ticks/s) -host_mem_usage 415460 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 82240 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 951006386 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 951006386 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 948055242 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 948055242 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1899061628 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1899061628 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1289 # Number of read requests accepted -system.mem_ctrls.writeReqs 1285 # Number of write requests accepted -system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44800 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 37696 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 45504 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 589 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 555 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 17 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 119 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 55 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 31 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 13 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 62 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 14 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 118 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 14 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 62 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 64 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 16 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 86680 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1289 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 700 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 35 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 46 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 247 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 359.384615 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 236.451062 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 319.751749 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 54 21.86% 21.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 65 26.32% 48.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 38 15.38% 63.56% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 27 10.93% 74.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 8 3.24% 77.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 4.05% 81.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 11 4.45% 86.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 3.64% 89.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 10.12% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 247 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 44 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.840909 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.640724 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.183849 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 4.55% 4.55% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 21 47.73% 52.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 40.91% 93.18% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 2 4.55% 97.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.27% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 44 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 44 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.159091 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.147705 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.644951 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 41 93.18% 93.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.27% 95.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 4.55% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 44 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12987 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26287 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3500 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 18.55 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 37.55 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 516.45 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 524.57 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 951.01 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 948.06 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.13 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.18 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 508 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 652 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 72.57 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 89.32 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.68 # Average gap between requests -system.mem_ctrls.pageHitRate 81.12 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1099560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 587328 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4969440 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 3574656 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10338432 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 148224 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 27605784 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 1209216 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 56293680 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 648.948424 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 63519 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 64 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 3149 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 20134 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 60539 # Time in different power states -system.mem_ctrls_1.actEnergy 692580 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 367080 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 3027360 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2363616 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 9621600 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 296448 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 26302992 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2761728 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 52194444 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 601.692804 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 64843 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 422 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7192 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 18590 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 57682 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86746 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 86746 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.999988 # Number of idle cycles -system.cpu.num_busy_cycles 86745.000012 # Number of busy cycles -system.cpu.not_idle_fraction 0.999988 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000012 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2574 # delay histogram for all message -system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2574 # delay histogram for all message +sim_seconds 0.000087 +sim_ticks 86746 +final_tick 86746 +sim_freq 1000000000 +host_inst_rate 50496 +host_op_rate 50484 +host_tick_rate 821944 +host_mem_usage 426428 +host_seconds 0.11 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86746 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 +system.mem_ctrls.bytes_read::total 82496 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 +system.mem_ctrls.bytes_written::total 82240 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 +system.mem_ctrls.num_reads::total 1289 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 +system.mem_ctrls.num_writes::total 1285 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 951006386 +system.mem_ctrls.bw_read::total 951006386 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 948055242 +system.mem_ctrls.bw_write::total 948055242 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1899061628 +system.mem_ctrls.bw_total::total 1899061628 +system.mem_ctrls.readReqs 1289 +system.mem_ctrls.writeReqs 1285 +system.mem_ctrls.readBursts 1289 +system.mem_ctrls.writeBursts 1285 +system.mem_ctrls.bytesReadDRAM 44800 +system.mem_ctrls.bytesReadWrQ 37696 +system.mem_ctrls.bytesWritten 45504 +system.mem_ctrls.bytesReadSys 82496 +system.mem_ctrls.bytesWrittenSys 82240 +system.mem_ctrls.servicedByWrQ 589 +system.mem_ctrls.mergedWrBursts 555 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 28 +system.mem_ctrls.perBankRdBursts::1 17 +system.mem_ctrls.perBankRdBursts::2 1 +system.mem_ctrls.perBankRdBursts::3 8 +system.mem_ctrls.perBankRdBursts::4 0 +system.mem_ctrls.perBankRdBursts::5 119 +system.mem_ctrls.perBankRdBursts::6 121 +system.mem_ctrls.perBankRdBursts::7 141 +system.mem_ctrls.perBankRdBursts::8 55 +system.mem_ctrls.perBankRdBursts::9 31 +system.mem_ctrls.perBankRdBursts::10 13 +system.mem_ctrls.perBankRdBursts::11 62 +system.mem_ctrls.perBankRdBursts::12 21 +system.mem_ctrls.perBankRdBursts::13 61 +system.mem_ctrls.perBankRdBursts::14 14 +system.mem_ctrls.perBankRdBursts::15 8 +system.mem_ctrls.perBankWrBursts::0 28 +system.mem_ctrls.perBankWrBursts::1 18 +system.mem_ctrls.perBankWrBursts::2 1 +system.mem_ctrls.perBankWrBursts::3 8 +system.mem_ctrls.perBankWrBursts::4 0 +system.mem_ctrls.perBankWrBursts::5 118 +system.mem_ctrls.perBankWrBursts::6 114 +system.mem_ctrls.perBankWrBursts::7 141 +system.mem_ctrls.perBankWrBursts::8 61 +system.mem_ctrls.perBankWrBursts::9 35 +system.mem_ctrls.perBankWrBursts::10 14 +system.mem_ctrls.perBankWrBursts::11 62 +system.mem_ctrls.perBankWrBursts::12 23 +system.mem_ctrls.perBankWrBursts::13 64 +system.mem_ctrls.perBankWrBursts::14 16 +system.mem_ctrls.perBankWrBursts::15 8 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 86680 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1289 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1285 +system.mem_ctrls.rdQLenPdf::0 700 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 3 +system.mem_ctrls.wrQLenPdf::16 3 +system.mem_ctrls.wrQLenPdf::17 35 +system.mem_ctrls.wrQLenPdf::18 45 +system.mem_ctrls.wrQLenPdf::19 45 +system.mem_ctrls.wrQLenPdf::20 49 +system.mem_ctrls.wrQLenPdf::21 49 +system.mem_ctrls.wrQLenPdf::22 46 +system.mem_ctrls.wrQLenPdf::23 44 +system.mem_ctrls.wrQLenPdf::24 44 +system.mem_ctrls.wrQLenPdf::25 44 +system.mem_ctrls.wrQLenPdf::26 44 +system.mem_ctrls.wrQLenPdf::27 44 +system.mem_ctrls.wrQLenPdf::28 44 +system.mem_ctrls.wrQLenPdf::29 44 +system.mem_ctrls.wrQLenPdf::30 44 +system.mem_ctrls.wrQLenPdf::31 44 +system.mem_ctrls.wrQLenPdf::32 44 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 247 +system.mem_ctrls.bytesPerActivate::mean 359.384615 +system.mem_ctrls.bytesPerActivate::gmean 236.451062 +system.mem_ctrls.bytesPerActivate::stdev 319.751749 +system.mem_ctrls.bytesPerActivate::0-127 54 21.86% 21.86% +system.mem_ctrls.bytesPerActivate::128-255 65 26.32% 48.18% +system.mem_ctrls.bytesPerActivate::256-383 38 15.38% 63.56% +system.mem_ctrls.bytesPerActivate::384-511 27 10.93% 74.49% +system.mem_ctrls.bytesPerActivate::512-639 8 3.24% 77.73% +system.mem_ctrls.bytesPerActivate::640-767 10 4.05% 81.78% +system.mem_ctrls.bytesPerActivate::768-895 11 4.45% 86.23% +system.mem_ctrls.bytesPerActivate::896-1023 9 3.64% 89.88% +system.mem_ctrls.bytesPerActivate::1024-1151 25 10.12% 100.00% +system.mem_ctrls.bytesPerActivate::total 247 +system.mem_ctrls.rdPerTurnAround::samples 44 +system.mem_ctrls.rdPerTurnAround::mean 15.840909 +system.mem_ctrls.rdPerTurnAround::gmean 15.640724 +system.mem_ctrls.rdPerTurnAround::stdev 3.183849 +system.mem_ctrls.rdPerTurnAround::12-13 2 4.55% 4.55% +system.mem_ctrls.rdPerTurnAround::14-15 21 47.73% 52.27% +system.mem_ctrls.rdPerTurnAround::16-17 18 40.91% 93.18% +system.mem_ctrls.rdPerTurnAround::18-19 2 4.55% 97.73% +system.mem_ctrls.rdPerTurnAround::34-35 1 2.27% 100.00% +system.mem_ctrls.rdPerTurnAround::total 44 +system.mem_ctrls.wrPerTurnAround::samples 44 +system.mem_ctrls.wrPerTurnAround::mean 16.159091 +system.mem_ctrls.wrPerTurnAround::gmean 16.147705 +system.mem_ctrls.wrPerTurnAround::stdev 0.644951 +system.mem_ctrls.wrPerTurnAround::16 41 93.18% 93.18% +system.mem_ctrls.wrPerTurnAround::17 1 2.27% 95.45% +system.mem_ctrls.wrPerTurnAround::19 2 4.55% 100.00% +system.mem_ctrls.wrPerTurnAround::total 44 +system.mem_ctrls.totQLat 12987 +system.mem_ctrls.totMemAccLat 26287 +system.mem_ctrls.totBusLat 3500 +system.mem_ctrls.avgQLat 18.55 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 37.55 +system.mem_ctrls.avgRdBW 516.45 +system.mem_ctrls.avgWrBW 524.57 +system.mem_ctrls.avgRdBWSys 951.01 +system.mem_ctrls.avgWrBWSys 948.06 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 8.13 +system.mem_ctrls.busUtilRead 4.03 +system.mem_ctrls.busUtilWrite 4.10 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.18 +system.mem_ctrls.readRowHits 508 +system.mem_ctrls.writeRowHits 652 +system.mem_ctrls.readRowHitRate 72.57 +system.mem_ctrls.writeRowHitRate 89.32 +system.mem_ctrls.avgGap 33.68 +system.mem_ctrls.pageHitRate 81.12 +system.mem_ctrls_0.actEnergy 1099560 +system.mem_ctrls_0.preEnergy 587328 +system.mem_ctrls_0.readEnergy 4969440 +system.mem_ctrls_0.writeEnergy 3574656 +system.mem_ctrls_0.refreshEnergy 6761040.000000 +system.mem_ctrls_0.actBackEnergy 10338432 +system.mem_ctrls_0.preBackEnergy 148224 +system.mem_ctrls_0.actPowerDownEnergy 27605784 +system.mem_ctrls_0.prePowerDownEnergy 1209216 +system.mem_ctrls_0.selfRefreshEnergy 0 +system.mem_ctrls_0.totalEnergy 56293680 +system.mem_ctrls_0.averagePower 648.948424 +system.mem_ctrls_0.totalIdleTime 63519 +system.mem_ctrls_0.memoryStateTime::IDLE 64 +system.mem_ctrls_0.memoryStateTime::REF 2860 +system.mem_ctrls_0.memoryStateTime::SREF 0 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 3149 +system.mem_ctrls_0.memoryStateTime::ACT 20134 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 60539 +system.mem_ctrls_1.actEnergy 692580 +system.mem_ctrls_1.preEnergy 367080 +system.mem_ctrls_1.readEnergy 3027360 +system.mem_ctrls_1.writeEnergy 2363616 +system.mem_ctrls_1.refreshEnergy 6761040.000000 +system.mem_ctrls_1.actBackEnergy 9621600 +system.mem_ctrls_1.preBackEnergy 296448 +system.mem_ctrls_1.actPowerDownEnergy 26302992 +system.mem_ctrls_1.prePowerDownEnergy 2761728 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 52194444 +system.mem_ctrls_1.averagePower 601.692804 +system.mem_ctrls_1.totalIdleTime 64843 +system.mem_ctrls_1.memoryStateTime::IDLE 422 +system.mem_ctrls_1.memoryStateTime::REF 2860 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7192 +system.mem_ctrls_1.memoryStateTime::ACT 18590 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 57682 +system.pwrStateResidencyTicks::UNDEFINED 86746 +system.cpu.clk_domain.clock 1 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 86746 +system.cpu.numCycles 86746 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5327 +system.cpu.committedOps 5327 +system.cpu.num_int_alu_accesses 4505 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 773 +system.cpu.num_int_insts 4505 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10598 +system.cpu.num_int_register_writes 4845 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1401 +system.cpu.num_load_insts 723 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 86746 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1121 +system.cpu.op_class::No_OpClass 173 3.22% 3.22% +system.cpu.op_class::IntAlu 3796 70.69% 73.91% +system.cpu.op_class::IntMult 0 0.00% 73.91% +system.cpu.op_class::IntDiv 0 0.00% 73.91% +system.cpu.op_class::FloatAdd 0 0.00% 73.91% +system.cpu.op_class::FloatCmp 0 0.00% 73.91% +system.cpu.op_class::FloatCvt 0 0.00% 73.91% +system.cpu.op_class::FloatMult 0 0.00% 73.91% +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::FloatDiv 0 0.00% 73.91% +system.cpu.op_class::FloatMisc 0 0.00% 73.91% +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdAdd 0 0.00% 73.91% +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% +system.cpu.op_class::SimdAlu 0 0.00% 73.91% +system.cpu.op_class::SimdCmp 0 0.00% 73.91% +system.cpu.op_class::SimdCvt 0 0.00% 73.91% +system.cpu.op_class::SimdMisc 0 0.00% 73.91% +system.cpu.op_class::SimdMult 0 0.00% 73.91% +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdShift 0 0.00% 73.91% +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% +system.cpu.op_class::MemRead 723 13.46% 87.37% +system.cpu.op_class::MemWrite 678 12.63% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5370 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2574 +system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2574 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 6759 @@ -381,36 +381,36 @@ system.ruby.miss_latency_hist_seqr::stdev 35.397665 system.ruby.miss_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1289 system.ruby.Directory.incomplete_times_seqr 1288 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers0.percent_links_utilized 7.418209 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 @@ -420,13 +420,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers1.percent_links_utilized 7.418209 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 @@ -436,25 +436,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 +system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 +system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 +system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 +system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 +system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers2.percent_links_utilized 7.418209 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 @@ -464,7 +464,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 10312 system.ruby.network.routers2.msg_bytes.Data::2 92520 system.ruby.network.routers2.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.msg_count.Control 3867 system.ruby.network.msg_count.Data 3855 system.ruby.network.msg_count.Response_Data 3867 @@ -473,7 +473,7 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers0.throttle0.link_utilization 7.427432 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 @@ -504,16 +504,16 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 92520 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1289 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1289 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 1289 +system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1289 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1285 +system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1285 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 715 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 467bc0996..48a2ce7b0 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index a65457027..55314358f 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38670 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64913 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 30526500 because target called exit() +Hello World!Exiting @ tick 30915500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 7d03d8b84..058393673 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,497 +1,497 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30915500 # Number of ticks simulated -final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536275 # Simulator instruction rate (inst/s) -host_op_rate 534981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3098223884 # Simulator tick rate (ticks/s) -host_mem_usage 250312 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 24896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61831 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was 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cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8321000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8321000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8321000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for 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overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 116.844047 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 116.844047 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057053 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10999 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits -system.cpu.icache.overall_hits::total 5114 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses -system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16093500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16093500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16093500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16093500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16093500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16093500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 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-system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15836500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15836500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15836500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15836500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15836500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15836500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 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Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011871 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 255 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 255 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 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ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992218 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.285347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.285347 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4090500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4090500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12878000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12878000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12878000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19645000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12878000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19645000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 389 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 389 # Request fanout histogram -system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) +sim_seconds 0.000031 +sim_ticks 30915500 +final_tick 30915500 +sim_freq 1000000000000 +host_inst_rate 330902 +host_op_rate 330442 +host_tick_rate 1915496347 +host_mem_usage 261572 +host_seconds 0.02 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 +system.physmem.bytes_read::cpu.inst 16320 +system.physmem.bytes_read::cpu.data 8576 +system.physmem.bytes_read::total 24896 +system.physmem.bytes_inst_read::cpu.inst 16320 +system.physmem.bytes_inst_read::total 16320 +system.physmem.num_reads::cpu.inst 255 +system.physmem.num_reads::cpu.data 134 +system.physmem.num_reads::total 389 +system.physmem.bw_read::cpu.inst 527890540 +system.physmem.bw_read::cpu.data 277401304 +system.physmem.bw_read::total 805291844 +system.physmem.bw_inst_read::cpu.inst 527890540 +system.physmem.bw_inst_read::total 527890540 +system.physmem.bw_total::cpu.inst 527890540 +system.physmem.bw_total::cpu.data 277401304 +system.physmem.bw_total::total 805291844 +system.pwrStateResidencyTicks::UNDEFINED 30915500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 30915500 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81.942328 +system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 +system.cpu.dcache.tags.occ_percent::total 0.020005 +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 +system.cpu.dcache.tags.tag_accesses 2911 +system.cpu.dcache.tags.data_accesses 2911 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 +system.cpu.dcache.ReadReq_hits::cpu.data 661 +system.cpu.dcache.ReadReq_hits::total 661 +system.cpu.dcache.WriteReq_hits::cpu.data 592 +system.cpu.dcache.WriteReq_hits::total 592 +system.cpu.dcache.demand_hits::cpu.data 1253 +system.cpu.dcache.demand_hits::total 1253 +system.cpu.dcache.overall_hits::cpu.data 1253 +system.cpu.dcache.overall_hits::total 1253 +system.cpu.dcache.ReadReq_misses::cpu.data 54 +system.cpu.dcache.ReadReq_misses::total 54 +system.cpu.dcache.WriteReq_misses::cpu.data 81 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+system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 +system.cpu.dcache.ReadReq_mshr_misses::total 54 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 +system.cpu.dcache.WriteReq_mshr_misses::total 81 +system.cpu.dcache.demand_mshr_misses::cpu.data 135 +system.cpu.dcache.demand_mshr_misses::total 135 +system.cpu.dcache.overall_mshr_misses::cpu.data 135 +system.cpu.dcache.overall_mshr_misses::total 135 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 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+system.membus.snoop_fanout::samples 389 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 389 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 389 +system.membus.reqLayer0.occupancy 389500 +system.membus.reqLayer0.utilization 1.3 +system.membus.respLayer1.occupancy 1945000 +system.membus.respLayer1.utilization 6.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 5809007c6..b5dc4aa3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -65,7 +66,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -764,7 +766,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -773,14 +775,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 5ab7e4cb5..d96836b29 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:55:59 -gem5 started Nov 29 2016 18:56:21 -gem5 executing on zizzer, pid 719 -command line: /z/powerjg/gem5-upstream/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87180 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 22466500 because target called exit() +Exiting @ tick 22516500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index a160b1441..f96155fcc 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,995 +1,995 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22516500 # Number of ticks simulated -final_tick 22516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69174 # Simulator instruction rate (inst/s) -host_op_rate 125309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 289442861 # Simulator tick rate (ticks/s) -host_mem_usage 271352 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 5380 # Number of instructions simulated -sim_ops 9747 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 417 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 787333733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 397930407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1185264140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 787333733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 397930407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1185264140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 31 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 5 # Per bank write bursts -system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 51 # Per bank write bursts -system.physmem.perBankRdBursts::5 44 # Per bank write bursts -system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 36 # Per bank write bursts -system.physmem.perBankRdBursts::8 24 # Per bank write bursts -system.physmem.perBankRdBursts::9 71 # Per bank write bursts -system.physmem.perBankRdBursts::10 64 # Per bank write bursts -system.physmem.perBankRdBursts::11 16 # Per bank write bursts -system.physmem.perBankRdBursts::12 2 # Per bank write bursts -system.physmem.perBankRdBursts::13 20 # Per bank write bursts -system.physmem.perBankRdBursts::14 6 # Per bank write bursts -system.physmem.perBankRdBursts::15 17 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22387500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 417 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.673469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.283411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.721287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 41.84% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 22.45% 64.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.33% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 7.14% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.02% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.06% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 6651000 # Total ticks spent queuing -system.physmem.totMemAccLat 14469750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15949.64 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34699.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1185.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1185.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.26 # Data bus utilization in percentage -system.physmem.busUtilRead 9.26 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 307 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53687.05 # Average gap between requests -system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 307020 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140415 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1406580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2488050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7581570 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 138720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13319955 # Total energy per rank (pJ) -system.physmem_0.averagePower 591.537915 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16888750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 361000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 4997500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16620500 # Time in different power states -system.physmem_1.actEnergy 478380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231495 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2961150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 80160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7211640 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13762905 # Total energy per rank (pJ) -system.physmem_1.averagePower 611.209282 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15691750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6065500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15828000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3542 # Number of BP lookups -system.cpu.branchPred.condPredicted 3542 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 576 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3006 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 386 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 97 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3006 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 514 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2492 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 416 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22516500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45034 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12047 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16169 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3542 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 900 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1582 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2077 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.701309 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20389 82.42% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 0.72% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 168 0.68% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 0.99% 84.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 0.87% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 220 0.89% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 262 1.06% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 167 0.68% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2892 11.69% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078652 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.359040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12032 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8141 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3437 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26977 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12302 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1085 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4966 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 25351 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 77 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4831 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 28444 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61768 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17381 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 24 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1430 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2685 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1593 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22118 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 157 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12393 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17118 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24737 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.737114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.712019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19548 79.02% 79.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1204 4.87% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 865 3.50% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 579 2.34% 89.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 831 3.36% 93.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 615 2.49% 95.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 628 2.54% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 340 1.37% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127 0.51% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24737 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 218 79.85% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 40 14.65% 94.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 5.49% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14605 80.10% 80.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2269 12.44% 92.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1341 7.35% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18234 # Type of FU issued -system.cpu.iq.rate 0.404894 # Inst issue rate -system.cpu.iq.fu_busy_cnt 273 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 61627 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34538 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16576 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18501 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 199 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 658 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1518 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22140 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2685 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 676 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 803 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17166 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1068 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1740 # Number of branches executed -system.cpu.iew.exec_stores 1252 # Number of stores executed -system.cpu.iew.exec_rate 0.381179 # Inst execution rate -system.cpu.iew.wb_sent 16892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16580 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11141 # num instructions producing a value -system.cpu.iew.wb_consumers 17351 # num instructions consuming a value -system.cpu.iew.wb_rate 0.368166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642096 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12392 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22646 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.430407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19391 85.63% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1011 4.46% 90.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 560 2.47% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 726 3.21% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 383 1.69% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 128 0.57% 98.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.52% 98.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.33% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 255 1.13% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22646 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5380 # Number of instructions committed -system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1988 # Number of memory references committed -system.cpu.commit.loads 1053 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 1208 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 9653 # Number of committed integer instructions. -system.cpu.commit.function_calls 106 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 44530 # The number of ROB reads -system.cpu.rob.rob_writes 46401 # The number of ROB writes -system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20297 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5380 # Number of Instructions Simulated -system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.370632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.370632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.119465 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.119465 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21947 # number of integer regfile reads -system.cpu.int_regfile_writes 13377 # number of integer regfile writes -system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8355 # number of cc regfile reads -system.cpu.cc_regfile_writes 5130 # number of cc regfile writes -system.cpu.misc_regfile_reads 7644 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.908470 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2549 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.207143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.908470 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5608 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5608 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1687 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1687 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2549 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2549 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2549 # number of overall hits -system.cpu.dcache.overall_hits::total 2549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 185 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 185 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 185 # number of overall misses -system.cpu.dcache.overall_misses::total 185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6772000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6772000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16584000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16584000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067666 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067666 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067666 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067666 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87607.142857 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87607.142857 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 92767.123288 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 92767.123288 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 89643.243243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 89643.243243 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.523512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1695 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.097122 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.523512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4432 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1695 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1695 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1695 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1695 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1695 # number of overall hits -system.cpu.icache.overall_hits::total 1695 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 382 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 382 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 382 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 382 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 382 # number of overall misses -system.cpu.icache.overall_misses::total 382 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30098500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30098500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30098500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30098500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2077 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2077 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2077 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2077 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183919 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183919 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183919 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78791.884817 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78791.884817 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 104 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 104 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 104 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 104 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 104 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23308500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23308500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 212.529421 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.555666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.973755 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003984 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002502 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 67 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 67 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses -system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6317500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6317500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22879500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12907000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35786500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22879500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12907000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35786500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20109500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11507000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31616500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20109500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11507000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31616500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 344 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 344 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2226500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.9 # Layer utilization (%) +sim_seconds 0.000023 +sim_ticks 22516500 +final_tick 22516500 +sim_freq 1000000000000 +host_inst_rate 26720 +host_op_rate 48405 +host_tick_rate 111808950 +host_mem_usage 281880 +host_seconds 0.20 +sim_insts 5380 +sim_ops 9747 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 +system.physmem.bytes_read::cpu.inst 17728 +system.physmem.bytes_read::cpu.data 8960 +system.physmem.bytes_read::total 26688 +system.physmem.bytes_inst_read::cpu.inst 17728 +system.physmem.bytes_inst_read::total 17728 +system.physmem.num_reads::cpu.inst 277 +system.physmem.num_reads::cpu.data 140 +system.physmem.num_reads::total 417 +system.physmem.bw_read::cpu.inst 787333733 +system.physmem.bw_read::cpu.data 397930407 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+system.cpu.toL2Bus.trans_dist::ReadResp 345 +system.cpu.toL2Bus.trans_dist::ReadExReq 73 +system.cpu.toL2Bus.trans_dist::ReadExResp 73 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 +system.cpu.toL2Bus.pkt_count::total 836 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 +system.cpu.toL2Bus.pkt_size::total 26752 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 418 +system.cpu.toL2Bus.snoop_fanout::mean 0.002392 +system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% +system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 418 +system.cpu.toL2Bus.reqLayer0.occupancy 209000 +system.cpu.toL2Bus.reqLayer0.utilization 0.9 +system.cpu.toL2Bus.respLayer0.occupancy 417000 +system.cpu.toL2Bus.respLayer0.utilization 1.9 +system.cpu.toL2Bus.respLayer1.occupancy 210000 +system.cpu.toL2Bus.respLayer1.utilization 0.9 +system.membus.snoop_filter.tot_requests 417 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 +system.membus.trans_dist::ReadResp 344 +system.membus.trans_dist::ReadExReq 73 +system.membus.trans_dist::ReadExResp 73 +system.membus.trans_dist::ReadSharedReq 344 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 +system.membus.pkt_count::total 834 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 +system.membus.pkt_size::total 26688 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 417 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 417 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 417 +system.membus.reqLayer0.occupancy 504000 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 2226500 +system.membus.respLayer1.utilization 9.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 62043a3c5..8968a4ed6 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index bd2d6df6a..8dcc9cbbd 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18561 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87156 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5615000 because target called exit() +Exiting @ tick 5615000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 54ef40828..2360c7c26 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5615000 # Number of ticks simulated -final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340881 # Simulator instruction rate (inst/s) -host_op_rate 616836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 354943212 # Simulator tick rate (ticks/s) -host_mem_usage 258192 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory -system.physmem.bytes_read::total 61978 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory -system.physmem.bytes_written::total 7112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1053 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7917 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory -system.physmem.num_writes::total 935 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9779519145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1258414960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11037934105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5615000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11231 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11230.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7917 # Transaction distribution -system.membus.trans_dist::ReadResp 7917 # Transaction distribution -system.membus.trans_dist::WriteReq 935 # Transaction distribution -system.membus.trans_dist::WriteResp 935 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 8852 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 8852 # Request fanout histogram +sim_seconds 0.000006 +sim_ticks 5615000 +final_tick 5615000 +sim_freq 1000000000000 +host_inst_rate 289662 +host_op_rate 524226 +host_tick_rate 301675446 +host_mem_usage 269844 +host_seconds 0.02 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 +system.physmem.bytes_read::cpu.inst 54912 +system.physmem.bytes_read::cpu.data 7066 +system.physmem.bytes_read::total 61978 +system.physmem.bytes_inst_read::cpu.inst 54912 +system.physmem.bytes_inst_read::total 54912 +system.physmem.bytes_written::cpu.data 7112 +system.physmem.bytes_written::total 7112 +system.physmem.num_reads::cpu.inst 6864 +system.physmem.num_reads::cpu.data 1053 +system.physmem.num_reads::total 7917 +system.physmem.num_writes::cpu.data 935 +system.physmem.num_writes::total 935 +system.physmem.bw_read::cpu.inst 9779519145 +system.physmem.bw_read::cpu.data 1258414960 +system.physmem.bw_read::total 11037934105 +system.physmem.bw_inst_read::cpu.inst 9779519145 +system.physmem.bw_inst_read::total 9779519145 +system.physmem.bw_write::cpu.data 1266607302 +system.physmem.bw_write::total 1266607302 +system.physmem.bw_total::cpu.inst 9779519145 +system.physmem.bw_total::cpu.data 2525022262 +system.physmem.bw_total::total 12304541407 +system.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 5615000 +system.cpu.numCycles 11231 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 11231 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 +system.membus.trans_dist::ReadReq 7917 +system.membus.trans_dist::ReadResp 7917 +system.membus.trans_dist::WriteReq 935 +system.membus.trans_dist::WriteResp 935 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 +system.membus.pkt_count_system.cpu.icache_port::total 13728 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 +system.membus.pkt_count_system.cpu.dcache_port::total 3976 +system.membus.pkt_count::total 17704 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 +system.membus.pkt_size_system.cpu.icache_port::total 54912 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 +system.membus.pkt_size_system.cpu.dcache_port::total 14178 +system.membus.pkt_size::total 69090 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 8852 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 8852 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 8852 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 49adea038..155aa9c1d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -171,7 +173,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -180,14 +182,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -346,6 +349,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index f6f6f15a5..95500d55b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -7,4 +7,5 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 60c5b94b3..18eac1046 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:01 -gem5 executing on e108600-lin, pid 17636 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87199 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 91859 because target called exit() +Exiting @ tick 91859 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 843ed7643..f79527e54 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,369 +1,369 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91859 # Number of ticks simulated -final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 94122 # Simulator instruction rate (inst/s) -host_op_rate 170479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1606243 # Simulator tick rate (ticks/s) -host_mem_usage 432368 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1377 # Number of read requests accepted -system.mem_ctrls.writeReqs 1373 # Number of write requests accepted -system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 41408 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 46720 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 730 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 702 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 60 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 39 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 115 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 55 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 48 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 38 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 130 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 123 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 37 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 91773 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 647 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 263 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 304.669202 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 201.653389 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 284.735596 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 263 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.100000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.846587 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.484765 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.281263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.822753 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12721 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25014 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3235 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 19.66 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38.66 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 450.78 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 454.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 959.38 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 956.60 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.07 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.52 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.84 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 435 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 591 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.23 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 88.08 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.37 # Average gap between requests -system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 340032 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3175872 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2246688 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10273224 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 269568 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 25208136 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 4818816 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 743760.000000 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 55115796 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 600.004311 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 68393 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 346 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 798 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 19759 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 # Time in different power states -system.mem_ctrls_1.actEnergy 1285200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 676200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4215456 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3198816 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 9576912 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 183552 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 28147512 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 3322368 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 57367056 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 624.512089 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 70328 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 150 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2866 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 18464 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 91859 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 91859 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999989 # Number of idle cycles -system.cpu.num_busy_cycles 91858.000011 # Number of busy cycles -system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000011 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2750 # delay histogram for all message -system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2750 # delay histogram for all message +sim_seconds 0.000092 +sim_ticks 91859 +final_tick 91859 +sim_freq 1000000000 +host_inst_rate 44912 +host_op_rate 81347 +host_tick_rate 766447 +host_mem_usage 444688 +host_seconds 0.12 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 +system.mem_ctrls.bytes_read::total 88128 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 +system.mem_ctrls.bytes_written::total 87872 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 +system.mem_ctrls.num_reads::total 1377 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 +system.mem_ctrls.num_writes::total 1373 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 +system.mem_ctrls.bw_read::total 959383403 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 +system.mem_ctrls.bw_write::total 956596523 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 +system.mem_ctrls.bw_total::total 1915979926 +system.mem_ctrls.readReqs 1377 +system.mem_ctrls.writeReqs 1373 +system.mem_ctrls.readBursts 1377 +system.mem_ctrls.writeBursts 1373 +system.mem_ctrls.bytesReadDRAM 41408 +system.mem_ctrls.bytesReadWrQ 46720 +system.mem_ctrls.bytesWritten 41728 +system.mem_ctrls.bytesReadSys 88128 +system.mem_ctrls.bytesWrittenSys 87872 +system.mem_ctrls.servicedByWrQ 730 +system.mem_ctrls.mergedWrBursts 702 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 60 +system.mem_ctrls.perBankRdBursts::1 2 +system.mem_ctrls.perBankRdBursts::2 6 +system.mem_ctrls.perBankRdBursts::3 10 +system.mem_ctrls.perBankRdBursts::4 51 +system.mem_ctrls.perBankRdBursts::5 53 +system.mem_ctrls.perBankRdBursts::6 39 +system.mem_ctrls.perBankRdBursts::7 57 +system.mem_ctrls.perBankRdBursts::8 28 +system.mem_ctrls.perBankRdBursts::9 129 +system.mem_ctrls.perBankRdBursts::10 115 +system.mem_ctrls.perBankRdBursts::11 24 +system.mem_ctrls.perBankRdBursts::12 2 +system.mem_ctrls.perBankRdBursts::13 28 +system.mem_ctrls.perBankRdBursts::14 8 +system.mem_ctrls.perBankRdBursts::15 35 +system.mem_ctrls.perBankWrBursts::0 55 +system.mem_ctrls.perBankWrBursts::1 2 +system.mem_ctrls.perBankWrBursts::2 6 +system.mem_ctrls.perBankWrBursts::3 8 +system.mem_ctrls.perBankWrBursts::4 52 +system.mem_ctrls.perBankWrBursts::5 48 +system.mem_ctrls.perBankWrBursts::6 38 +system.mem_ctrls.perBankWrBursts::7 60 +system.mem_ctrls.perBankWrBursts::8 28 +system.mem_ctrls.perBankWrBursts::9 130 +system.mem_ctrls.perBankWrBursts::10 123 +system.mem_ctrls.perBankWrBursts::11 24 +system.mem_ctrls.perBankWrBursts::12 2 +system.mem_ctrls.perBankWrBursts::13 31 +system.mem_ctrls.perBankWrBursts::14 8 +system.mem_ctrls.perBankWrBursts::15 37 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 91773 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1377 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1373 +system.mem_ctrls.rdQLenPdf::0 647 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 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+system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% +system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% +system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% +system.mem_ctrls.bytesPerActivate::total 263 +system.mem_ctrls.rdPerTurnAround::samples 40 +system.mem_ctrls.rdPerTurnAround::mean 16.100000 +system.mem_ctrls.rdPerTurnAround::gmean 15.846587 +system.mem_ctrls.rdPerTurnAround::stdev 3.484765 +system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% +system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% +system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% +system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% +system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% +system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% +system.mem_ctrls.rdPerTurnAround::total 40 +system.mem_ctrls.wrPerTurnAround::samples 40 +system.mem_ctrls.wrPerTurnAround::mean 16.300000 +system.mem_ctrls.wrPerTurnAround::gmean 16.281263 +system.mem_ctrls.wrPerTurnAround::stdev 0.822753 +system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% +system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% +system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% +system.mem_ctrls.wrPerTurnAround::total 40 +system.mem_ctrls.totQLat 12721 +system.mem_ctrls.totMemAccLat 25014 +system.mem_ctrls.totBusLat 3235 +system.mem_ctrls.avgQLat 19.66 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 38.66 +system.mem_ctrls.avgRdBW 450.78 +system.mem_ctrls.avgWrBW 454.26 +system.mem_ctrls.avgRdBWSys 959.38 +system.mem_ctrls.avgWrBWSys 956.60 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 7.07 +system.mem_ctrls.busUtilRead 3.52 +system.mem_ctrls.busUtilWrite 3.55 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.84 +system.mem_ctrls.readRowHits 435 +system.mem_ctrls.writeRowHits 591 +system.mem_ctrls.readRowHitRate 67.23 +system.mem_ctrls.writeRowHitRate 88.08 +system.mem_ctrls.avgGap 33.37 +system.mem_ctrls.pageHitRate 77.85 +system.mem_ctrls_0.actEnergy 664020 +system.mem_ctrls_0.preEnergy 340032 +system.mem_ctrls_0.readEnergy 3175872 +system.mem_ctrls_0.writeEnergy 2246688 +system.mem_ctrls_0.refreshEnergy 7375680.000000 +system.mem_ctrls_0.actBackEnergy 10273224 +system.mem_ctrls_0.preBackEnergy 269568 +system.mem_ctrls_0.actPowerDownEnergy 25208136 +system.mem_ctrls_0.prePowerDownEnergy 4818816 +system.mem_ctrls_0.selfRefreshEnergy 743760.000000 +system.mem_ctrls_0.totalEnergy 55115796 +system.mem_ctrls_0.averagePower 600.004311 +system.mem_ctrls_0.totalIdleTime 68393 +system.mem_ctrls_0.memoryStateTime::IDLE 346 +system.mem_ctrls_0.memoryStateTime::REF 3126 +system.mem_ctrls_0.memoryStateTime::SREF 798 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 +system.mem_ctrls_0.memoryStateTime::ACT 19759 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 +system.mem_ctrls_1.actEnergy 1285200 +system.mem_ctrls_1.preEnergy 676200 +system.mem_ctrls_1.readEnergy 4215456 +system.mem_ctrls_1.writeEnergy 3198816 +system.mem_ctrls_1.refreshEnergy 6761040.000000 +system.mem_ctrls_1.actBackEnergy 9576912 +system.mem_ctrls_1.preBackEnergy 183552 +system.mem_ctrls_1.actPowerDownEnergy 28147512 +system.mem_ctrls_1.prePowerDownEnergy 3322368 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 57367056 +system.mem_ctrls_1.averagePower 624.512089 +system.mem_ctrls_1.totalIdleTime 70328 +system.mem_ctrls_1.memoryStateTime::IDLE 150 +system.mem_ctrls_1.memoryStateTime::REF 2866 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 +system.mem_ctrls_1.memoryStateTime::ACT 18464 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 +system.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.apic_clk_domain.clock 16 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 91859 +system.cpu.numCycles 91859 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 91859 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2750 +system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2750 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8852 +system.ruby.outstanding_req_hist_seqr::samples 8853 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8852 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8853 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8852 @@ -388,36 +388,36 @@ system.ruby.miss_latency_hist_seqr::stdev 33.880423 system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096364 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096375 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.percent_links_utilized 7.484297 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -427,13 +427,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers1.percent_links_utilized 7.484297 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 @@ -443,25 +443,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers2.percent_links_utilized 7.484297 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 @@ -471,7 +471,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11016 system.ruby.network.routers2.msg_bytes.Data::2 98856 system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.msg_count.Control 4131 system.ruby.network.msg_count.Data 4119 system.ruby.network.msg_count.Response_Data 4131 @@ -480,7 +480,7 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.throttle0.link_utilization 7.493006 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -511,16 +511,16 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 1377 +system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1377 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1373 +system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1373 system.ruby.LD.latency_hist_seqr::bucket_size 32 system.ruby.LD.latency_hist_seqr::max_bucket 319 system.ruby.LD.latency_hist_seqr::samples 1045 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index bc04df7fd..1bbdae21e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 17523a325..30d3fbf05 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18567 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87155 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 30886500 because target called exit() +Exiting @ tick 31247500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b6ef5972c..e9a5f137e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,501 +1,501 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31247500 # Number of ticks simulated -final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377585 # Simulator instruction rate (inst/s) -host_op_rate 682900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2185869298 # Simulator tick rate (ticks/s) -host_mem_usage 268708 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 23104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 62495 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13956 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits -system.cpu.icache.overall_hits::total 6636 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses -system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.8 # Layer utilization (%) +sim_seconds 0.000031 +sim_ticks 31247500 +final_tick 31247500 +sim_freq 1000000000000 +host_inst_rate 194718 +host_op_rate 352470 +host_tick_rate 1129073998 +host_mem_usage 278812 +host_seconds 0.03 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 +system.physmem.bytes_read::cpu.inst 14528 +system.physmem.bytes_read::cpu.data 8576 +system.physmem.bytes_read::total 23104 +system.physmem.bytes_inst_read::cpu.inst 14528 +system.physmem.bytes_inst_read::total 14528 +system.physmem.num_reads::cpu.inst 227 +system.physmem.num_reads::cpu.data 134 +system.physmem.num_reads::total 361 +system.physmem.bw_read::cpu.inst 464933195 +system.physmem.bw_read::cpu.data 274453956 +system.physmem.bw_read::total 739387151 +system.physmem.bw_inst_read::cpu.inst 464933195 +system.physmem.bw_inst_read::total 464933195 +system.physmem.bw_total::cpu.inst 464933195 +system.physmem.bw_total::cpu.data 274453956 +system.physmem.bw_total::total 739387151 +system.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 31247500 +system.cpu.numCycles 62495 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 62495 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% 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+system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 +system.membus.trans_dist::ReadResp 282 +system.membus.trans_dist::ReadExReq 79 +system.membus.trans_dist::ReadExResp 79 +system.membus.trans_dist::ReadSharedReq 282 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 +system.membus.pkt_count::total 722 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 +system.membus.pkt_size::total 23104 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 361 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 361 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 361 +system.membus.reqLayer0.occupancy 361500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 1805000 +system.membus.respLayer1.utilization 5.8 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini index 5c4d73bb2..d465f3325 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini @@ -739,7 +739,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/h gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout pgid=100 pid=100 @@ -763,7 +763,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/h gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout pgid=100 pid=101 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index 98b12d0fa..45d42fd47 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 29 2017 21:35:16 -gem5 started Mar 29 2017 21:35:26 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87431 +gem5 compiled Mar 29 2017 21:52:42 +gem5 started Mar 29 2017 21:52:53 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 118268 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt Global frequency set at 1000000000000 ticks per second Hello world! Hello world! -Exiting @ tick 27117500 because target called exit() +Exiting @ tick 27117500 because exiting with last active thread context diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index ed0c77d41..1efa6d783 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 sim_ticks 27117500 final_tick 27117500 sim_freq 1000000000000 -host_inst_rate 132500 -host_op_rate 132484 -host_tick_rate 281303428 -host_mem_usage 265748 -host_seconds 0.10 +host_inst_rate 121145 +host_op_rate 121128 +host_tick_rate 257188425 +host_mem_usage 265776 +host_seconds 0.11 sim_insts 12770 sim_ops 12770 system.voltage_domain.voltage 1 @@ -755,7 +755,7 @@ system.cpu.cpi_total 4.247142 system.cpu.ipc::0 0.117726 system.cpu.ipc::1 0.117726 system.cpu.ipc_total 0.235452 -system.cpu.int_regfile_reads 23898 +system.cpu.int_regfile_reads 23899 system.cpu.int_regfile_writes 13306 system.cpu.fp_regfile_reads 16 system.cpu.fp_regfile_writes 4 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 7685aa1bd..4fcd776f1 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +139,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -715,7 +716,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -724,14 +725,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 7b48b6ce0..d5dd8e395 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:44:12 -gem5 started Nov 29 2016 18:44:33 -gem5 executing on zizzer, pid 58827 -command line: /z/powerjg/gem5-upstream/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:39 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64867 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 29908500 because target called exit() +Exiting @ tick 29673500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d8bf75e3e..c16641d08 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,990 +1,990 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29673500 # Number of ticks simulated -final_tick 29673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97740 # Simulator instruction rate (inst/s) -host_op_rate 97731 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 200871294 # Simulator tick rate (ticks/s) -host_mem_usage 251556 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -sim_insts 14436 # Number of instructions simulated -sim_ops 14436 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 782920788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317050567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1099971355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 782920788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 782920788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 782920788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317050567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1099971355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 511 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 104 # Per bank write bursts -system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 54 # Per bank write bursts -system.physmem.perBankRdBursts::3 28 # Per bank write bursts -system.physmem.perBankRdBursts::4 22 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 38 # Per bank write bursts -system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 4 # Per bank write bursts -system.physmem.perBankRdBursts::10 2 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 57 # Per bank write bursts -system.physmem.perBankRdBursts::13 31 # Per bank write bursts -system.physmem.perBankRdBursts::14 63 # Per bank write bursts -system.physmem.perBankRdBursts::15 41 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29642000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 511 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.025641 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.718123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.605052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 6610250 # Total ticks spent queuing -system.physmem.totMemAccLat 16191500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12935.91 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31685.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1102.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1102.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.61 # Data bus utilization in percentage -system.physmem.busUtilRead 8.61 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 422 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 58007.83 # Average gap between requests -system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 364140 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2184840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3606960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9847320 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 18086550 # Total energy per rank (pJ) -system.physmem_0.averagePower 609.513459 # Core power per rank (mW) -system.physmem_0.totalIdleTime 21469250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7251250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 21598000 # Time in different power states -system.physmem_1.actEnergy 271320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2504580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 86400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10184760 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 622560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17098680 # Total energy per rank (pJ) -system.physmem_1.averagePower 576.222419 # Core power per rank (mW) -system.physmem_1.totalIdleTime 23952750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1619750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4797750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22333000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11901 # Number of BP lookups -system.cpu.branchPred.condPredicted 7287 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1354 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 685 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9352 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1949 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7403 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 793 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29673500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59348 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15163 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 55604 # Number of instructions fetch has processed -system.cpu.fetch.Branches 11901 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2634 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2905 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 12 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1168 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7191 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 701 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 35180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.580557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.839184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22867 65.00% 65.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4490 12.76% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 508 1.44% 79.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 450 1.28% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.16% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 731 2.08% 84.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 296 0.84% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 343 0.97% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4734 13.46% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.200529 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.936914 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12094 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13233 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7639 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 762 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1452 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 39805 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1452 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12828 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9904 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7640 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1543 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 35279 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 30611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 63420 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 52396 # Number of integer rename lookups -system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16792 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 761 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 767 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4154 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 27854 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 724 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 24627 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14142 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10452 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.700028 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.493682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35180 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51 17.59% 69.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 30.34% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18085 73.44% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4096 16.63% 90.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2446 9.93% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 24627 # Type of FU issued -system.cpu.iq.rate 0.414959 # Inst issue rate -system.cpu.iq.fu_busy_cnt 290 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011776 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 84846 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42748 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22066 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 24917 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2166 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1355 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1452 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1841 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 30085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 231 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 209 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23080 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3816 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1547 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1507 # number of nop insts executed -system.cpu.iew.exec_refs 6070 # number of memory reference insts executed -system.cpu.iew.exec_branches 4884 # Number of branches executed -system.cpu.iew.exec_stores 2254 # Number of stores executed -system.cpu.iew.exec_rate 0.388893 # Inst execution rate -system.cpu.iew.wb_sent 22529 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22066 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10367 # num instructions producing a value -system.cpu.iew.wb_consumers 13651 # num instructions consuming a value -system.cpu.iew.wb_rate 0.371807 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.759432 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14855 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1354 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32262 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.469965 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.260994 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25609 79.38% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3577 11.09% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1157 3.59% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 603 1.87% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 332 1.03% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 298 0.92% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 393 1.22% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 58 0.18% 99.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 235 0.73% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32262 # Number of insts commited each cycle -system.cpu.commit.committedInsts 15162 # Number of instructions committed -system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 3673 # Number of memory references committed -system.cpu.commit.loads 2225 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 3358 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 12174 # Number of committed integer instructions. -system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 235 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 61221 # The number of ROB reads -system.cpu.rob.rob_writes 63021 # The number of ROB writes -system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24168 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 14436 # Number of Instructions Simulated -system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 4.111111 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.111111 # CPI: Total CPI of All Threads -system.cpu.ipc 0.243243 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.243243 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36173 # number of integer regfile reads -system.cpu.int_regfile_writes 20126 # number of integer regfile writes -system.cpu.misc_regfile_reads 7956 # number of misc regfile reads -system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.931439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4528 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.013699 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.931439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024153 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024153 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10292 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10292 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4522 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4522 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4522 # number of overall hits -system.cpu.dcache.overall_hits::total 4522 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 545 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 545 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 545 # number of overall misses -system.cpu.dcache.overall_misses::total 545 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10734500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10734500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29028485 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29028485 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39762985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39762985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39762985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39762985 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5067 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5067 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5067 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5067 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037517 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037517 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.107559 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.107559 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.107559 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.107559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78930.147059 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78930.147059 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70974.290954 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70974.290954 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72959.605505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72959.605505 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 397 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 397 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 397 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 397 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6906500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6906500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12986500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12986500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12986500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12986500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017931 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017931 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93538.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93538.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83210.843373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83210.843373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 202.053622 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6606 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.098630 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 202.053622 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.098659 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.098659 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 14747 # Number of tag accesses -system.cpu.icache.tags.data_accesses 14747 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6606 # number of overall hits -system.cpu.icache.overall_hits::total 6606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 585 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 585 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 585 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 585 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 585 # number of overall misses -system.cpu.icache.overall_misses::total 585 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45161000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45161000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45161000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45161000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7191 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77198.290598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77198.290598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77198.290598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77198.290598 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 220 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 220 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 220 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 220 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29981500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29981500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29981500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29981500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29981500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29981500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050758 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050758 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050758 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82141.095890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82141.095890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 300.398022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 201.414921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 98.983101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006147 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003021 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.009167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses -system.cpu.l2cache.overall_misses::total 511 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6781000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6781000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29411000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29411000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5985000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5985000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29411000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 42177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29411000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 42177000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81698.795181 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81698.795181 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81022.038567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81022.038567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92076.923077 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92076.923077 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82538.160470 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82538.160470 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426 # Transaction distribution -system.membus.trans_dist::ReadExReq 83 # Transaction distribution -system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 511 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2697250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.1 # Layer utilization (%) +sim_seconds 0.000030 +sim_ticks 29673500 +final_tick 29673500 +sim_freq 1000000000000 +host_inst_rate 61209 +host_op_rate 61203 +host_tick_rate 125793033 +host_mem_usage 263540 +host_seconds 0.24 +sim_insts 14436 +sim_ops 14436 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 +system.physmem.bytes_read::cpu.inst 23232 +system.physmem.bytes_read::cpu.data 9408 +system.physmem.bytes_read::total 32640 +system.physmem.bytes_inst_read::cpu.inst 23232 +system.physmem.bytes_inst_read::total 23232 +system.physmem.num_reads::cpu.inst 363 +system.physmem.num_reads::cpu.data 147 +system.physmem.num_reads::total 510 +system.physmem.bw_read::cpu.inst 782920788 +system.physmem.bw_read::cpu.data 317050567 +system.physmem.bw_read::total 1099971355 +system.physmem.bw_inst_read::cpu.inst 782920788 +system.physmem.bw_inst_read::total 782920788 +system.physmem.bw_total::cpu.inst 782920788 +system.physmem.bw_total::cpu.data 317050567 +system.physmem.bw_total::total 1099971355 +system.physmem.readReqs 511 +system.physmem.writeReqs 0 +system.physmem.readBursts 511 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 32704 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 32704 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 104 +system.physmem.perBankRdBursts::1 28 +system.physmem.perBankRdBursts::2 54 +system.physmem.perBankRdBursts::3 28 +system.physmem.perBankRdBursts::4 22 +system.physmem.perBankRdBursts::5 0 +system.physmem.perBankRdBursts::6 32 +system.physmem.perBankRdBursts::7 38 +system.physmem.perBankRdBursts::8 7 +system.physmem.perBankRdBursts::9 4 +system.physmem.perBankRdBursts::10 2 +system.physmem.perBankRdBursts::11 0 +system.physmem.perBankRdBursts::12 57 +system.physmem.perBankRdBursts::13 31 +system.physmem.perBankRdBursts::14 63 +system.physmem.perBankRdBursts::15 41 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 29642000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 511 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 282 +system.physmem.rdQLenPdf::1 153 +system.physmem.rdQLenPdf::2 58 +system.physmem.rdQLenPdf::3 14 +system.physmem.rdQLenPdf::4 4 +system.physmem.rdQLenPdf::5 0 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 78 +system.physmem.bytesPerActivate::mean 393.025641 +system.physmem.bytesPerActivate::gmean 252.718123 +system.physmem.bytesPerActivate::stdev 347.605052 +system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% +system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% +system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% +system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% +system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% +system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% +system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% +system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% +system.physmem.bytesPerActivate::total 78 +system.physmem.totQLat 6610250 +system.physmem.totMemAccLat 16191500 +system.physmem.totBusLat 2555000 +system.physmem.avgQLat 12935.91 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 31685.91 +system.physmem.avgRdBW 1102.13 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 1102.13 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 8.61 +system.physmem.busUtilRead 8.61 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.64 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 422 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 82.58 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 58007.83 +system.physmem.pageHitRate 82.58 +system.physmem_0.actEnergy 364140 +system.physmem_0.preEnergy 174570 +system.physmem_0.readEnergy 2184840 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 1843920.000000 +system.physmem_0.actBackEnergy 3606960 +system.physmem_0.preBackEnergy 63360 +system.physmem_0.actPowerDownEnergy 9847320 +system.physmem_0.prePowerDownEnergy 1440 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 18086550 +system.physmem_0.averagePower 609.513459 +system.physmem_0.totalIdleTime 21469250 +system.physmem_0.memoryStateTime::IDLE 40500 +system.physmem_0.memoryStateTime::REF 780000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 3750 +system.physmem_0.memoryStateTime::ACT 7251250 +system.physmem_0.memoryStateTime::ACT_PDN 21598000 +system.physmem_1.actEnergy 271320 +system.physmem_1.preEnergy 121440 +system.physmem_1.readEnergy 1463700 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 1843920.000000 +system.physmem_1.actBackEnergy 2504580 +system.physmem_1.preBackEnergy 86400 +system.physmem_1.actPowerDownEnergy 10184760 +system.physmem_1.prePowerDownEnergy 622560 +system.physmem_1.selfRefreshEnergy 0 +system.physmem_1.totalEnergy 17098680 +system.physmem_1.averagePower 576.222419 +system.physmem_1.totalIdleTime 23952750 +system.physmem_1.memoryStateTime::IDLE 143000 +system.physmem_1.memoryStateTime::REF 780000 +system.physmem_1.memoryStateTime::SREF 0 +system.physmem_1.memoryStateTime::PRE_PDN 1619750 +system.physmem_1.memoryStateTime::ACT 4797750 +system.physmem_1.memoryStateTime::ACT_PDN 22333000 +system.pwrStateResidencyTicks::UNDEFINED 29673500 +system.cpu.branchPred.lookups 11901 +system.cpu.branchPred.condPredicted 7287 +system.cpu.branchPred.condIncorrect 1354 +system.cpu.branchPred.BTBLookups 9352 +system.cpu.branchPred.BTBHits 0 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 0.000000 +system.cpu.branchPred.usedRAS 685 +system.cpu.branchPred.RASInCorrect 166 +system.cpu.branchPred.indirectLookups 9352 +system.cpu.branchPred.indirectHits 1949 +system.cpu.branchPred.indirectMisses 7403 +system.cpu.branchPredindirectMispredicted 793 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 18 +system.cpu.pwrStateResidencyTicks::ON 29673500 +system.cpu.numCycles 59348 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 15163 +system.cpu.fetch.Insts 55604 +system.cpu.fetch.Branches 11901 +system.cpu.fetch.predictedBranches 2634 +system.cpu.fetch.Cycles 17364 +system.cpu.fetch.SquashCycles 2904 +system.cpu.fetch.TlbCycles 12 +system.cpu.fetch.MiscStallCycles 9 +system.cpu.fetch.PendingTrapStallCycles 1168 +system.cpu.fetch.IcacheWaitRetryStallCycles 12 +system.cpu.fetch.CacheLines 7191 +system.cpu.fetch.IcacheSquashes 701 +system.cpu.fetch.ItlbSquashes 1 +system.cpu.fetch.rateDist::samples 35180 +system.cpu.fetch.rateDist::mean 1.580557 +system.cpu.fetch.rateDist::stdev 2.839184 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 22867 65.00% 65.00% +system.cpu.fetch.rateDist::1 4490 12.76% 77.76% +system.cpu.fetch.rateDist::2 508 1.44% 79.21% +system.cpu.fetch.rateDist::3 450 1.28% 80.49% +system.cpu.fetch.rateDist::4 761 2.16% 82.65% +system.cpu.fetch.rateDist::5 731 2.08% 84.73% +system.cpu.fetch.rateDist::6 296 0.84% 85.57% +system.cpu.fetch.rateDist::7 343 0.97% 86.54% +system.cpu.fetch.rateDist::8 4734 13.46% 100.00% +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 8 +system.cpu.fetch.rateDist::total 35180 +system.cpu.fetch.branchRate 0.200529 +system.cpu.fetch.rate 0.936914 +system.cpu.decode.IdleCycles 12094 +system.cpu.decode.BlockedCycles 13233 +system.cpu.decode.RunCycles 7639 +system.cpu.decode.UnblockCycles 762 +system.cpu.decode.SquashCycles 1452 +system.cpu.decode.DecodedInsts 39805 +system.cpu.rename.SquashCycles 1452 +system.cpu.rename.IdleCycles 12828 +system.cpu.rename.BlockCycles 1813 +system.cpu.rename.serializeStallCycles 9904 +system.cpu.rename.RunCycles 7640 +system.cpu.rename.UnblockCycles 1543 +system.cpu.rename.RenamedInsts 35279 +system.cpu.rename.IQFullEvents 9 +system.cpu.rename.SQFullEvents 1128 +system.cpu.rename.RenamedOperands 30611 +system.cpu.rename.RenameLookups 63420 +system.cpu.rename.int_rename_lookups 52396 +system.cpu.rename.CommittedMaps 13819 +system.cpu.rename.UndoneMaps 16792 +system.cpu.rename.serializingInsts 761 +system.cpu.rename.tempSerializingInsts 767 +system.cpu.rename.skidInsts 4154 +system.cpu.memDep0.insertedLoads 4391 +system.cpu.memDep0.insertedStores 2803 +system.cpu.memDep0.conflictingLoads 14 +system.cpu.memDep0.conflictingStores 8 +system.cpu.iq.iqInstsAdded 27854 +system.cpu.iq.iqNonSpecInstsAdded 724 +system.cpu.iq.iqInstsIssued 24627 +system.cpu.iq.iqSquashedInstsIssued 122 +system.cpu.iq.iqSquashedInstsExamined 14141 +system.cpu.iq.iqSquashedOperandsExamined 10452 +system.cpu.iq.iqSquashedNonSpecRemoved 249 +system.cpu.iq.issued_per_cycle::samples 35180 +system.cpu.iq.issued_per_cycle::mean 0.700028 +system.cpu.iq.issued_per_cycle::stdev 1.493682 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% +system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% +system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% +system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% +system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% +system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% +system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% +system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% +system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 8 +system.cpu.iq.issued_per_cycle::total 35180 +system.cpu.iq.fu_full::No_OpClass 0 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1020 +system.membus.pkt_count::total 1020 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 +system.membus.pkt_size::total 32576 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 511 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 511 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 511 +system.membus.reqLayer0.occupancy 623500 +system.membus.reqLayer0.utilization 2.1 +system.membus.respLayer1.occupancy 2697250 +system.membus.respLayer1.utilization 9.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 28ad26872..297f86454 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index da1b76716..bf2b3f4bd 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38677 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64897 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 7612000 because target called exit() +Exiting @ tick 7612000 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 008914f75..322c3c70b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 7612000 # Number of ticks simulated -final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 446852 # Simulator instruction rate (inst/s) -host_op_rate 446721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224213840 # Simulator tick rate (ticks/s) -host_mem_usage 239476 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory -system.physmem.bytes_read::total 72170 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory -system.physmem.bytes_written::total 9042 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory -system.physmem.num_other::total 6 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 7612000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 15225 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13819 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 17432 # Transaction distribution -system.membus.trans_dist::ReadResp 17432 # Transaction distribution -system.membus.trans_dist::WriteReq 1442 # Transaction distribution -system.membus.trans_dist::WriteResp 1442 # Transaction distribution -system.membus.trans_dist::SwapReq 6 # Transaction distribution -system.membus.trans_dist::SwapResp 6 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18880 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18880 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18880 # Request fanout histogram +sim_seconds 0.000008 +sim_ticks 7612000 +final_tick 7612000 +sim_freq 1000000000000 +host_inst_rate 370319 +host_op_rate 370098 +host_tick_rate 185717309 +host_mem_usage 251756 +host_seconds 0.04 +sim_insts 15162 +sim_ops 15162 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 +system.physmem.bytes_read::cpu.inst 60828 +system.physmem.bytes_read::cpu.data 11342 +system.physmem.bytes_read::total 72170 +system.physmem.bytes_inst_read::cpu.inst 60828 +system.physmem.bytes_inst_read::total 60828 +system.physmem.bytes_written::cpu.data 9042 +system.physmem.bytes_written::total 9042 +system.physmem.num_reads::cpu.inst 15207 +system.physmem.num_reads::cpu.data 2225 +system.physmem.num_reads::total 17432 +system.physmem.num_writes::cpu.data 1442 +system.physmem.num_writes::total 1442 +system.physmem.num_other::cpu.data 6 +system.physmem.num_other::total 6 +system.physmem.bw_read::cpu.inst 7991066737 +system.physmem.bw_read::cpu.data 1490015765 +system.physmem.bw_read::total 9481082501 +system.physmem.bw_inst_read::cpu.inst 7991066737 +system.physmem.bw_inst_read::total 7991066737 +system.physmem.bw_write::cpu.data 1187861272 +system.physmem.bw_write::total 1187861272 +system.physmem.bw_total::cpu.inst 7991066737 +system.physmem.bw_total::cpu.data 2677877036 +system.physmem.bw_total::total 10668943773 +system.pwrStateResidencyTicks::UNDEFINED 7612000 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 18 +system.cpu.pwrStateResidencyTicks::ON 7612000 +system.cpu.numCycles 15225 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 15162 +system.cpu.committedOps 15162 +system.cpu.num_int_alu_accesses 12219 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 385 +system.cpu.num_conditional_control_insts 2434 +system.cpu.num_int_insts 12219 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 29037 +system.cpu.num_int_register_writes 13819 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 3683 +system.cpu.num_load_insts 2231 +system.cpu.num_store_insts 1452 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 15225 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 3363 +system.cpu.op_class::No_OpClass 726 4.77% 4.77% +system.cpu.op_class::IntAlu 10798 71.01% 75.78% +system.cpu.op_class::IntMult 0 0.00% 75.78% +system.cpu.op_class::IntDiv 0 0.00% 75.78% +system.cpu.op_class::FloatAdd 0 0.00% 75.78% +system.cpu.op_class::FloatCmp 0 0.00% 75.78% +system.cpu.op_class::FloatCvt 0 0.00% 75.78% +system.cpu.op_class::FloatMult 0 0.00% 75.78% +system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% +system.cpu.op_class::FloatDiv 0 0.00% 75.78% +system.cpu.op_class::FloatMisc 0 0.00% 75.78% +system.cpu.op_class::FloatSqrt 0 0.00% 75.78% +system.cpu.op_class::SimdAdd 0 0.00% 75.78% +system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% +system.cpu.op_class::SimdAlu 0 0.00% 75.78% +system.cpu.op_class::SimdCmp 0 0.00% 75.78% +system.cpu.op_class::SimdCvt 0 0.00% 75.78% +system.cpu.op_class::SimdMisc 0 0.00% 75.78% +system.cpu.op_class::SimdMult 0 0.00% 75.78% +system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% +system.cpu.op_class::SimdShift 0 0.00% 75.78% +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% +system.cpu.op_class::SimdSqrt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% +system.cpu.op_class::MemRead 2231 14.67% 90.45% +system.cpu.op_class::MemWrite 1452 9.55% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 15207 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 +system.membus.trans_dist::ReadReq 17432 +system.membus.trans_dist::ReadResp 17432 +system.membus.trans_dist::WriteReq 1442 +system.membus.trans_dist::WriteResp 1442 +system.membus.trans_dist::SwapReq 6 +system.membus.trans_dist::SwapResp 6 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 +system.membus.pkt_count::total 37760 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 +system.membus.pkt_size::total 81270 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 18880 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 18880 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 18880 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index 76eaa1c9f..d56f74081 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index aa11b3776..65544f70a 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:38 -gem5 executing on e108600-lin, pid 38722 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:42 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64930 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 44282500 because target called exit() +Exiting @ tick 44698500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 08009f0ca..98ef53418 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,497 +1,497 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000045 # Number of seconds simulated -sim_ticks 44698500 # Number of ticks simulated -final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357665 # Simulator instruction rate (inst/s) -host_op_rate 357507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053539740 # Simulator tick rate (ticks/s) -host_mem_usage 250236 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 89397 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13818 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits -system.cpu.dcache.overall_hits::total 3529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits -system.cpu.icache.overall_hits::total 14928 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses -system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 331 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 416 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.7 # Layer utilization (%) +sim_seconds 0.000045 +sim_ticks 44698500 +final_tick 44698500 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+system.cpu.toL2Bus.reqLayer0.occupancy 209000 +system.cpu.toL2Bus.reqLayer0.utilization 0.5 +system.cpu.toL2Bus.respLayer0.occupancy 420000 +system.cpu.toL2Bus.respLayer0.utilization 0.9 +system.cpu.toL2Bus.respLayer1.occupancy 207000 +system.cpu.toL2Bus.respLayer1.utilization 0.5 +system.membus.snoop_filter.tot_requests 416 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 +system.membus.trans_dist::ReadResp 331 +system.membus.trans_dist::ReadExReq 85 +system.membus.trans_dist::ReadExResp 85 +system.membus.trans_dist::ReadSharedReq 331 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 +system.membus.pkt_count::total 832 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 +system.membus.pkt_size::total 26624 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 416 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 416 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 416 +system.membus.reqLayer0.occupancy 416500 +system.membus.reqLayer0.utilization 0.9 +system.membus.respLayer1.occupancy 2080000 +system.membus.respLayer1.utilization 4.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini index 2d26791e9..34c898798 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -93,6 +93,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -166,8 +167,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -178,8 +177,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/arm/linux/hello cwd= drivers= @@ -252,10 +249,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout index 40266a5d8..01bb29eda 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:05:23 -gem5 executing on e108600-lin, pid 17594 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:05:51 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55329 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 372284000 because target called exit() +Exiting @ tick 372284000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index d96e2fe55..bf625223f 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,510 +1,510 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000372 # Number of seconds simulated -sim_ticks 372284000 # Number of ticks simulated -final_tick 372284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264702 # Simulator instruction rate (inst/s) -host_op_rate 305997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19731375693 # Simulator tick rate (ticks/s) -host_mem_usage 650740 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 4988 # Number of instructions simulated -sim_ops 5770 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1061 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 54012528 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 12549559 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 66562087 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 54012528 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 54012528 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9927905 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9927905 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 54012528 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 22477463 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 76489992 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 6089 # Number of read requests accepted -system.mem_ctrl.writeReqs 936 # Number of write requests accepted -system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 855 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 724 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 364 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 505 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 303 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 487 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 192 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 422 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 80 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 372207000 # Total gap between requests -system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) 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-system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 514 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 749.322957 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 608.037375 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 344.826867 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 514 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 57609500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 169903250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9619.22 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28369.22 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1029.58 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 11.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 66.57 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.93 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.13 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.04 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5473 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.38 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 52983.20 # Average gap between requests -system.mem_ctrl.pageHitRate 91.19 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2727480 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1438305 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 35364420 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 64999380 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1619520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 98643060 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 3533760 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 237214005 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 637.183891 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 225396250 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 954000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 133713750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 # Time in different power states -system.mem_ctrl_1.actEnergy 971040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 512325 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7389900 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 334080 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 27658800.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 18607080 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 791520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 128152530 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 7837920 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 7265340 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 199520535 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 535.934929 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 328663750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 770000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11706000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 27971000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 30385000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 372284000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 372284 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4988 # Number of instructions committed -system.cpu.committedOps 5770 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 215 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls -system.cpu.num_int_insts 4977 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 8049 # number of times the integer registers were read -system.cpu.num_int_register_writes 2992 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written -system.cpu.num_mem_refs 2035 # number of memory refs -system.cpu.num_load_insts 1085 # Number of load instructions -system.cpu.num_store_insts 950 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 372283.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1107 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5831 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6078 # Transaction distribution -system.membus.trans_dist::ReadResp 6088 # Transaction distribution -system.membus.trans_dist::WriteReq 925 # Transaction distribution -system.membus.trans_dist::WriteResp 925 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14049 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28476 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7025 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7025 # Request fanout histogram -system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 11413250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3327250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +sim_seconds 0.000372 +sim_ticks 372284000 +final_tick 372284000 +sim_freq 1000000000000 +host_inst_rate 111411 +host_op_rate 128815 +host_tick_rate 8307715104 +host_mem_usage 662496 +host_seconds 0.05 +sim_insts 4988 +sim_ops 5770 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 +system.mem_ctrl.bytes_read::cpu.inst 20108 +system.mem_ctrl.bytes_read::cpu.data 4672 +system.mem_ctrl.bytes_read::total 24780 +system.mem_ctrl.bytes_inst_read::cpu.inst 20108 +system.mem_ctrl.bytes_inst_read::total 20108 +system.mem_ctrl.bytes_written::cpu.data 3696 +system.mem_ctrl.bytes_written::total 3696 +system.mem_ctrl.num_reads::cpu.inst 5027 +system.mem_ctrl.num_reads::cpu.data 1061 +system.mem_ctrl.num_reads::total 6088 +system.mem_ctrl.num_writes::cpu.data 936 +system.mem_ctrl.num_writes::total 936 +system.mem_ctrl.bw_read::cpu.inst 54012528 +system.mem_ctrl.bw_read::cpu.data 12549559 +system.mem_ctrl.bw_read::total 66562087 +system.mem_ctrl.bw_inst_read::cpu.inst 54012528 +system.mem_ctrl.bw_inst_read::total 54012528 +system.mem_ctrl.bw_write::cpu.data 9927905 +system.mem_ctrl.bw_write::total 9927905 +system.mem_ctrl.bw_total::cpu.inst 54012528 +system.mem_ctrl.bw_total::cpu.data 22477463 +system.mem_ctrl.bw_total::total 76489992 +system.mem_ctrl.readReqs 6089 +system.mem_ctrl.writeReqs 936 +system.mem_ctrl.readBursts 6089 +system.mem_ctrl.writeBursts 936 +system.mem_ctrl.bytesReadDRAM 383296 +system.mem_ctrl.bytesReadWrQ 6400 +system.mem_ctrl.bytesWritten 4096 +system.mem_ctrl.bytesReadSys 24784 +system.mem_ctrl.bytesWrittenSys 3696 +system.mem_ctrl.servicedByWrQ 100 +system.mem_ctrl.mergedWrBursts 855 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 911 +system.mem_ctrl.perBankRdBursts::1 1454 +system.mem_ctrl.perBankRdBursts::2 724 +system.mem_ctrl.perBankRdBursts::3 364 +system.mem_ctrl.perBankRdBursts::4 505 +system.mem_ctrl.perBankRdBursts::5 303 +system.mem_ctrl.perBankRdBursts::6 487 +system.mem_ctrl.perBankRdBursts::7 206 +system.mem_ctrl.perBankRdBursts::8 42 +system.mem_ctrl.perBankRdBursts::9 155 +system.mem_ctrl.perBankRdBursts::10 192 +system.mem_ctrl.perBankRdBursts::11 422 +system.mem_ctrl.perBankRdBursts::12 108 +system.mem_ctrl.perBankRdBursts::13 36 +system.mem_ctrl.perBankRdBursts::14 0 +system.mem_ctrl.perBankRdBursts::15 80 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 0 +system.mem_ctrl.perBankWrBursts::10 13 +system.mem_ctrl.perBankWrBursts::11 46 +system.mem_ctrl.perBankWrBursts::12 5 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 372207000 +system.mem_ctrl.readPktSize::0 70 +system.mem_ctrl.readPktSize::1 1 +system.mem_ctrl.readPktSize::2 5858 +system.mem_ctrl.readPktSize::3 160 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 16 +system.mem_ctrl.writePktSize::1 0 +system.mem_ctrl.writePktSize::2 920 +system.mem_ctrl.writePktSize::3 0 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 5980 +system.mem_ctrl.rdQLenPdf::1 9 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 4 +system.mem_ctrl.wrQLenPdf::18 4 +system.mem_ctrl.wrQLenPdf::19 4 +system.mem_ctrl.wrQLenPdf::20 4 +system.mem_ctrl.wrQLenPdf::21 4 +system.mem_ctrl.wrQLenPdf::22 4 +system.mem_ctrl.wrQLenPdf::23 4 +system.mem_ctrl.wrQLenPdf::24 4 +system.mem_ctrl.wrQLenPdf::25 4 +system.mem_ctrl.wrQLenPdf::26 4 +system.mem_ctrl.wrQLenPdf::27 4 +system.mem_ctrl.wrQLenPdf::28 4 +system.mem_ctrl.wrQLenPdf::29 4 +system.mem_ctrl.wrQLenPdf::30 4 +system.mem_ctrl.wrQLenPdf::31 4 +system.mem_ctrl.wrQLenPdf::32 4 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 514 +system.mem_ctrl.bytesPerActivate::mean 749.322957 +system.mem_ctrl.bytesPerActivate::gmean 608.037375 +system.mem_ctrl.bytesPerActivate::stdev 344.826867 +system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% +system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% +system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% +system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% +system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% +system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% +system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% +system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% +system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% +system.mem_ctrl.bytesPerActivate::total 514 +system.mem_ctrl.rdPerTurnAround::samples 4 +system.mem_ctrl.rdPerTurnAround::mean 1490.500000 +system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 +system.mem_ctrl.rdPerTurnAround::stdev 606.712727 +system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% +system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% +system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% +system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% +system.mem_ctrl.rdPerTurnAround::total 4 +system.mem_ctrl.wrPerTurnAround::samples 4 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 4 +system.mem_ctrl.totQLat 57609500 +system.mem_ctrl.totMemAccLat 169903250 +system.mem_ctrl.totBusLat 29945000 +system.mem_ctrl.avgQLat 9619.22 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28369.22 +system.mem_ctrl.avgRdBW 1029.58 +system.mem_ctrl.avgWrBW 11.00 +system.mem_ctrl.avgRdBWSys 66.57 +system.mem_ctrl.avgWrBWSys 9.93 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.13 +system.mem_ctrl.busUtilRead 8.04 +system.mem_ctrl.busUtilWrite 0.09 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 24.94 +system.mem_ctrl.readRowHits 5473 +system.mem_ctrl.writeRowHits 62 +system.mem_ctrl.readRowHitRate 91.38 +system.mem_ctrl.writeRowHitRate 76.54 +system.mem_ctrl.avgGap 52983.20 +system.mem_ctrl.pageHitRate 91.19 +system.mem_ctrl_0.actEnergy 2727480 +system.mem_ctrl_0.preEnergy 1438305 +system.mem_ctrl_0.readEnergy 35364420 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 28888080.000000 +system.mem_ctrl_0.actBackEnergy 64999380 +system.mem_ctrl_0.preBackEnergy 1619520 +system.mem_ctrl_0.actPowerDownEnergy 98643060 +system.mem_ctrl_0.prePowerDownEnergy 3533760 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 237214005 +system.mem_ctrl_0.averagePower 637.183891 +system.mem_ctrl_0.totalIdleTime 225396250 +system.mem_ctrl_0.memoryStateTime::IDLE 954000 +system.mem_ctrl_0.memoryStateTime::REF 12220000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 +system.mem_ctrl_0.memoryStateTime::ACT 133713750 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 +system.mem_ctrl_1.actEnergy 971040 +system.mem_ctrl_1.preEnergy 512325 +system.mem_ctrl_1.readEnergy 7389900 +system.mem_ctrl_1.writeEnergy 334080 +system.mem_ctrl_1.refreshEnergy 27658800.000000 +system.mem_ctrl_1.actBackEnergy 18607080 +system.mem_ctrl_1.preBackEnergy 791520 +system.mem_ctrl_1.actPowerDownEnergy 128152530 +system.mem_ctrl_1.prePowerDownEnergy 7837920 +system.mem_ctrl_1.selfRefreshEnergy 7265340 +system.mem_ctrl_1.totalEnergy 199520535 +system.mem_ctrl_1.averagePower 535.934929 +system.mem_ctrl_1.totalIdleTime 328663750 +system.mem_ctrl_1.memoryStateTime::IDLE 770000 +system.mem_ctrl_1.memoryStateTime::REF 11706000 +system.mem_ctrl_1.memoryStateTime::SREF 27971000 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 +system.mem_ctrl_1.memoryStateTime::ACT 30385000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 +system.pwrStateResidencyTicks::UNDEFINED 372284000 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 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+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 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+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 13 +system.cpu.pwrStateResidencyTicks::ON 372284000 +system.cpu.numCycles 372284 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4988 +system.cpu.committedOps 5770 +system.cpu.num_int_alu_accesses 4977 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 215 +system.cpu.num_conditional_control_insts 800 +system.cpu.num_int_insts 4977 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 8049 +system.cpu.num_int_register_writes 2992 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 20681 +system.cpu.num_cc_register_writes 2647 +system.cpu.num_mem_refs 2035 +system.cpu.num_load_insts 1085 +system.cpu.num_store_insts 950 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 372284 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1107 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3789 64.98% 64.98% +system.cpu.op_class::IntMult 4 0.07% 65.05% +system.cpu.op_class::IntDiv 0 0.00% 65.05% +system.cpu.op_class::FloatAdd 0 0.00% 65.05% +system.cpu.op_class::FloatCmp 0 0.00% 65.05% +system.cpu.op_class::FloatCvt 0 0.00% 65.05% +system.cpu.op_class::FloatMult 0 0.00% 65.05% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% +system.cpu.op_class::FloatDiv 0 0.00% 65.05% +system.cpu.op_class::FloatMisc 0 0.00% 65.05% +system.cpu.op_class::FloatSqrt 0 0.00% 65.05% +system.cpu.op_class::SimdAdd 0 0.00% 65.05% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% +system.cpu.op_class::SimdAlu 0 0.00% 65.05% +system.cpu.op_class::SimdCmp 0 0.00% 65.05% +system.cpu.op_class::SimdCvt 0 0.00% 65.05% +system.cpu.op_class::SimdMisc 0 0.00% 65.05% +system.cpu.op_class::SimdMult 0 0.00% 65.05% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% +system.cpu.op_class::SimdShift 0 0.00% 65.05% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% +system.cpu.op_class::SimdSqrt 0 0.00% 65.05% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% +system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% +system.cpu.op_class::MemRead 1085 18.61% 83.71% +system.cpu.op_class::MemWrite 934 16.02% 99.73% +system.cpu.op_class::FloatMemRead 0 0.00% 99.73% +system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5831 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 +system.membus.trans_dist::ReadReq 6078 +system.membus.trans_dist::ReadResp 6088 +system.membus.trans_dist::WriteReq 925 +system.membus.trans_dist::WriteResp 925 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 +system.membus.pkt_count::total 14049 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 +system.membus.pkt_size::total 28476 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 7025 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 7025 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 7025 +system.membus.reqLayer0.occupancy 7961000 +system.membus.reqLayer0.utilization 2.1 +system.membus.respLayer0.occupancy 11413250 +system.membus.respLayer0.utilization 3.1 +system.membus.respLayer1.occupancy 3327250 +system.membus.respLayer1.utilization 0.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini index 733323a88..df4988eaf 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -93,6 +93,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -106,10 +107,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -123,6 +124,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -135,15 +137,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -202,10 +205,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -219,6 +222,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -231,15 +235,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -258,8 +263,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -270,8 +273,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -331,7 +332,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/arm/linux/hello cwd= drivers= @@ -344,10 +345,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -397,10 +399,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -414,6 +416,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -426,15 +429,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout index 7a7d67b77..00615c5ed 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:05:17 -gem5 executing on e108600-lin, pid 17589 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55755 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 52453000 because target called exit() +Exiting @ tick 52453000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 0bf6798da..67ec14819 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,846 +1,846 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000052 # Number of seconds simulated -sim_ticks 52453000 # Number of ticks simulated -final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 494492 # Simulator instruction rate (inst/s) -host_op_rate 571324 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5188174566 # Simulator tick rate (ticks/s) -host_mem_usage 654324 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4988 # Number of instructions simulated -sim_ops 5770 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 351 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 52348000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation -system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 149139.60 # Average gap between requests -system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states -system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 52453 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4988 # Number of instructions committed -system.cpu.committedOps 5770 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 215 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls -system.cpu.num_int_insts 4977 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 8049 # number of times the integer registers were read -system.cpu.num_int_register_writes 2992 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written -system.cpu.num_mem_refs 2035 # number of memory refs -system.cpu.num_load_insts 1085 # Number of load instructions -system.cpu.num_store_insts 950 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1107 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits -system.cpu.dcache.overall_hits::total 1833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits -system.cpu.icache.overall_hits::total 4779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses -system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 348 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 391 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram -system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 391 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use -system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3959 # Number of tag accesses -system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits -system.l2cache.demand_hits::total 40 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.l2cache.overall_hits::cpu.data 16 # number of overall hits -system.l2cache.overall_hits::total 40 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 225 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.l2cache.demand_misses::total 351 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 351 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 351 # Request fanout histogram -system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1866250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.6 # Layer utilization (%) +sim_seconds 0.000052 +sim_ticks 52453000 +final_tick 52453000 +sim_freq 1000000000000 +host_inst_rate 255460 +host_op_rate 295178 +host_tick_rate 2680706051 +host_mem_usage 666596 +host_seconds 0.02 +sim_insts 4988 +sim_ops 5770 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 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+system.membus.reqLayer0.utilization 0.7 +system.membus.respLayer0.occupancy 1866250 +system.membus.respLayer0.utilization 3.6 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini index d1ab85628..22ac65ead 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini @@ -91,6 +91,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -120,7 +121,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/sparc/linux/hello cwd= drivers= @@ -133,10 +134,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout index 4568a6760..4f2bfd587 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:47:16 -gem5 executing on e108600-lin, pid 17418 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:38 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64860 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 380341000 because target called exit() +Hello World!Exiting @ tick 380341000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 25ad41fa6..c3baff489 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -1,386 +1,386 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000380 # Number of seconds simulated -sim_ticks 380341000 # Number of ticks simulated -final_tick 380341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290732 # Simulator instruction rate (inst/s) -host_op_rate 290372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19883940078 # Simulator tick rate (ticks/s) -host_mem_usage 632768 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5548 # Number of instructions simulated -sim_ops 5548 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 22364 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 22364 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 5065 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 5065 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 5591 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 718 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 58799866 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 12199579 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 70999445 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 58799866 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 58799866 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 13316997 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 13316997 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 58799866 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25516576 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 84316442 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 6310 # Number of read requests accepted -system.mem_ctrl.writeReqs 673 # Number of write requests accepted -system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 397760 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 548 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 84 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 1004 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 875 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 348 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 99 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 623 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 56 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 162 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 200 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 78 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 16 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 42 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 19 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 5 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 4 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 10 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 380264000 # Total gap between requests -system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 509 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 13 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 2 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 54 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 604 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6215 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 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-system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 575 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 700.438261 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 528.229400 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 375.888489 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 575 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 59680000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 176211250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 31075000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9602.57 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28352.57 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1045.80 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 16.15 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 71.01 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 13.32 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.30 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.17 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.12 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5650 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 83 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 90.91 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 66.40 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54455.68 # Average gap between requests -system.mem_ctrl.pageHitRate 90.43 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2598960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1377585 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 28124460 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 401940 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 55884510 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 903360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 108619200 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 6618240 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 234030975 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 615.318415 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 255286000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 462000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 111848750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 # Time in different power states -system.mem_ctrl_1.actEnergy 1527960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 804540 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 16243500 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 99180 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 28273440.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35538930 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1997760 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 96272430 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 16892160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 11758020 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 209407920 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 550.579039 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 297220000 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 3473000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11978000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 42087750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 67670000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 380341000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 380341 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5548 # Number of instructions committed -system.cpu.committedOps 5548 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls -system.cpu.num_int_insts 4660 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10977 # number of times the integer registers were read -system.cpu.num_int_register_writes 5062 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1404 # number of memory refs -system.cpu.num_load_insts 726 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 380340.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1187 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction -system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5591 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6310 # Transaction distribution -system.membus.trans_dist::ReadResp 6309 # Transaction distribution -system.membus.trans_dist::WriteReq 673 # Transaction distribution -system.membus.trans_dist::WriteResp 673 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13965 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32069 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6983 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6983 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6983 # Request fanout histogram -system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 12691750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2300750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +sim_seconds 0.000380 +sim_ticks 380341000 +final_tick 380341000 +sim_freq 1000000000000 +host_inst_rate 164409 +host_op_rate 164322 +host_tick_rate 11259796640 +host_mem_usage 644796 +host_seconds 0.03 +sim_insts 5548 +sim_ops 5548 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 +system.mem_ctrl.bytes_read::cpu.inst 22364 +system.mem_ctrl.bytes_read::cpu.data 4640 +system.mem_ctrl.bytes_read::total 27004 +system.mem_ctrl.bytes_inst_read::cpu.inst 22364 +system.mem_ctrl.bytes_inst_read::total 22364 +system.mem_ctrl.bytes_written::cpu.data 5065 +system.mem_ctrl.bytes_written::total 5065 +system.mem_ctrl.num_reads::cpu.inst 5591 +system.mem_ctrl.num_reads::cpu.data 718 +system.mem_ctrl.num_reads::total 6309 +system.mem_ctrl.num_writes::cpu.data 673 +system.mem_ctrl.num_writes::total 673 +system.mem_ctrl.bw_read::cpu.inst 58799866 +system.mem_ctrl.bw_read::cpu.data 12199579 +system.mem_ctrl.bw_read::total 70999445 +system.mem_ctrl.bw_inst_read::cpu.inst 58799866 +system.mem_ctrl.bw_inst_read::total 58799866 +system.mem_ctrl.bw_write::cpu.data 13316997 +system.mem_ctrl.bw_write::total 13316997 +system.mem_ctrl.bw_total::cpu.inst 58799866 +system.mem_ctrl.bw_total::cpu.data 25516576 +system.mem_ctrl.bw_total::total 84316442 +system.mem_ctrl.readReqs 6310 +system.mem_ctrl.writeReqs 673 +system.mem_ctrl.readBursts 6310 +system.mem_ctrl.writeBursts 673 +system.mem_ctrl.bytesReadDRAM 397760 +system.mem_ctrl.bytesReadWrQ 6080 +system.mem_ctrl.bytesWritten 6144 +system.mem_ctrl.bytesReadSys 27008 +system.mem_ctrl.bytesWrittenSys 5065 +system.mem_ctrl.servicedByWrQ 95 +system.mem_ctrl.mergedWrBursts 548 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 220 +system.mem_ctrl.perBankRdBursts::1 84 +system.mem_ctrl.perBankRdBursts::2 2 +system.mem_ctrl.perBankRdBursts::3 199 +system.mem_ctrl.perBankRdBursts::4 0 +system.mem_ctrl.perBankRdBursts::5 1004 +system.mem_ctrl.perBankRdBursts::6 1555 +system.mem_ctrl.perBankRdBursts::7 875 +system.mem_ctrl.perBankRdBursts::8 710 +system.mem_ctrl.perBankRdBursts::9 348 +system.mem_ctrl.perBankRdBursts::10 99 +system.mem_ctrl.perBankRdBursts::11 623 +system.mem_ctrl.perBankRdBursts::12 56 +system.mem_ctrl.perBankRdBursts::13 162 +system.mem_ctrl.perBankRdBursts::14 200 +system.mem_ctrl.perBankRdBursts::15 78 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 16 +system.mem_ctrl.perBankWrBursts::6 42 +system.mem_ctrl.perBankWrBursts::7 19 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 5 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 4 +system.mem_ctrl.perBankWrBursts::13 10 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 380264000 +system.mem_ctrl.readPktSize::0 88 +system.mem_ctrl.readPktSize::1 2 +system.mem_ctrl.readPktSize::2 5711 +system.mem_ctrl.readPktSize::3 509 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 13 +system.mem_ctrl.writePktSize::1 2 +system.mem_ctrl.writePktSize::2 54 +system.mem_ctrl.writePktSize::3 604 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 6215 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 7 +system.mem_ctrl.wrQLenPdf::18 7 +system.mem_ctrl.wrQLenPdf::19 7 +system.mem_ctrl.wrQLenPdf::20 7 +system.mem_ctrl.wrQLenPdf::21 7 +system.mem_ctrl.wrQLenPdf::22 7 +system.mem_ctrl.wrQLenPdf::23 7 +system.mem_ctrl.wrQLenPdf::24 7 +system.mem_ctrl.wrQLenPdf::25 7 +system.mem_ctrl.wrQLenPdf::26 7 +system.mem_ctrl.wrQLenPdf::27 7 +system.mem_ctrl.wrQLenPdf::28 7 +system.mem_ctrl.wrQLenPdf::29 6 +system.mem_ctrl.wrQLenPdf::30 6 +system.mem_ctrl.wrQLenPdf::31 6 +system.mem_ctrl.wrQLenPdf::32 6 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 575 +system.mem_ctrl.bytesPerActivate::mean 700.438261 +system.mem_ctrl.bytesPerActivate::gmean 528.229400 +system.mem_ctrl.bytesPerActivate::stdev 375.888489 +system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% +system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% +system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% +system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% +system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% +system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% +system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% +system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% +system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% +system.mem_ctrl.bytesPerActivate::total 575 +system.mem_ctrl.rdPerTurnAround::samples 6 +system.mem_ctrl.rdPerTurnAround::mean 772.166667 +system.mem_ctrl.rdPerTurnAround::gmean 643.154197 +system.mem_ctrl.rdPerTurnAround::stdev 524.176084 +system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% +system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% +system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% +system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33% +system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00% +system.mem_ctrl.rdPerTurnAround::total 6 +system.mem_ctrl.wrPerTurnAround::samples 6 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 6 +system.mem_ctrl.totQLat 59680000 +system.mem_ctrl.totMemAccLat 176211250 +system.mem_ctrl.totBusLat 31075000 +system.mem_ctrl.avgQLat 9602.57 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28352.57 +system.mem_ctrl.avgRdBW 1045.80 +system.mem_ctrl.avgWrBW 16.15 +system.mem_ctrl.avgRdBWSys 71.01 +system.mem_ctrl.avgWrBWSys 13.32 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.30 +system.mem_ctrl.busUtilRead 8.17 +system.mem_ctrl.busUtilWrite 0.13 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 23.12 +system.mem_ctrl.readRowHits 5650 +system.mem_ctrl.writeRowHits 83 +system.mem_ctrl.readRowHitRate 90.91 +system.mem_ctrl.writeRowHitRate 66.40 +system.mem_ctrl.avgGap 54455.68 +system.mem_ctrl.pageHitRate 90.43 +system.mem_ctrl_0.actEnergy 2598960 +system.mem_ctrl_0.preEnergy 1377585 +system.mem_ctrl_0.readEnergy 28124460 +system.mem_ctrl_0.writeEnergy 401940 +system.mem_ctrl_0.refreshEnergy 29502720.000000 +system.mem_ctrl_0.actBackEnergy 55884510 +system.mem_ctrl_0.preBackEnergy 903360 +system.mem_ctrl_0.actPowerDownEnergy 108619200 +system.mem_ctrl_0.prePowerDownEnergy 6618240 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 234030975 +system.mem_ctrl_0.averagePower 615.318415 +system.mem_ctrl_0.totalIdleTime 255286000 +system.mem_ctrl_0.memoryStateTime::IDLE 462000 +system.mem_ctrl_0.memoryStateTime::REF 12480000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 +system.mem_ctrl_0.memoryStateTime::ACT 111848750 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 +system.mem_ctrl_1.actEnergy 1527960 +system.mem_ctrl_1.preEnergy 804540 +system.mem_ctrl_1.readEnergy 16243500 +system.mem_ctrl_1.writeEnergy 99180 +system.mem_ctrl_1.refreshEnergy 28273440.000000 +system.mem_ctrl_1.actBackEnergy 35538930 +system.mem_ctrl_1.preBackEnergy 1997760 +system.mem_ctrl_1.actPowerDownEnergy 96272430 +system.mem_ctrl_1.prePowerDownEnergy 16892160 +system.mem_ctrl_1.selfRefreshEnergy 11758020 +system.mem_ctrl_1.totalEnergy 209407920 +system.mem_ctrl_1.averagePower 550.579039 +system.mem_ctrl_1.totalIdleTime 297220000 +system.mem_ctrl_1.memoryStateTime::IDLE 3473000 +system.mem_ctrl_1.memoryStateTime::REF 11978000 +system.mem_ctrl_1.memoryStateTime::SREF 42087750 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 +system.mem_ctrl_1.memoryStateTime::ACT 67670000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 +system.pwrStateResidencyTicks::UNDEFINED 380341000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 380341000 +system.cpu.numCycles 380341 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5548 +system.cpu.committedOps 5548 +system.cpu.num_int_alu_accesses 4660 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 835 +system.cpu.num_int_insts 4660 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10977 +system.cpu.num_int_register_writes 5062 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1404 +system.cpu.num_load_insts 726 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 380341 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1187 +system.cpu.op_class::No_OpClass 173 3.09% 3.09% +system.cpu.op_class::IntAlu 4014 71.79% 74.89% +system.cpu.op_class::IntMult 0 0.00% 74.89% +system.cpu.op_class::IntDiv 0 0.00% 74.89% +system.cpu.op_class::FloatAdd 0 0.00% 74.89% +system.cpu.op_class::FloatCmp 0 0.00% 74.89% +system.cpu.op_class::FloatCvt 0 0.00% 74.89% +system.cpu.op_class::FloatMult 0 0.00% 74.89% +system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::FloatDiv 0 0.00% 74.89% +system.cpu.op_class::FloatMisc 0 0.00% 74.89% +system.cpu.op_class::FloatSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdAdd 0 0.00% 74.89% +system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% +system.cpu.op_class::SimdAlu 0 0.00% 74.89% +system.cpu.op_class::SimdCmp 0 0.00% 74.89% +system.cpu.op_class::SimdCvt 0 0.00% 74.89% +system.cpu.op_class::SimdMisc 0 0.00% 74.89% +system.cpu.op_class::SimdMult 0 0.00% 74.89% +system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdShift 0 0.00% 74.89% +system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% +system.cpu.op_class::SimdSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% +system.cpu.op_class::MemRead 726 12.99% 87.87% +system.cpu.op_class::MemWrite 678 12.13% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5591 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 +system.membus.trans_dist::ReadReq 6310 +system.membus.trans_dist::ReadResp 6309 +system.membus.trans_dist::WriteReq 673 +system.membus.trans_dist::WriteResp 673 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782 +system.membus.pkt_count::total 13965 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705 +system.membus.pkt_size::total 32069 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6983 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6983 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6983 +system.membus.reqLayer0.occupancy 7656000 +system.membus.reqLayer0.utilization 2.0 +system.membus.respLayer0.occupancy 12691750 +system.membus.respLayer0.utilization 3.3 +system.membus.respLayer1.occupancy 2300750 +system.membus.respLayer1.utilization 0.6 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini index d90641228..ec35c6b67 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini @@ -91,6 +91,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -104,10 +105,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +122,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +135,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -155,10 +158,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -172,6 +175,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -184,15 +188,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -212,7 +217,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/sparc/linux/hello cwd= drivers= @@ -225,10 +230,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -278,10 +284,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -295,6 +301,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -307,15 +314,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout index 95530f5be..ca7e9e456 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:45:43 -gem5 executing on e108600-lin, pid 17392 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:43:32 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66465 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 56511000 because target called exit() +Hello World!Exiting @ tick 56511000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 86dd54128..c0123cf6a 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,716 +1,716 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000057 # Number of seconds simulated -sim_ticks 56511000 # Number of ticks simulated -final_tick 56511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 572788 # Simulator instruction rate (inst/s) -host_op_rate 572177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5822018151 # Simulator tick rate (ticks/s) -host_mem_usage 636864 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5548 # Number of instructions simulated -sim_ops 5548 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 291058378 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 155155633 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 446214011 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 291058378 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 291058378 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 291058378 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 155155633 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 446214011 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 394 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 21 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 7 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 7 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 69 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 79 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 32 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 9 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 47 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 10 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 21 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 56394000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 394 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 248.816327 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 183.748429 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 196.431638 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 98 # Bytes accessed per row activation -system.mem_ctrl.totQLat 5793000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 13180500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 14703.05 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 33453.05 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 446.21 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 446.21 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.49 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.49 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 292 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 74.11 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 143131.98 # Average gap between requests -system.mem_ctrl.pageHitRate 74.11 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 421260 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 216315 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1756440 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 4075500 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 122880 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 21123630 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 357120 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 32375625 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 572.905837 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 47002000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 71000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 7357750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 # Time in different power states -system.mem_ctrl_1.actEnergy 307020 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 155595 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1056720 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 2785590 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 293760 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 20523420 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 1777920 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 31202505 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 552.146785 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 49582750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 557000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 4495750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 56511000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56511 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5548 # Number of instructions committed -system.cpu.committedOps 5548 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls -system.cpu.num_int_insts 4660 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10977 # number of times the integer registers were read -system.cpu.num_int_register_writes 5062 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1404 # number of memory refs -system.cpu.num_load_insts 726 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 56510.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1187 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction -system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5591 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.847801 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.081883 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.081883 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6576000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8937000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15513000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15513000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15513000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15513000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 112413.043478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 112413.043478 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15237000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15237000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.324434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.324434 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.384080 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.384080 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11443 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits -system.cpu.icache.overall_hits::total 5333 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses -system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27828000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27828000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27828000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27828000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27828000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27828000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 107444.015444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 107444.015444 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27310000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27310000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27310000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27310000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27310000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27310000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 315 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 397 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.007557 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.086709 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 394 99.24% 99.24% # Request fanout histogram -system.l2bus.snoop_fanout::1 3 0.76% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 397 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 201.052259 # Cycle average of tags in use -system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 118.133782 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 82.918477 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.028841 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.020244 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.049085 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 4130 # Number of tag accesses -system.l2cache.tags.data_accesses 4130 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.l2cache.overall_hits::total 3 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 82 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 82 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 257 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.l2cache.demand_misses::total 394 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 257 # number of overall misses -system.l2cache.overall_misses::cpu.data 137 # number of overall misses -system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8527000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8527000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26487000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 6273000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 32760000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 26487000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 14800000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 41287000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 26487000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 14800000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 41287000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 259 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 397 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.992278 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 105000 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 104789.340102 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 104789.340102 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6887000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6887000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21347000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5173000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 26520000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 21347000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 12060000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33407000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 12060000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33407000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 312 # Transaction distribution -system.membus.trans_dist::ReadExReq 82 # Transaction distribution -system.membus.trans_dist::ReadExResp 82 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 394 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 394 # Request fanout histogram -system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2102500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) +sim_seconds 0.000057 +sim_ticks 56511000 +final_tick 56511000 +sim_freq 1000000000000 +host_inst_rate 336003 +host_op_rate 335612 +host_tick_rate 3415114336 +host_mem_usage 648892 +host_seconds 0.02 +sim_insts 5548 +sim_ops 5548 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 +system.mem_ctrl.bytes_read::cpu.inst 16448 +system.mem_ctrl.bytes_read::cpu.data 8768 +system.mem_ctrl.bytes_read::total 25216 +system.mem_ctrl.bytes_inst_read::cpu.inst 16448 +system.mem_ctrl.bytes_inst_read::total 16448 +system.mem_ctrl.num_reads::cpu.inst 257 +system.mem_ctrl.num_reads::cpu.data 137 +system.mem_ctrl.num_reads::total 394 +system.mem_ctrl.bw_read::cpu.inst 291058378 +system.mem_ctrl.bw_read::cpu.data 155155633 +system.mem_ctrl.bw_read::total 446214011 +system.mem_ctrl.bw_inst_read::cpu.inst 291058378 +system.mem_ctrl.bw_inst_read::total 291058378 +system.mem_ctrl.bw_total::cpu.inst 291058378 +system.mem_ctrl.bw_total::cpu.data 155155633 +system.mem_ctrl.bw_total::total 446214011 +system.mem_ctrl.readReqs 394 +system.mem_ctrl.writeReqs 0 +system.mem_ctrl.readBursts 394 +system.mem_ctrl.writeBursts 0 +system.mem_ctrl.bytesReadDRAM 25216 +system.mem_ctrl.bytesReadWrQ 0 +system.mem_ctrl.bytesWritten 0 +system.mem_ctrl.bytesReadSys 25216 +system.mem_ctrl.bytesWrittenSys 0 +system.mem_ctrl.servicedByWrQ 0 +system.mem_ctrl.mergedWrBursts 0 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 21 +system.mem_ctrl.perBankRdBursts::1 7 +system.mem_ctrl.perBankRdBursts::2 1 +system.mem_ctrl.perBankRdBursts::3 7 +system.mem_ctrl.perBankRdBursts::4 0 +system.mem_ctrl.perBankRdBursts::5 69 +system.mem_ctrl.perBankRdBursts::6 79 +system.mem_ctrl.perBankRdBursts::7 62 +system.mem_ctrl.perBankRdBursts::8 32 +system.mem_ctrl.perBankRdBursts::9 17 +system.mem_ctrl.perBankRdBursts::10 9 +system.mem_ctrl.perBankRdBursts::11 47 +system.mem_ctrl.perBankRdBursts::12 10 +system.mem_ctrl.perBankRdBursts::13 21 +system.mem_ctrl.perBankRdBursts::14 5 +system.mem_ctrl.perBankRdBursts::15 7 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 0 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 56394000 +system.mem_ctrl.readPktSize::0 0 +system.mem_ctrl.readPktSize::1 0 +system.mem_ctrl.readPktSize::2 0 +system.mem_ctrl.readPktSize::3 0 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 394 +system.mem_ctrl.writePktSize::0 0 +system.mem_ctrl.writePktSize::1 0 +system.mem_ctrl.writePktSize::2 0 +system.mem_ctrl.writePktSize::3 0 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 394 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 0 +system.mem_ctrl.wrQLenPdf::1 0 +system.mem_ctrl.wrQLenPdf::2 0 +system.mem_ctrl.wrQLenPdf::3 0 +system.mem_ctrl.wrQLenPdf::4 0 +system.mem_ctrl.wrQLenPdf::5 0 +system.mem_ctrl.wrQLenPdf::6 0 +system.mem_ctrl.wrQLenPdf::7 0 +system.mem_ctrl.wrQLenPdf::8 0 +system.mem_ctrl.wrQLenPdf::9 0 +system.mem_ctrl.wrQLenPdf::10 0 +system.mem_ctrl.wrQLenPdf::11 0 +system.mem_ctrl.wrQLenPdf::12 0 +system.mem_ctrl.wrQLenPdf::13 0 +system.mem_ctrl.wrQLenPdf::14 0 +system.mem_ctrl.wrQLenPdf::15 0 +system.mem_ctrl.wrQLenPdf::16 0 +system.mem_ctrl.wrQLenPdf::17 0 +system.mem_ctrl.wrQLenPdf::18 0 +system.mem_ctrl.wrQLenPdf::19 0 +system.mem_ctrl.wrQLenPdf::20 0 +system.mem_ctrl.wrQLenPdf::21 0 +system.mem_ctrl.wrQLenPdf::22 0 +system.mem_ctrl.wrQLenPdf::23 0 +system.mem_ctrl.wrQLenPdf::24 0 +system.mem_ctrl.wrQLenPdf::25 0 +system.mem_ctrl.wrQLenPdf::26 0 +system.mem_ctrl.wrQLenPdf::27 0 +system.mem_ctrl.wrQLenPdf::28 0 +system.mem_ctrl.wrQLenPdf::29 0 +system.mem_ctrl.wrQLenPdf::30 0 +system.mem_ctrl.wrQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::32 0 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 98 +system.mem_ctrl.bytesPerActivate::mean 248.816327 +system.mem_ctrl.bytesPerActivate::gmean 183.748429 +system.mem_ctrl.bytesPerActivate::stdev 196.431638 +system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% +system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% +system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% +system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% +system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% +system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% +system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% +system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% +system.mem_ctrl.bytesPerActivate::total 98 +system.mem_ctrl.totQLat 5793000 +system.mem_ctrl.totMemAccLat 13180500 +system.mem_ctrl.totBusLat 1970000 +system.mem_ctrl.avgQLat 14703.05 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 33453.05 +system.mem_ctrl.avgRdBW 446.21 +system.mem_ctrl.avgWrBW 0.00 +system.mem_ctrl.avgRdBWSys 446.21 +system.mem_ctrl.avgWrBWSys 0.00 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 3.49 +system.mem_ctrl.busUtilRead 3.49 +system.mem_ctrl.busUtilWrite 0.00 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 0.00 +system.mem_ctrl.readRowHits 292 +system.mem_ctrl.writeRowHits 0 +system.mem_ctrl.readRowHitRate 74.11 +system.mem_ctrl.writeRowHitRate nan +system.mem_ctrl.avgGap 143131.98 +system.mem_ctrl.pageHitRate 74.11 +system.mem_ctrl_0.actEnergy 421260 +system.mem_ctrl_0.preEnergy 216315 +system.mem_ctrl_0.readEnergy 1756440 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 4302480.000000 +system.mem_ctrl_0.actBackEnergy 4075500 +system.mem_ctrl_0.preBackEnergy 122880 +system.mem_ctrl_0.actPowerDownEnergy 21123630 +system.mem_ctrl_0.prePowerDownEnergy 357120 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 32375625 +system.mem_ctrl_0.averagePower 572.905837 +system.mem_ctrl_0.totalIdleTime 47002000 +system.mem_ctrl_0.memoryStateTime::IDLE 71000 +system.mem_ctrl_0.memoryStateTime::REF 1820000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 +system.mem_ctrl_0.memoryStateTime::ACT 7357750 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 +system.mem_ctrl_1.actEnergy 307020 +system.mem_ctrl_1.preEnergy 155595 +system.mem_ctrl_1.readEnergy 1056720 +system.mem_ctrl_1.writeEnergy 0 +system.mem_ctrl_1.refreshEnergy 4302480.000000 +system.mem_ctrl_1.actBackEnergy 2785590 +system.mem_ctrl_1.preBackEnergy 293760 +system.mem_ctrl_1.actPowerDownEnergy 20523420 +system.mem_ctrl_1.prePowerDownEnergy 1777920 +system.mem_ctrl_1.selfRefreshEnergy 0 +system.mem_ctrl_1.totalEnergy 31202505 +system.mem_ctrl_1.averagePower 552.146785 +system.mem_ctrl_1.totalIdleTime 49582750 +system.mem_ctrl_1.memoryStateTime::IDLE 557000 +system.mem_ctrl_1.memoryStateTime::REF 1820000 +system.mem_ctrl_1.memoryStateTime::SREF 0 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 +system.mem_ctrl_1.memoryStateTime::ACT 4495750 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 +system.pwrStateResidencyTicks::UNDEFINED 56511000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 56511000 +system.cpu.numCycles 56511 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5548 +system.cpu.committedOps 5548 +system.cpu.num_int_alu_accesses 4660 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 835 +system.cpu.num_int_insts 4660 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10977 +system.cpu.num_int_register_writes 5062 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1404 +system.cpu.num_load_insts 726 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 56511 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1187 +system.cpu.op_class::No_OpClass 173 3.09% 3.09% +system.cpu.op_class::IntAlu 4014 71.79% 74.89% +system.cpu.op_class::IntMult 0 0.00% 74.89% +system.cpu.op_class::IntDiv 0 0.00% 74.89% +system.cpu.op_class::FloatAdd 0 0.00% 74.89% +system.cpu.op_class::FloatCmp 0 0.00% 74.89% +system.cpu.op_class::FloatCvt 0 0.00% 74.89% +system.cpu.op_class::FloatMult 0 0.00% 74.89% +system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::FloatDiv 0 0.00% 74.89% +system.cpu.op_class::FloatMisc 0 0.00% 74.89% +system.cpu.op_class::FloatSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdAdd 0 0.00% 74.89% +system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% +system.cpu.op_class::SimdAlu 0 0.00% 74.89% +system.cpu.op_class::SimdCmp 0 0.00% 74.89% +system.cpu.op_class::SimdCvt 0 0.00% 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+system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 +system.membus.pkt_size::total 25216 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 394 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 394 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 394 +system.membus.reqLayer0.occupancy 394000 +system.membus.reqLayer0.utilization 0.7 +system.membus.respLayer0.occupancy 2102500 +system.membus.respLayer0.utilization 3.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini index 612b72e20..55e4fb657 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -180,10 +182,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout index 3227a9df4..7864b0cf9 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:11:23 -gem5 executing on e108600-lin, pid 17668 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:23 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87205 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 507841000 because target called exit() +Exiting @ tick 507841000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index 7797c05db..b34dd3952 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,398 +1,398 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000508 # Number of seconds simulated -sim_ticks 507841000 # Number of ticks simulated -final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118772 # Simulator instruction rate (inst/s) -host_op_rate 214398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10553661963 # Simulator tick rate (ticks/s) -host_mem_usage 651408 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 7160 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 7160 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 7283 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1084 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 114728823 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14112685 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 128841507 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 114728823 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 28211586 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 142940409 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 8367 # Number of read requests accepted -system.mem_ctrl.writeReqs 941 # Number of write requests accepted -system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 1619 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 965 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1103 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 10 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 54 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 34 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 4 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 507709000 # Total gap between requests -system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 8099 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 14 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 3 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 63 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 861 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 856 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 618.018692 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 421.107711 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 393.969749 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 856 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 82515500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 236378000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 10055.51 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28805.51 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1034.15 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 14.11 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 128.84 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 14.10 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.08 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.79 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7357 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.65 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54545.44 # Average gap between requests -system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3127320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1647030 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37149420 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 52200 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 70559160 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1716480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 113314290 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 13222080 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 17426520 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 294478260 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 579.862821 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 347720500 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 1584000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 15358000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 65707000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 142245250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 # Time in different power states -system.mem_ctrl_1.actEnergy 3034500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1601490 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 21441420 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 532440 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 51598110 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1155360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 151289970 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 18740160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 3216240 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 291946650 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 574.877779 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 391695500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 757000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 16646000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 11100000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 98712250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 507841000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 507841 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 507840.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 8367 # Transaction distribution -system.membus.trans_dist::ReadResp 8367 # Transaction distribution -system.membus.trans_dist::WriteReq 941 # Transaction distribution -system.membus.trans_dist::WriteResp 941 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 18616 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 72591 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 9308 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9308 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9308 # Request fanout histogram -system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 16544750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3432250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +sim_seconds 0.000508 +sim_ticks 507841000 +final_tick 507841000 +sim_freq 1000000000000 +host_inst_rate 110016 +host_op_rate 198569 +host_tick_rate 9773316243 +host_mem_usage 663056 +host_seconds 0.05 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 +system.mem_ctrl.bytes_read::cpu.inst 58264 +system.mem_ctrl.bytes_read::cpu.data 7167 +system.mem_ctrl.bytes_read::total 65431 +system.mem_ctrl.bytes_inst_read::cpu.inst 58264 +system.mem_ctrl.bytes_inst_read::total 58264 +system.mem_ctrl.bytes_written::cpu.data 7160 +system.mem_ctrl.bytes_written::total 7160 +system.mem_ctrl.num_reads::cpu.inst 7283 +system.mem_ctrl.num_reads::cpu.data 1084 +system.mem_ctrl.num_reads::total 8367 +system.mem_ctrl.num_writes::cpu.data 941 +system.mem_ctrl.num_writes::total 941 +system.mem_ctrl.bw_read::cpu.inst 114728823 +system.mem_ctrl.bw_read::cpu.data 14112685 +system.mem_ctrl.bw_read::total 128841507 +system.mem_ctrl.bw_inst_read::cpu.inst 114728823 +system.mem_ctrl.bw_inst_read::total 114728823 +system.mem_ctrl.bw_write::cpu.data 14098901 +system.mem_ctrl.bw_write::total 14098901 +system.mem_ctrl.bw_total::cpu.inst 114728823 +system.mem_ctrl.bw_total::cpu.data 28211586 +system.mem_ctrl.bw_total::total 142940409 +system.mem_ctrl.readReqs 8368 +system.mem_ctrl.writeReqs 941 +system.mem_ctrl.readBursts 8368 +system.mem_ctrl.writeBursts 941 +system.mem_ctrl.bytesReadDRAM 525248 +system.mem_ctrl.bytesReadWrQ 10304 +system.mem_ctrl.bytesWritten 7168 +system.mem_ctrl.bytesReadSys 65439 +system.mem_ctrl.bytesWrittenSys 7160 +system.mem_ctrl.servicedByWrQ 161 +system.mem_ctrl.mergedWrBursts 810 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 277 +system.mem_ctrl.perBankRdBursts::1 4 +system.mem_ctrl.perBankRdBursts::2 227 +system.mem_ctrl.perBankRdBursts::3 102 +system.mem_ctrl.perBankRdBursts::4 1619 +system.mem_ctrl.perBankRdBursts::5 965 +system.mem_ctrl.perBankRdBursts::6 1103 +system.mem_ctrl.perBankRdBursts::7 906 +system.mem_ctrl.perBankRdBursts::8 703 +system.mem_ctrl.perBankRdBursts::9 491 +system.mem_ctrl.perBankRdBursts::10 1059 +system.mem_ctrl.perBankRdBursts::11 59 +system.mem_ctrl.perBankRdBursts::12 11 +system.mem_ctrl.perBankRdBursts::13 489 +system.mem_ctrl.perBankRdBursts::14 78 +system.mem_ctrl.perBankRdBursts::15 114 +system.mem_ctrl.perBankWrBursts::0 10 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 3 +system.mem_ctrl.perBankWrBursts::9 54 +system.mem_ctrl.perBankWrBursts::10 34 +system.mem_ctrl.perBankWrBursts::11 7 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 4 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 507764000 +system.mem_ctrl.readPktSize::0 135 +system.mem_ctrl.readPktSize::1 14 +system.mem_ctrl.readPktSize::2 119 +system.mem_ctrl.readPktSize::3 8100 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 14 +system.mem_ctrl.writePktSize::1 3 +system.mem_ctrl.writePktSize::2 63 +system.mem_ctrl.writePktSize::3 861 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 8207 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 8 +system.mem_ctrl.wrQLenPdf::18 8 +system.mem_ctrl.wrQLenPdf::19 7 +system.mem_ctrl.wrQLenPdf::20 7 +system.mem_ctrl.wrQLenPdf::21 7 +system.mem_ctrl.wrQLenPdf::22 7 +system.mem_ctrl.wrQLenPdf::23 7 +system.mem_ctrl.wrQLenPdf::24 7 +system.mem_ctrl.wrQLenPdf::25 7 +system.mem_ctrl.wrQLenPdf::26 7 +system.mem_ctrl.wrQLenPdf::27 7 +system.mem_ctrl.wrQLenPdf::28 7 +system.mem_ctrl.wrQLenPdf::29 7 +system.mem_ctrl.wrQLenPdf::30 7 +system.mem_ctrl.wrQLenPdf::31 7 +system.mem_ctrl.wrQLenPdf::32 7 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 856 +system.mem_ctrl.bytesPerActivate::mean 618.018692 +system.mem_ctrl.bytesPerActivate::gmean 421.107711 +system.mem_ctrl.bytesPerActivate::stdev 393.969749 +system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% +system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% +system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% +system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% +system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% +system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% +system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% +system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% +system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% +system.mem_ctrl.bytesPerActivate::total 856 +system.mem_ctrl.rdPerTurnAround::samples 7 +system.mem_ctrl.rdPerTurnAround::mean 1165.285714 +system.mem_ctrl.rdPerTurnAround::gmean 941.793638 +system.mem_ctrl.rdPerTurnAround::stdev 714.559471 +system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% +system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% +system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% +system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% +system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% +system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% +system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% +system.mem_ctrl.rdPerTurnAround::total 7 +system.mem_ctrl.wrPerTurnAround::samples 7 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 7 +system.mem_ctrl.totQLat 82521500 +system.mem_ctrl.totMemAccLat 236402750 +system.mem_ctrl.totBusLat 41035000 +system.mem_ctrl.avgQLat 10055.01 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28805.01 +system.mem_ctrl.avgRdBW 1034.28 +system.mem_ctrl.avgWrBW 14.11 +system.mem_ctrl.avgRdBWSys 128.86 +system.mem_ctrl.avgWrBWSys 14.10 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.19 +system.mem_ctrl.busUtilRead 8.08 +system.mem_ctrl.busUtilWrite 0.11 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 23.79 +system.mem_ctrl.readRowHits 7358 +system.mem_ctrl.writeRowHits 98 +system.mem_ctrl.readRowHitRate 89.66 +system.mem_ctrl.writeRowHitRate 74.81 +system.mem_ctrl.avgGap 54545.49 +system.mem_ctrl.pageHitRate 89.42 +system.mem_ctrl_0.actEnergy 3127320 +system.mem_ctrl_0.preEnergy 1647030 +system.mem_ctrl_0.readEnergy 37149420 +system.mem_ctrl_0.writeEnergy 52200 +system.mem_ctrl_0.refreshEnergy 36263760.000000 +system.mem_ctrl_0.actBackEnergy 70559160 +system.mem_ctrl_0.preBackEnergy 1716480 +system.mem_ctrl_0.actPowerDownEnergy 113314290 +system.mem_ctrl_0.prePowerDownEnergy 13222080 +system.mem_ctrl_0.selfRefreshEnergy 17426520 +system.mem_ctrl_0.totalEnergy 294478260 +system.mem_ctrl_0.averagePower 579.862821 +system.mem_ctrl_0.totalIdleTime 347720500 +system.mem_ctrl_0.memoryStateTime::IDLE 1584000 +system.mem_ctrl_0.memoryStateTime::REF 15358000 +system.mem_ctrl_0.memoryStateTime::SREF 65707000 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 +system.mem_ctrl_0.memoryStateTime::ACT 142245250 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 +system.mem_ctrl_1.actEnergy 3034500 +system.mem_ctrl_1.preEnergy 1601490 +system.mem_ctrl_1.readEnergy 21441420 +system.mem_ctrl_1.writeEnergy 532440 +system.mem_ctrl_1.refreshEnergy 39336960.000000 +system.mem_ctrl_1.actBackEnergy 51598110 +system.mem_ctrl_1.preBackEnergy 1155360 +system.mem_ctrl_1.actPowerDownEnergy 151289970 +system.mem_ctrl_1.prePowerDownEnergy 18740160 +system.mem_ctrl_1.selfRefreshEnergy 3216240 +system.mem_ctrl_1.totalEnergy 291946650 +system.mem_ctrl_1.averagePower 574.877779 +system.mem_ctrl_1.totalIdleTime 391725750 +system.mem_ctrl_1.memoryStateTime::IDLE 757000 +system.mem_ctrl_1.memoryStateTime::REF 16646000 +system.mem_ctrl_1.memoryStateTime::SREF 11100000 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 +system.mem_ctrl_1.memoryStateTime::ACT 98712250 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 +system.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.apic_clk_domain.clock 16000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 507841000 +system.cpu.numCycles 507841 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5712 +system.cpu.committedOps 10314 +system.cpu.num_int_alu_accesses 10205 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 221 +system.cpu.num_conditional_control_insts 986 +system.cpu.num_int_insts 10205 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 19296 +system.cpu.num_int_register_writes 7977 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 7020 +system.cpu.num_cc_register_writes 3825 +system.cpu.num_mem_refs 2025 +system.cpu.num_load_insts 1084 +system.cpu.num_store_insts 941 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 507841 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1306 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 8275 80.23% 80.24% +system.cpu.op_class::IntMult 6 0.06% 80.30% +system.cpu.op_class::IntDiv 7 0.07% 80.37% +system.cpu.op_class::FloatAdd 0 0.00% 80.37% +system.cpu.op_class::FloatCmp 0 0.00% 80.37% +system.cpu.op_class::FloatCvt 0 0.00% 80.37% +system.cpu.op_class::FloatMult 0 0.00% 80.37% +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::FloatDiv 0 0.00% 80.37% +system.cpu.op_class::FloatMisc 0 0.00% 80.37% +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdAdd 0 0.00% 80.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% +system.cpu.op_class::SimdAlu 0 0.00% 80.37% +system.cpu.op_class::SimdCmp 0 0.00% 80.37% +system.cpu.op_class::SimdCvt 0 0.00% 80.37% +system.cpu.op_class::SimdMisc 0 0.00% 80.37% +system.cpu.op_class::SimdMult 0 0.00% 80.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdShift 0 0.00% 80.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% +system.cpu.op_class::MemRead 1084 10.51% 90.88% +system.cpu.op_class::MemWrite 941 9.12% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 10314 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 +system.membus.trans_dist::ReadReq 8368 +system.membus.trans_dist::ReadResp 8367 +system.membus.trans_dist::WriteReq 941 +system.membus.trans_dist::WriteResp 941 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14567 +system.membus.pkt_count_system.cpu.icache_port::total 14567 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 +system.membus.pkt_count_system.cpu.dcache_port::total 4050 +system.membus.pkt_count::total 18617 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 +system.membus.pkt_size_system.cpu.icache_port::total 58264 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 +system.membus.pkt_size_system.cpu.dcache_port::total 14327 +system.membus.pkt_size::total 72591 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 9309 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 9309 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 9309 +system.membus.reqLayer2.occupancy 10250000 +system.membus.reqLayer2.utilization 2.0 +system.membus.respLayer0.occupancy 16544750 +system.membus.respLayer0.utilization 3.3 +system.membus.respLayer1.occupancy 3432250 +system.membus.respLayer1.utilization 0.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini index c3a9301a3..be3d0013c 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -110,10 +112,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -127,6 +129,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -139,15 +142,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -175,10 +179,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -192,6 +196,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -204,15 +209,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -259,7 +265,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -272,10 +278,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -325,10 +332,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -342,6 +349,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -354,15 +362,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout index 736ff89ea..51ea33107 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:22 -gem5 executing on e108600-lin, pid 17647 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87157 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 58513000 because target called exit() +Exiting @ tick 58513000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index c7497d010..5f55051fc 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,722 +1,722 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 58513000 # Number of ticks simulated -final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297973 # Simulator instruction rate (inst/s) -host_op_rate 537391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3045372421 # Simulator tick rate (ticks/s) -host_mem_usage 656016 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 364 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 30 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 40 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 24 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 71 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 16 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58376000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 364 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation -system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 160373.63 # Average gap between requests -system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states -system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58513 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits -system.cpu.dcache.overall_hits::total 1890 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses -system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits -system.cpu.icache.overall_hits::total 7048 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses -system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 291 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 370 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.002703 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.051988 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 370 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use -system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3788 # Number of tag accesses -system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits -system.l2cache.demand_hits::total 6 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 6 # number of overall hits -system.l2cache.overall_hits::total 6 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.l2cache.demand_misses::total 364 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 229 # number of overall misses -system.l2cache.overall_misses::cpu.data 135 # number of overall misses -system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 235 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 370 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 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106170.370370 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 285 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::total 23296 # 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-system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +sim_seconds 0.000059 +sim_ticks 58513000 +final_tick 58513000 +sim_freq 1000000000000 +host_inst_rate 157408 +host_op_rate 284057 +host_tick_rate 1610644917 +host_mem_usage 667152 +host_seconds 0.04 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 +system.mem_ctrl.bytes_read::cpu.inst 14656 +system.mem_ctrl.bytes_read::cpu.data 8640 +system.mem_ctrl.bytes_read::total 23296 +system.mem_ctrl.bytes_inst_read::cpu.inst 14656 +system.mem_ctrl.bytes_inst_read::total 14656 +system.mem_ctrl.num_reads::cpu.inst 229 +system.mem_ctrl.num_reads::cpu.data 135 +system.mem_ctrl.num_reads::total 364 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12800.00 +system.mem_ctrl.busUtil 3.11 +system.mem_ctrl.busUtilRead 3.11 +system.mem_ctrl.busUtilWrite 0.00 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 0.00 +system.mem_ctrl.readRowHits 248 +system.mem_ctrl.writeRowHits 0 +system.mem_ctrl.readRowHitRate 68.13 +system.mem_ctrl.writeRowHitRate nan +system.mem_ctrl.avgGap 160373.63 +system.mem_ctrl.pageHitRate 68.13 +system.mem_ctrl_0.actEnergy 292740 +system.mem_ctrl_0.preEnergy 136620 +system.mem_ctrl_0.readEnergy 1170960 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 4302480.000000 +system.mem_ctrl_0.actBackEnergy 2975970 +system.mem_ctrl_0.preBackEnergy 96960 +system.mem_ctrl_0.actPowerDownEnergy 20164320 +system.mem_ctrl_0.prePowerDownEnergy 2885760 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 32025810 +system.mem_ctrl_0.averagePower 547.321100 +system.mem_ctrl_0.totalIdleTime 51467750 +system.mem_ctrl_0.memoryStateTime::IDLE 59000 +system.mem_ctrl_0.memoryStateTime::REF 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+system.l2cache.overall_mshr_misses::cpu.inst 229 +system.l2cache.overall_mshr_misses::cpu.data 135 +system.l2cache.overall_mshr_misses::total 364 +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 +system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 +system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 +system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 +system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 +system.l2cache.demand_mshr_miss_latency::total 31379000 +system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 +system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 +system.l2cache.overall_mshr_miss_latency::total 31379000 +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 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86206.043956 +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 +system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 +system.membus.snoop_filter.tot_requests 364 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 +system.membus.trans_dist::ReadResp 285 +system.membus.trans_dist::ReadExReq 79 +system.membus.trans_dist::ReadExResp 79 +system.membus.trans_dist::ReadSharedReq 285 +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 +system.membus.pkt_count_system.l2cache.mem_side::total 728 +system.membus.pkt_count::total 728 +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 +system.membus.pkt_size_system.l2cache.mem_side::total 23296 +system.membus.pkt_size::total 23296 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 364 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 364 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 364 +system.membus.reqLayer2.occupancy 364000 +system.membus.reqLayer2.utilization 0.6 +system.membus.respLayer0.occupancy 1951250 +system.membus.respLayer0.utilization 3.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini index 66d67b951..634dac451 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini @@ -1234,6 +1234,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=536870912 +system=system version=0 [system.dir_cntrl0.probeToCore] diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout index 6c1fcd449..3b8d8439d 100755 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ru gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2017 16:47:29 -gem5 started Mar 28 2017 16:47:45 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 50774 +gem5 compiled Mar 29 2017 16:09:06 +gem5 started Mar 29 2017 16:09:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54093 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO Using GPU kernel code file(s) /usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm @@ -19,4 +19,4 @@ Forcing maxCoalescedReqs to 32 (TLB assoc.) keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 the gpu says: elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe -Exiting @ tick 667407500 because target called exit() +Exiting @ tick 667407500 because exiting with last active thread context diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index ef3da5994..8bd8eadec 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000667 sim_ticks 667407500 final_tick 667407500 sim_freq 1000000000000 -host_inst_rate 219740 -host_op_rate 451865 -host_tick_rate 2189959227 -host_mem_usage 1336836 -host_seconds 0.30 +host_inst_rate 212660 +host_op_rate 437306 +host_tick_rate 2119397283 +host_mem_usage 1336868 +host_seconds 0.32 sim_insts 66963 sim_ops 137705 system.voltage_domain.voltage 1 @@ -299,12 +299,12 @@ system.pwrStateResidencyTicks::UNDEFINED 667407500 system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 114203 +system.ruby.outstanding_req_hist_seqr::samples 114204 system.ruby.outstanding_req_hist_seqr::mean 1.000035 system.ruby.outstanding_req_hist_seqr::gmean 1.000024 system.ruby.outstanding_req_hist_seqr::stdev 0.005918 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 114203 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114200 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 114204 system.ruby.outstanding_req_hist_coalsr::bucket_size 1 system.ruby.outstanding_req_hist_coalsr::max_bucket 9 system.ruby.outstanding_req_hist_coalsr::samples 27 @@ -431,8 +431,8 @@ system.cpu0.num_cc_register_writes 42183 system.cpu0.num_mem_refs 27198 system.cpu0.num_load_insts 16684 system.cpu0.num_store_insts 10514 -system.cpu0.num_idle_cycles 4191.003994 -system.cpu0.num_busy_cycles 1330623.996006 +system.cpu0.num_idle_cycles 4191.001994 +system.cpu0.num_busy_cycles 1330623.998006 system.cpu0.not_idle_fraction 0.996860 system.cpu0.idle_fraction 0.003140 system.cpu0.Branches 16199 diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 01ff6a1ab..ac0dae266 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout index fcb337fda..5142942fc 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23089 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54233 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 54141000500 because target called exit() +Exiting @ tick 54141000500 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index c0847e153..5844293a7 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.054141 # Number of seconds simulated -sim_ticks 54141000500 # Number of ticks simulated -final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2113722 # Simulator instruction rate (inst/s) -host_op_rate 2124249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1263089948 # Simulator tick rate (ticks/s) -host_mem_usage 393096 # Number of bytes of host memory used -host_seconds 42.86 # Real time elapsed on the host -sim_insts 90602408 # Number of instructions simulated -sim_ops 91053639 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory -system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory -system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 108282002 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90602408 # Number of instructions committed -system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124257600 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 130287906 # Transaction distribution -system.membus.trans_dist::ReadResp 130291793 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 135031171 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 135031171 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 135031171 # Request fanout histogram +sim_seconds 0.054141 +sim_ticks 54141000500 +final_tick 54141000500 +sim_freq 1000000000000 +host_inst_rate 903691 +host_op_rate 908191 +host_tick_rate 540015581 +host_mem_usage 404604 +host_seconds 100.26 +sim_insts 90602408 +sim_ops 91053639 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.physmem.bytes_read::cpu.inst 431323084 +system.physmem.bytes_read::cpu.data 90016598 +system.physmem.bytes_read::total 521339682 +system.physmem.bytes_inst_read::cpu.inst 431323084 +system.physmem.bytes_inst_read::total 431323084 +system.physmem.bytes_written::cpu.data 18908138 +system.physmem.bytes_written::total 18908138 +system.physmem.num_reads::cpu.inst 107830771 +system.physmem.num_reads::cpu.data 22461532 +system.physmem.num_reads::total 130292303 +system.physmem.num_writes::cpu.data 4738868 +system.physmem.num_writes::total 4738868 +system.physmem.bw_read::cpu.inst 7966662604 +system.physmem.bw_read::cpu.data 1662632703 +system.physmem.bw_read::total 9629295306 +system.physmem.bw_inst_read::cpu.inst 7966662604 +system.physmem.bw_inst_read::total 7966662604 +system.physmem.bw_write::cpu.data 349238799 +system.physmem.bw_write::total 349238799 +system.physmem.bw_total::cpu.inst 7966662604 +system.physmem.bw_total::cpu.data 2011871502 +system.physmem.bw_total::total 9978534106 +system.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 442 +system.cpu.pwrStateResidencyTicks::ON 54141000500 +system.cpu.numCycles 108282002 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 90602408 +system.cpu.committedOps 91053639 +system.cpu.num_int_alu_accesses 72326352 +system.cpu.num_fp_alu_accesses 48 +system.cpu.num_func_calls 112245 +system.cpu.num_conditional_control_insts 15520157 +system.cpu.num_int_insts 72326352 +system.cpu.num_fp_insts 48 +system.cpu.num_int_register_reads 124257600 +system.cpu.num_int_register_writes 52782988 +system.cpu.num_fp_register_reads 54 +system.cpu.num_fp_register_writes 30 +system.cpu.num_cc_register_reads 271814243 +system.cpu.num_cc_register_writes 53956115 +system.cpu.num_mem_refs 27220755 +system.cpu.num_load_insts 22475911 +system.cpu.num_store_insts 4744844 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 108282002 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 18732305 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 63822829 70.09% 70.09% +system.cpu.op_class::IntMult 10474 0.01% 70.10% +system.cpu.op_class::IntDiv 0 0.00% 70.10% +system.cpu.op_class::FloatAdd 0 0.00% 70.10% +system.cpu.op_class::FloatCmp 0 0.00% 70.10% +system.cpu.op_class::FloatCvt 0 0.00% 70.10% +system.cpu.op_class::FloatMult 0 0.00% 70.10% +system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% +system.cpu.op_class::FloatDiv 0 0.00% 70.10% +system.cpu.op_class::FloatMisc 0 0.00% 70.10% +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% +system.cpu.op_class::SimdAdd 0 0.00% 70.10% +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% +system.cpu.op_class::SimdAlu 0 0.00% 70.10% +system.cpu.op_class::SimdCmp 0 0.00% 70.10% +system.cpu.op_class::SimdCvt 0 0.00% 70.10% +system.cpu.op_class::SimdMisc 0 0.00% 70.10% +system.cpu.op_class::SimdMult 0 0.00% 70.10% +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% +system.cpu.op_class::SimdShift 0 0.00% 70.10% +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% +system.cpu.op_class::MemRead 22475905 24.68% 94.79% +system.cpu.op_class::MemWrite 4744822 5.21% 100.00% +system.cpu.op_class::FloatMemRead 6 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 91054081 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.membus.trans_dist::ReadReq 130287906 +system.membus.trans_dist::ReadResp 130291793 +system.membus.trans_dist::WriteReq 4734981 +system.membus.trans_dist::WriteResp 4734981 +system.membus.trans_dist::SoftPFReq 510 +system.membus.trans_dist::SoftPFResp 510 +system.membus.trans_dist::LoadLockedReq 3887 +system.membus.trans_dist::StoreCondReq 3887 +system.membus.trans_dist::StoreCondResp 3887 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 +system.membus.pkt_count::total 270062342 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 +system.membus.pkt_size::total 540247820 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 135031171 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 135031171 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 135031171 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 8e2469e68..65ada4bb2 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout index 70c7c951b..b4d1d6fbf 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:58:41 -gem5 executing on e108600-lin, pid 24094 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54228 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 147148719500 because target called exit() +Exiting @ tick 147164058500 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 208468615..54d266736 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,673 +1,673 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.147164 # Number of seconds simulated -sim_ticks 147164058500 # Number of ticks simulated -final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1482184 # Simulator instruction rate (inst/s) -host_op_rate 1489549 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2408165715 # Simulator tick rate (ticks/s) -host_mem_usage 404112 # Number of bytes of host memory used -host_seconds 61.11 # Real time elapsed on the host -sim_insts 90576862 # Number of instructions simulated -sim_ops 91026991 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory -system.physmem.bytes_read::total 981760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 294328117 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576862 # Number of instructions committed -system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124236934 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249077 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses -system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various 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36670000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36670000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks -system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles 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latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.325518 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15135236 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits -system.cpu.l2cache.overall_hits::total 932057 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses -system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 928334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 928334500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses 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-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 15340 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 0.147164 +sim_ticks 147164058500 +final_tick 147164058500 +sim_freq 1000000000000 +host_inst_rate 652695 +host_op_rate 655939 +host_tick_rate 1060461195 +host_mem_usage 414592 +host_seconds 138.77 +sim_insts 90576862 +sim_ops 91026991 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 +system.physmem.bytes_read::cpu.inst 36928 +system.physmem.bytes_read::cpu.data 944832 +system.physmem.bytes_read::total 981760 +system.physmem.bytes_inst_read::cpu.inst 36928 +system.physmem.bytes_inst_read::total 36928 +system.physmem.num_reads::cpu.inst 577 +system.physmem.num_reads::cpu.data 14763 +system.physmem.num_reads::total 15340 +system.physmem.bw_read::cpu.inst 250931 +system.physmem.bw_read::cpu.data 6420263 +system.physmem.bw_read::total 6671194 +system.physmem.bw_inst_read::cpu.inst 250931 +system.physmem.bw_inst_read::total 250931 +system.physmem.bw_total::cpu.inst 250931 +system.physmem.bw_total::cpu.data 6420263 +system.physmem.bw_total::total 6671194 +system.pwrStateResidencyTicks::UNDEFINED 147164058500 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+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 442 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14763 +system.cpu.l2cache.demand_mshr_misses::total 15340 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 +system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 +system.cpu.l2cache.overall_mshr_misses::total 15340 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 +system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 +system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 +system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 +system.cpu.toL2Bus.trans_dist::ReadResp 900788 +system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 +system.cpu.toL2Bus.trans_dist::WritebackClean 2 +system.cpu.toL2Bus.trans_dist::CleanEvict 368 +system.cpu.toL2Bus.trans_dist::ReadExReq 46609 +system.cpu.toL2Bus.trans_dist::ReadExResp 46609 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 +system.cpu.toL2Bus.pkt_count::total 2837498 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 +system.cpu.toL2Bus.pkt_size::total 120942912 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 947397 +system.cpu.toL2Bus.snoop_fanout::mean 0.000132 +system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% +system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 947397 +system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 +system.cpu.toL2Bus.reqLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer0.occupancy 898500 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 1420197000 +system.cpu.toL2Bus.respLayer1.utilization 1.0 +system.membus.snoop_filter.tot_requests 15340 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 +system.membus.trans_dist::ReadResp 792 +system.membus.trans_dist::ReadExReq 14548 +system.membus.trans_dist::ReadExResp 14548 +system.membus.trans_dist::ReadSharedReq 792 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 +system.membus.pkt_count::total 30680 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 +system.membus.pkt_size::total 981760 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 15340 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 15340 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 15340 +system.membus.reqLayer0.occupancy 15604500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 76700000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index c9c77a327..37e37c5a9 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout index 99db763e0..bfb274bdd 100755 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-a gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:35 -gem5 executing on e108600-lin, pid 38668 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64903 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 122215823500 because target called exit() +Exiting @ tick 122215823500 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 735a3d4df..505667cfa 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.122216 # Number of seconds simulated -sim_ticks 122215823500 # Number of ticks simulated -final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2760120 # Simulator instruction rate (inst/s) -host_op_rate 2760234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1383492525 # Simulator tick rate (ticks/s) -host_mem_usage 373928 # Number of bytes of host memory used -host_seconds 88.34 # Real time elapsed on the host -sim_insts 243825150 # Number of instructions simulated -sim_ops 243835265 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory -system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory -system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory -system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory -system.physmem.num_other::total 3886 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 443 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 122215823500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 244431648 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825150 # Number of instructions committed -system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses -system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726494 # number of integer instructions -system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written -system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read -system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711441 # number of memory refs -system.cpu.num_load_insts 82803521 # Number of load instructions -system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29302884 # Number of branches fetched -system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction -system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 244431613 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 326641931 # Transaction distribution -system.membus.trans_dist::ReadResp 326641931 # Transaction distribution -system.membus.trans_dist::WriteReq 22901951 # Transaction distribution -system.membus.trans_dist::WriteResp 22901951 # Transaction distribution -system.membus.trans_dist::SwapReq 3886 # Transaction distribution -system.membus.trans_dist::SwapResp 3886 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 349547768 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 349547768 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 349547768 # Request fanout histogram +sim_seconds 0.122216 +sim_ticks 122215823500 +final_tick 122215823500 +sim_freq 1000000000000 +host_inst_rate 1246885 +host_op_rate 1246936 +host_tick_rate 624993047 +host_mem_usage 386196 +host_seconds 195.55 +sim_insts 243825150 +sim_ops 243835265 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500 +system.physmem.bytes_read::cpu.inst 977685992 +system.physmem.bytes_read::cpu.data 328674008 +system.physmem.bytes_read::total 1306360000 +system.physmem.bytes_inst_read::cpu.inst 977685992 +system.physmem.bytes_inst_read::total 977685992 +system.physmem.bytes_written::cpu.data 91606089 +system.physmem.bytes_written::total 91606089 +system.physmem.num_reads::cpu.inst 244421498 +system.physmem.num_reads::cpu.data 82220433 +system.physmem.num_reads::total 326641931 +system.physmem.num_writes::cpu.data 22901951 +system.physmem.num_writes::total 22901951 +system.physmem.num_other::cpu.data 3886 +system.physmem.num_other::total 3886 +system.physmem.bw_read::cpu.inst 7999667834 +system.physmem.bw_read::cpu.data 2689291768 +system.physmem.bw_read::total 10688959601 +system.physmem.bw_inst_read::cpu.inst 7999667834 +system.physmem.bw_inst_read::total 7999667834 +system.physmem.bw_write::cpu.data 749543606 +system.physmem.bw_write::total 749543606 +system.physmem.bw_total::cpu.inst 7999667834 +system.physmem.bw_total::cpu.data 3438835373 +system.physmem.bw_total::total 11438503207 +system.pwrStateResidencyTicks::UNDEFINED 122215823500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 443 +system.cpu.pwrStateResidencyTicks::ON 122215823500 +system.cpu.numCycles 244431648 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 243825150 +system.cpu.committedOps 243835265 +system.cpu.num_int_alu_accesses 194726494 +system.cpu.num_fp_alu_accesses 11630 +system.cpu.num_func_calls 4252956 +system.cpu.num_conditional_control_insts 18619959 +system.cpu.num_int_insts 194726494 +system.cpu.num_fp_insts 11630 +system.cpu.num_int_register_reads 456818988 +system.cpu.num_int_register_writes 215451554 +system.cpu.num_fp_register_reads 23256 +system.cpu.num_fp_register_writes 90 +system.cpu.num_mem_refs 105711441 +system.cpu.num_load_insts 82803521 +system.cpu.num_store_insts 22907920 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 244431648 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 29302884 +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% +system.cpu.op_class::IntMult 0 0.00% 56.75% +system.cpu.op_class::IntDiv 0 0.00% 56.75% +system.cpu.op_class::FloatAdd 42 0.00% 56.75% +system.cpu.op_class::FloatCmp 0 0.00% 56.75% +system.cpu.op_class::FloatCvt 0 0.00% 56.75% +system.cpu.op_class::FloatMult 0 0.00% 56.75% +system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% +system.cpu.op_class::FloatDiv 0 0.00% 56.75% +system.cpu.op_class::FloatMisc 0 0.00% 56.75% +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% +system.cpu.op_class::SimdAdd 0 0.00% 56.75% +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% +system.cpu.op_class::SimdAlu 0 0.00% 56.75% +system.cpu.op_class::SimdCmp 0 0.00% 56.75% +system.cpu.op_class::SimdCvt 0 0.00% 56.75% +system.cpu.op_class::SimdMisc 0 0.00% 56.75% +system.cpu.op_class::SimdMult 0 0.00% 56.75% +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% +system.cpu.op_class::SimdShift 0 0.00% 56.75% +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% +system.cpu.op_class::MemRead 82803516 33.88% 90.63% +system.cpu.op_class::MemWrite 22896343 9.37% 100.00% +system.cpu.op_class::FloatMemRead 11 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 244431613 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 +system.membus.trans_dist::ReadReq 326641931 +system.membus.trans_dist::ReadResp 326641931 +system.membus.trans_dist::WriteReq 22901951 +system.membus.trans_dist::WriteResp 22901951 +system.membus.trans_dist::SwapReq 3886 +system.membus.trans_dist::SwapResp 3886 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 +system.membus.pkt_count::total 699095536 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 +system.membus.pkt_size::total 1397997177 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 349547768 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 349547768 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 349547768 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index b442fbc66..92c3012b0 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout index 42e1355e1..9dc643081 100755 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18547 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87179 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 168950040000 because target called exit() +Exiting @ tick 168950040000 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index e47781d66..eabb3db7d 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.168950 # Number of seconds simulated -sim_ticks 168950040000 # Number of ticks simulated -final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1482871 # Simulator instruction rate (inst/s) -host_op_rate 2611098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1585754680 # Simulator tick rate (ticks/s) -host_mem_usage 400496 # Number of bytes of host memory used -host_seconds 106.54 # Real time elapsed on the host -sim_insts 157988548 # Number of instructions simulated -sim_ops 278192465 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory -system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory -system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory -system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 337900081 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 8475189 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278169482 # number of integer instructions -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read -system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read -system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written -system.cpu.num_mem_refs 122219137 # number of memory refs -system.cpu.num_load_insts 90779385 # Number of load instructions -system.cpu.num_store_insts 31439752 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29309705 # Number of branches fetched -system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction -system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 278192465 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 308475611 # Transaction distribution -system.membus.trans_dist::ReadResp 308475611 # Transaction distribution -system.membus.trans_dist::WriteReq 31439752 # Transaction distribution -system.membus.trans_dist::WriteResp 31439752 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 339915363 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 339915363 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 339915363 # Request fanout histogram +sim_seconds 0.168950 +sim_ticks 168950040000 +final_tick 168950040000 +sim_freq 1000000000000 +host_inst_rate 689046 +host_op_rate 1213300 +host_tick_rate 736853372 +host_mem_usage 412400 +host_seconds 229.29 +sim_insts 157988548 +sim_ops 278192465 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.physmem.bytes_read::cpu.inst 1741569312 +system.physmem.bytes_read::cpu.data 717246013 +system.physmem.bytes_read::total 2458815325 +system.physmem.bytes_inst_read::cpu.inst 1741569312 +system.physmem.bytes_inst_read::total 1741569312 +system.physmem.bytes_written::cpu.data 243173117 +system.physmem.bytes_written::total 243173117 +system.physmem.num_reads::cpu.inst 217696164 +system.physmem.num_reads::cpu.data 90779447 +system.physmem.num_reads::total 308475611 +system.physmem.num_writes::cpu.data 31439752 +system.physmem.num_writes::total 31439752 +system.physmem.bw_read::cpu.inst 10308191179 +system.physmem.bw_read::cpu.data 4245314254 +system.physmem.bw_read::total 14553505433 +system.physmem.bw_inst_read::cpu.inst 10308191179 +system.physmem.bw_inst_read::total 10308191179 +system.physmem.bw_write::cpu.data 1439319677 +system.physmem.bw_write::total 1439319677 +system.physmem.bw_total::cpu.inst 10308191179 +system.physmem.bw_total::cpu.data 5684633931 +system.physmem.bw_total::total 15992825110 +system.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu.workload.numSyscalls 444 +system.cpu.pwrStateResidencyTicks::ON 168950040000 +system.cpu.numCycles 337900081 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 157988548 +system.cpu.committedOps 278192465 +system.cpu.num_int_alu_accesses 278169482 +system.cpu.num_fp_alu_accesses 40 +system.cpu.num_func_calls 8475189 +system.cpu.num_conditional_control_insts 18628007 +system.cpu.num_int_insts 278169482 +system.cpu.num_fp_insts 40 +system.cpu.num_int_register_reads 635379407 +system.cpu.num_int_register_writes 217447860 +system.cpu.num_fp_register_reads 40 +system.cpu.num_fp_register_writes 26 +system.cpu.num_cc_register_reads 104140596 +system.cpu.num_cc_register_writes 61764861 +system.cpu.num_mem_refs 122219137 +system.cpu.num_load_insts 90779385 +system.cpu.num_store_insts 31439752 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 337900081 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 29309705 +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% +system.cpu.op_class::IntMult 10938 0.00% 56.07% +system.cpu.op_class::IntDiv 329 0.00% 56.07% +system.cpu.op_class::FloatAdd 12 0.00% 56.07% +system.cpu.op_class::FloatCmp 0 0.00% 56.07% +system.cpu.op_class::FloatCvt 0 0.00% 56.07% +system.cpu.op_class::FloatMult 0 0.00% 56.07% +system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% +system.cpu.op_class::FloatDiv 0 0.00% 56.07% +system.cpu.op_class::FloatMisc 0 0.00% 56.07% +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% +system.cpu.op_class::SimdAdd 0 0.00% 56.07% +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% +system.cpu.op_class::SimdAlu 0 0.00% 56.07% +system.cpu.op_class::SimdCmp 0 0.00% 56.07% +system.cpu.op_class::SimdCvt 0 0.00% 56.07% +system.cpu.op_class::SimdMisc 0 0.00% 56.07% +system.cpu.op_class::SimdMult 0 0.00% 56.07% +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% +system.cpu.op_class::SimdShift 0 0.00% 56.07% +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% +system.cpu.op_class::MemRead 90779371 32.63% 88.70% +system.cpu.op_class::MemWrite 31439738 11.30% 100.00% +system.cpu.op_class::FloatMemRead 14 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 278192465 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.membus.trans_dist::ReadReq 308475611 +system.membus.trans_dist::ReadResp 308475611 +system.membus.trans_dist::WriteReq 31439752 +system.membus.trans_dist::WriteResp 31439752 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 +system.membus.pkt_count_system.cpu.icache_port::total 435392328 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 +system.membus.pkt_count::total 679830726 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 +system.membus.pkt_size::total 2701988442 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 339915363 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 339915363 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 339915363 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 8d377039e..7ee3ff550 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 29 2017 20:18:54 -gem5 started Mar 29 2017 20:19:04 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 121347 +gem5 compiled Mar 29 2017 21:12:17 +gem5 started Mar 29 2017 21:12:27 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 42630 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -81,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 126524000 because target called exit() +Exiting @ tick 126524000 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index c550cf53f..a10174db1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000127 sim_ticks 126524000 final_tick 126524000 sim_freq 1000000000000 -host_inst_rate 214440 -host_op_rate 214440 -host_tick_rate 23217304 +host_inst_rate 211101 +host_op_rate 211100 +host_tick_rate 22855727 host_mem_usage 280860 -host_seconds 5.45 +host_seconds 5.54 sim_insts 1168600 sim_ops 1168600 system.voltage_domain.voltage 1 @@ -316,7 +316,7 @@ system.cpu0.fetch.Insts 585438 system.cpu0.fetch.Branches 99156 system.cpu0.fetch.predictedBranches 90042 system.cpu0.fetch.Cycles 194902 -system.cpu0.fetch.SquashCycles 3487 +system.cpu0.fetch.SquashCycles 3486 system.cpu0.fetch.MiscStallCycles 9 system.cpu0.fetch.PendingTrapStallCycles 2371 system.cpu0.fetch.IcacheWaitRetryStallCycles 8 @@ -373,7 +373,7 @@ system.cpu0.iq.iqInstsAdded 468496 system.cpu0.iq.iqNonSpecInstsAdded 1145 system.cpu0.iq.iqInstsIssued 464441 system.cpu0.iq.iqSquashedInstsIssued 106 -system.cpu0.iq.iqSquashedInstsExamined 16686 +system.cpu0.iq.iqSquashedInstsExamined 16685 system.cpu0.iq.iqSquashedOperandsExamined 13469 system.cpu0.iq.iqSquashedNonSpecRemoved 586 system.cpu0.iq.issued_per_cycle::samples 222303 @@ -474,7 +474,7 @@ system.cpu0.iq.rate 1.835380 system.cpu0.iq.fu_busy_cnt 333 system.cpu0.iq.fu_busy_rate 0.000717 system.cpu0.iq.int_inst_queue_reads 1151624 -system.cpu0.iq.int_inst_queue_writes 486379 +system.cpu0.iq.int_inst_queue_writes 486378 system.cpu0.iq.int_inst_queue_wakeup_accesses 461879 system.cpu0.iq.fp_inst_queue_reads 0 system.cpu0.iq.fp_inst_queue_writes 0 @@ -592,7 +592,7 @@ system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% system.cpu0.commit.op_class_0::total 540180 system.cpu0.commit.bw_lim_events 456 system.cpu0.rob.rob_reads 774865 -system.cpu0.rob.rob_writes 1118644 +system.cpu0.rob.rob_writes 1118643 system.cpu0.timesIdled 329 system.cpu0.idleCycles 30746 system.cpu0.committedInsts 452871 @@ -1142,7 +1142,7 @@ system.cpu1.cpi 0.859746 system.cpu1.cpi_total 0.859746 system.cpu1.ipc 1.163134 system.cpu1.ipc_total 1.163134 -system.cpu1.int_regfile_reads 419202 +system.cpu1.int_regfile_reads 419203 system.cpu1.int_regfile_writes 195886 system.cpu1.fp_regfile_writes 64 system.cpu1.misc_regfile_reads 120419 @@ -1682,7 +1682,7 @@ system.cpu2.cpi 0.897099 system.cpu2.cpi_total 0.897099 system.cpu2.ipc 1.114704 system.cpu2.ipc_total 1.114704 -system.cpu2.int_regfile_reads 403345 +system.cpu2.int_regfile_reads 403346 system.cpu2.int_regfile_writes 188790 system.cpu2.fp_regfile_writes 64 system.cpu2.misc_regfile_reads 114754 @@ -2218,7 +2218,7 @@ system.cpu3.cpi 0.704137 system.cpu3.cpi_total 0.704137 system.cpu3.ipc 1.420178 system.cpu3.ipc_total 1.420178 -system.cpu3.int_regfile_reads 509137 +system.cpu3.int_regfile_reads 509138 system.cpu3.int_regfile_writes 236602 system.cpu3.fp_regfile_writes 64 system.cpu3.misc_regfile_reads 150205 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index d84a9f055..9aefbd6d1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer width=1 @@ -98,14 +99,14 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -119,6 +120,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -131,15 +133,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -149,14 +152,14 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -170,6 +173,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -182,15 +186,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -210,7 +215,7 @@ type=ExeTracer eventq_index=0 [system.cpu0.workload] -type=LiveProcess +type=Process cmd=test_atomic 4 cwd= drivers= @@ -219,14 +224,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -267,6 +273,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer width=1 @@ -277,14 +284,14 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -298,6 +305,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -310,15 +318,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -328,14 +337,14 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -349,6 +358,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -361,15 +371,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -423,6 +434,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer width=1 @@ -433,14 +445,14 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -454,6 +466,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -466,15 +479,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -484,14 +498,14 @@ size=64 [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -505,6 +519,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -517,15 +532,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -579,6 +595,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer width=1 @@ -589,14 +606,14 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -610,6 +627,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -622,15 +640,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -640,14 +659,14 @@ size=64 [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -661,6 +680,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -673,15 +693,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -719,14 +740,14 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -740,6 +761,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -752,15 +774,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar @@ -799,6 +822,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -806,7 +830,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.toL2Bus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr index a5c275fc8..32afe7799 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr @@ -3,4 +3,5 @@ warn: ClockedObject: More than one power state change request encountered within warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: ClockedObject: Already in the requested power state, request ignored diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index f5b06fc1f..527306347 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:37 -gem5 executing on e108600-lin, pid 38680 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +gem5 compiled Mar 29 2017 17:08:10 +gem5 started Mar 29 2017 17:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 126091 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 @@ -82,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 87707000 because target called exit() +Exiting @ tick 87707000 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index e242611fb..e21097758 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,1031 +1,1031 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 87707000 # Number of ticks simulated -final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154171 # Simulator instruction rate (inst/s) -host_op_rate 1154139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 149440007 # Simulator tick rate (ticks/s) -host_mem_usage 264052 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -sim_insts 677333 # Number of instructions simulated -sim_ops 677333 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 559 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.numSyscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 175415 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 175326 # Number of instructions committed -system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls -system.cpu0.num_int_insts 120376 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 82397 # number of memory refs -system.cpu0.num_load_insts 54591 # Number of load instructions -system.cpu0.num_store_insts 27806 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 29689 # Number of branches fetched -system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction -system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 175388 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits -system.cpu0.dcache.overall_hits::total 82008 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses -system.cpu0.dcache.overall_misses::total 328 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits -system.cpu0.icache.overall_hits::total 174921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 173297 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 167400 # Number of instructions committed -system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 633 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107326 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read -system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 49494 # number of memory refs -system.cpu1.num_load_insts 39345 # Number of load instructions -system.cpu1.num_store_insts 10149 # Number of store instructions -system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles -system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles -system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles -system.cpu1.Branches 35694 # Number of branches fetched -system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction -system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction -system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 167432 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits -system.cpu1.dcache.overall_hits::total 49120 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses -system.cpu1.dcache.overall_misses::total 287 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits -system.cpu1.icache.overall_hits::total 167074 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses -system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 278 # number of writebacks -system.cpu1.icache.writebacks::total 278 # number of writebacks -system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 173296 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 167335 # Number of instructions committed -system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 633 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls -system.cpu2.num_int_insts 114196 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read -system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59830 # number of memory refs -system.cpu2.num_load_insts 42793 # Number of load instructions -system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles -system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles -system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.Branches 32221 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction -system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction -system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 167367 # Class of executed instruction -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits -system.cpu2.dcache.overall_hits::total 59499 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses -system.cpu2.dcache.overall_misses::total 255 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits -system.cpu2.icache.overall_hits::total 167009 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses -system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 278 # number of writebacks -system.cpu2.icache.writebacks::total 278 # number of writebacks -system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 173297 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167272 # Number of instructions committed -system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 633 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls -system.cpu3.num_int_insts 113295 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 58510 # number of memory refs -system.cpu3.num_load_insts 42344 # Number of load instructions -system.cpu3.num_store_insts 16166 # Number of store instructions -system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles -system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles -system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles -system.cpu3.Branches 32639 # Number of branches fetched -system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction -system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction -system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 167304 # Class of executed instruction -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits -system.cpu3.dcache.overall_hits::total 58176 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses -system.cpu3.dcache.overall_misses::total 260 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits -system.cpu3.icache.overall_hits::total 166945 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses -system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 279 # number of writebacks -system.cpu3.icache.writebacks::total 279 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use -system.l2c.tags.total_refs 1799 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19423 # Number of tag accesses -system.l2c.tags.data_accesses 19423 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 355 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 3 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 1 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193 # Transaction distribution -system.membus.trans_dist::ReadExReq 183 # Transaction distribution -system.membus.trans_dist::ReadExResp 136 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 799 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 799 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1142 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.279735 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.218885 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 882 22.51% 60.41% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 521 13.30% 73.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram +sim_seconds 0.000088 +sim_ticks 87707000 +final_tick 87707000 +sim_freq 1000000000000 +host_inst_rate 1004816 +host_op_rate 1004778 +host_tick_rate 130103429 +host_mem_usage 276508 +host_seconds 0.67 +sim_insts 677333 +sim_ops 677333 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 +system.physmem.bytes_read::cpu0.inst 18048 +system.physmem.bytes_read::cpu0.data 10560 +system.physmem.bytes_read::cpu1.inst 3968 +system.physmem.bytes_read::cpu1.data 1280 +system.physmem.bytes_read::cpu2.inst 192 +system.physmem.bytes_read::cpu2.data 832 +system.physmem.bytes_read::cpu3.inst 64 +system.physmem.bytes_read::cpu3.data 832 +system.physmem.bytes_read::total 35776 +system.physmem.bytes_inst_read::cpu0.inst 18048 +system.physmem.bytes_inst_read::cpu1.inst 3968 +system.physmem.bytes_inst_read::cpu2.inst 192 +system.physmem.bytes_inst_read::cpu3.inst 64 +system.physmem.bytes_inst_read::total 22272 +system.physmem.num_reads::cpu0.inst 282 +system.physmem.num_reads::cpu0.data 165 +system.physmem.num_reads::cpu1.inst 62 +system.physmem.num_reads::cpu1.data 20 +system.physmem.num_reads::cpu2.inst 3 +system.physmem.num_reads::cpu2.data 13 +system.physmem.num_reads::cpu3.inst 1 +system.physmem.num_reads::cpu3.data 13 +system.physmem.num_reads::total 559 +system.physmem.bw_read::cpu0.inst 205776050 +system.physmem.bw_read::cpu0.data 120400880 +system.physmem.bw_read::cpu1.inst 45241543 +system.physmem.bw_read::cpu1.data 14594046 +system.physmem.bw_read::cpu2.inst 2189107 +system.physmem.bw_read::cpu2.data 9486130 +system.physmem.bw_read::cpu3.inst 729702 +system.physmem.bw_read::cpu3.data 9486130 +system.physmem.bw_read::total 407903588 +system.physmem.bw_inst_read::cpu0.inst 205776050 +system.physmem.bw_inst_read::cpu1.inst 45241543 +system.physmem.bw_inst_read::cpu2.inst 2189107 +system.physmem.bw_inst_read::cpu3.inst 729702 +system.physmem.bw_inst_read::total 253936402 +system.physmem.bw_total::cpu0.inst 205776050 +system.physmem.bw_total::cpu0.data 120400880 +system.physmem.bw_total::cpu1.inst 45241543 +system.physmem.bw_total::cpu1.data 14594046 +system.physmem.bw_total::cpu2.inst 2189107 +system.physmem.bw_total::cpu2.data 9486130 +system.physmem.bw_total::cpu3.inst 729702 +system.physmem.bw_total::cpu3.data 9486130 +system.physmem.bw_total::total 407903588 +system.pwrStateResidencyTicks::UNDEFINED 87707000 +system.cpu_clk_domain.clock 500 +system.cpu0.workload.numSyscalls 26 +system.cpu0.pwrStateResidencyTicks::ON 87707000 +system.cpu0.numCycles 175415 +system.cpu0.numWorkItemsStarted 0 +system.cpu0.numWorkItemsCompleted 0 +system.cpu0.committedInsts 175326 +system.cpu0.committedOps 175326 +system.cpu0.num_int_alu_accesses 120376 +system.cpu0.num_fp_alu_accesses 0 +system.cpu0.num_func_calls 390 +system.cpu0.num_conditional_control_insts 28824 +system.cpu0.num_int_insts 120376 +system.cpu0.num_fp_insts 0 +system.cpu0.num_int_register_reads 349286 +system.cpu0.num_int_register_writes 121983 +system.cpu0.num_fp_register_reads 0 +system.cpu0.num_fp_register_writes 0 +system.cpu0.num_mem_refs 82397 +system.cpu0.num_load_insts 54591 +system.cpu0.num_store_insts 27806 +system.cpu0.num_idle_cycles 0 +system.cpu0.num_busy_cycles 175415 +system.cpu0.not_idle_fraction 1 +system.cpu0.idle_fraction 0 +system.cpu0.Branches 29689 +system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% +system.cpu0.op_class::IntAlu 66491 37.91% 52.97% +system.cpu0.op_class::IntMult 0 0.00% 52.97% +system.cpu0.op_class::IntDiv 0 0.00% 52.97% +system.cpu0.op_class::FloatAdd 0 0.00% 52.97% +system.cpu0.op_class::FloatCmp 0 0.00% 52.97% +system.cpu0.op_class::FloatCvt 0 0.00% 52.97% +system.cpu0.op_class::FloatMult 0 0.00% 52.97% +system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% +system.cpu0.op_class::FloatDiv 0 0.00% 52.97% +system.cpu0.op_class::FloatMisc 0 0.00% 52.97% +system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% +system.cpu0.op_class::SimdAdd 0 0.00% 52.97% +system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% +system.cpu0.op_class::SimdAlu 0 0.00% 52.97% +system.cpu0.op_class::SimdCmp 0 0.00% 52.97% +system.cpu0.op_class::SimdCvt 0 0.00% 52.97% +system.cpu0.op_class::SimdMisc 0 0.00% 52.97% +system.cpu0.op_class::SimdMult 0 0.00% 52.97% +system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% +system.cpu0.op_class::SimdShift 0 0.00% 52.97% +system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% +system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% +system.cpu0.op_class::MemRead 54675 31.17% 84.15% +system.cpu0.op_class::MemWrite 27806 15.85% 100.00% +system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu0.op_class::IprAccess 0 0.00% 100.00% +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu0.op_class::total 175388 +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 +system.cpu0.dcache.tags.replacements 2 +system.cpu0.dcache.tags.tagsinuse 150.745705 +system.cpu0.dcache.tags.total_refs 81882 +system.cpu0.dcache.tags.sampled_refs 167 +system.cpu0.dcache.tags.avg_refs 490.311377 +system.cpu0.dcache.tags.warmup_cycle 0 +system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 +system.cpu0.dcache.tags.occ_percent::total 0.294425 +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 +system.cpu0.dcache.tags.tag_accesses 329804 +system.cpu0.dcache.tags.data_accesses 329804 +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 +system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 +system.cpu0.dcache.ReadReq_hits::total 54430 +system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 +system.cpu0.dcache.WriteReq_hits::total 27578 +system.cpu0.dcache.SwapReq_hits::cpu0.data 15 +system.cpu0.dcache.SwapReq_hits::total 15 +system.cpu0.dcache.demand_hits::cpu0.data 82008 +system.cpu0.dcache.demand_hits::total 82008 +system.cpu0.dcache.overall_hits::cpu0.data 82008 +system.cpu0.dcache.overall_hits::total 82008 +system.cpu0.dcache.ReadReq_misses::cpu0.data 151 +system.cpu0.dcache.ReadReq_misses::total 151 +system.cpu0.dcache.WriteReq_misses::cpu0.data 177 +system.cpu0.dcache.WriteReq_misses::total 177 +system.cpu0.dcache.SwapReq_misses::cpu0.data 27 +system.cpu0.dcache.SwapReq_misses::total 27 +system.cpu0.dcache.demand_misses::cpu0.data 328 +system.cpu0.dcache.demand_misses::total 328 +system.cpu0.dcache.overall_misses::cpu0.data 328 +system.cpu0.dcache.overall_misses::total 328 +system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 +system.cpu0.dcache.ReadReq_accesses::total 54581 +system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 +system.cpu0.dcache.WriteReq_accesses::total 27755 +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 +system.cpu0.dcache.SwapReq_accesses::total 42 +system.cpu0.dcache.demand_accesses::cpu0.data 82336 +system.cpu0.dcache.demand_accesses::total 82336 +system.cpu0.dcache.overall_accesses::cpu0.data 82336 +system.cpu0.dcache.overall_accesses::total 82336 +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 +system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 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+system.cpu0.icache.ReadReq_misses::total 467 +system.cpu0.icache.demand_misses::cpu0.inst 467 +system.cpu0.icache.demand_misses::total 467 +system.cpu0.icache.overall_misses::cpu0.inst 467 +system.cpu0.icache.overall_misses::total 467 +system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 +system.cpu0.icache.ReadReq_accesses::total 175388 +system.cpu0.icache.demand_accesses::cpu0.inst 175388 +system.cpu0.icache.demand_accesses::total 175388 +system.cpu0.icache.overall_accesses::cpu0.inst 175388 +system.cpu0.icache.overall_accesses::total 175388 +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 +system.cpu0.icache.ReadReq_miss_rate::total 0.002663 +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 +system.cpu0.icache.demand_miss_rate::total 0.002663 +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 +system.cpu0.icache.overall_miss_rate::total 0.002663 +system.cpu0.icache.blocked_cycles::no_mshrs 0 +system.cpu0.icache.blocked_cycles::no_targets 0 +system.cpu0.icache.blocked::no_mshrs 0 +system.cpu0.icache.blocked::no_targets 0 +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan +system.cpu0.icache.avg_blocked_cycles::no_targets nan +system.cpu0.icache.writebacks::writebacks 215 +system.cpu0.icache.writebacks::total 215 +system.cpu1.pwrStateResidencyTicks::ON 87707000 +system.cpu1.numCycles 173297 +system.cpu1.numWorkItemsStarted 0 +system.cpu1.numWorkItemsCompleted 0 +system.cpu1.committedInsts 167400 +system.cpu1.committedOps 167400 +system.cpu1.num_int_alu_accesses 107326 +system.cpu1.num_fp_alu_accesses 0 +system.cpu1.num_func_calls 633 +system.cpu1.num_conditional_control_insts 34043 +system.cpu1.num_int_insts 107326 +system.cpu1.num_fp_insts 0 +system.cpu1.num_int_register_reads 254436 +system.cpu1.num_int_register_writes 94218 +system.cpu1.num_fp_register_reads 0 +system.cpu1.num_fp_register_writes 0 +system.cpu1.num_mem_refs 49494 +system.cpu1.num_load_insts 39345 +system.cpu1.num_store_insts 10149 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+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 +system.toL2Bus.pkt_size::total 233088 +system.toL2Bus.snoops 0 +system.toL2Bus.snoopTraffic 0 +system.toL2Bus.snoop_fanout::samples 3918 +system.toL2Bus.snoop_fanout::mean 1.279735 +system.toL2Bus.snoop_fanout::stdev 1.218885 +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% +system.toL2Bus.snoop_fanout::1 882 22.51% 60.41% +system.toL2Bus.snoop_fanout::2 521 13.30% 73.71% +system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::min_value 0 +system.toL2Bus.snoop_fanout::max_value 3 +system.toL2Bus.snoop_fanout::total 3918 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 524dea641..02e1544f6 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer workload=system.cpu0.workload @@ -94,14 +95,14 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -206,7 +211,7 @@ type=ExeTracer eventq_index=0 [system.cpu0.workload] -type=LiveProcess +type=Process cmd=test_atomic 4 cwd= drivers= @@ -215,14 +220,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -260,6 +266,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer workload=system.cpu0.workload @@ -269,14 +276,14 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -290,6 +297,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -302,15 +310,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -320,14 +329,14 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -341,6 +350,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -353,15 +363,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -412,6 +423,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer workload=system.cpu0.workload @@ -421,14 +433,14 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -442,6 +454,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -454,15 +467,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -472,14 +486,14 @@ size=64 [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -493,6 +507,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -505,15 +520,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -564,6 +580,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer workload=system.cpu0.workload @@ -573,14 +590,14 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -594,6 +611,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -606,15 +624,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -624,14 +643,14 @@ size=64 [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -645,6 +664,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -657,15 +677,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -703,14 +724,14 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -724,6 +745,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -736,15 +758,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar @@ -783,6 +806,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -790,7 +814,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.toL2Bus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr index a5c275fc8..32afe7799 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr @@ -3,4 +3,5 @@ warn: ClockedObject: More than one power state change request encountered within warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: ClockedObject: Already in the requested power state, request ignored diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index dc5d474a6..771ec0419 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38675 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +gem5 compiled Mar 29 2017 17:08:10 +gem5 started Mar 29 2017 17:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 126092 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 @@ -27,59 +26,59 @@ Iteration 1 completed Iteration 2 completed [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 5, Thread 2] Got lock [Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 Iteration 5 completed +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 Iteration 8 completed -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 Iteration 9 completed -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 264174500 because target called exit() +Exiting @ tick 263409500 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index bdf146296..e816fec12 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,1659 +1,1659 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 263409500 # Number of ticks simulated -final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 870162 # Simulator instruction rate (inst/s) -host_op_rate 870149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345251596 # Simulator tick rate (ticks/s) -host_mem_usage 264052 # Number of bytes of host memory used -host_seconds 0.76 # Real time elapsed on the host -sim_insts 663871 # Number of instructions simulated -sim_ops 663871 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 36608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.numSyscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 526819 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158244 # Number of instructions committed -system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108988 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73856 # number of memory refs -system.cpu0.num_load_insts 48897 # Number of load instructions -system.cpu0.num_store_insts 24959 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26842 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158306 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits -system.cpu0.dcache.overall_hits::total 73442 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses -system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158774 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits -system.cpu0.icache.overall_hits::total 157840 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency -system.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 526818 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 169340 # Number of instructions committed -system.cpu1.committedOps 169340 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111465 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54688 # number of memory refs -system.cpu1.num_load_insts 41399 # Number of load instructions -system.cpu1.num_store_insts 13289 # Number of store instructions -system.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles -system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles -system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles -system.cpu1.Branches 34599 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction -system.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction -system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 169372 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits -system.cpu1.dcache.overall_hits::total 54340 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses -system.cpu1.dcache.overall_misses::total 269 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169739 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits -system.cpu1.icache.overall_hits::total 169007 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses -system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5703000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5703000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5703000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5703000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 280 # number of writebacks -system.cpu1.icache.writebacks::total 280 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency -system.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 526819 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165892 # Number of instructions committed -system.cpu2.committedOps 165892 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110657 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 278357 # number of times the integer registers were read -system.cpu2.num_int_register_writes 106099 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 55200 # number of memory refs -system.cpu2.num_load_insts 40995 # Number of load instructions -system.cpu2.num_store_insts 14205 # Number of store instructions -system.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles -system.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles -system.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.142231 # Percentage of idle cycles -system.cpu2.Branches 33279 # Number of branches fetched -system.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction -system.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction -system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165924 # Class of executed instruction -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits -system.cpu2.dcache.overall_hits::total 54855 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses -system.cpu2.dcache.overall_misses::total 267 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 166291 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits -system.cpu2.icache.overall_hits::total 165559 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses -system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 280 # number of writebacks -system.cpu2.icache.writebacks::total 280 # number of writebacks -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency -system.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 526818 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 170395 # Number of instructions committed -system.cpu3.committedOps 170395 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111057 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 271753 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102596 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53550 # number of memory refs -system.cpu3.num_load_insts 41191 # Number of load instructions -system.cpu3.num_store_insts 12359 # Number of store instructions -system.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles -system.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles -system.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.142747 # Percentage of idle cycles -system.cpu3.Branches 35332 # Number of branches fetched -system.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction -system.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction -system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 170427 # Class of executed instruction -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits -system.cpu3.dcache.overall_hits::total 53200 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate 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-system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5475500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5475500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5475500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5475500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5475500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 170428 # number of demand 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14919.618529 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 281 # number of writebacks -system.cpu3.icache.writebacks::total 281 # number of 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latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 470.663959 # Cycle average of tags in use -system.l2c.tags.total_refs 1794 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 572 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.136364 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.inst 230.500098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 147.566608 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.217156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10.908895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 46.660458 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 17.373358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.877256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 10.560130 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.inst 0.003517 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.002252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy 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ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50500 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195 # Transaction distribution -system.membus.trans_dist::ReadExReq 208 # Transaction distribution -system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 261 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 839 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 839 # Request fanout histogram -system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1080 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1028 # Total snoops (count) -system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.294964 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.172134 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 554986 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 431477 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) +sim_seconds 0.000263 +sim_ticks 263409500 +final_tick 263409500 +sim_freq 1000000000000 +host_inst_rate 743335 +host_op_rate 743323 +host_tick_rate 294930057 +host_mem_usage 276508 +host_seconds 0.89 +sim_insts 663871 +sim_ops 663871 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 +system.physmem.bytes_read::cpu0.inst 18240 +system.physmem.bytes_read::cpu0.data 10560 +system.physmem.bytes_read::cpu1.inst 640 +system.physmem.bytes_read::cpu1.data 960 +system.physmem.bytes_read::cpu2.inst 3712 +system.physmem.bytes_read::cpu2.data 1472 +system.physmem.bytes_read::cpu3.inst 64 +system.physmem.bytes_read::cpu3.data 960 +system.physmem.bytes_read::total 36608 +system.physmem.bytes_inst_read::cpu0.inst 18240 +system.physmem.bytes_inst_read::cpu1.inst 640 +system.physmem.bytes_inst_read::cpu2.inst 3712 +system.physmem.bytes_inst_read::cpu3.inst 64 +system.physmem.bytes_inst_read::total 22656 +system.physmem.num_reads::cpu0.inst 285 +system.physmem.num_reads::cpu0.data 165 +system.physmem.num_reads::cpu1.inst 10 +system.physmem.num_reads::cpu1.data 15 +system.physmem.num_reads::cpu2.inst 58 +system.physmem.num_reads::cpu2.data 23 +system.physmem.num_reads::cpu3.inst 1 +system.physmem.num_reads::cpu3.data 15 +system.physmem.num_reads::total 572 +system.physmem.bw_read::cpu0.inst 69245794 +system.physmem.bw_read::cpu0.data 40089670 +system.physmem.bw_read::cpu1.inst 2429677 +system.physmem.bw_read::cpu1.data 3644515 +system.physmem.bw_read::cpu2.inst 14092127 +system.physmem.bw_read::cpu2.data 5588257 +system.physmem.bw_read::cpu3.inst 242968 +system.physmem.bw_read::cpu3.data 3644515 +system.physmem.bw_read::total 138977524 +system.physmem.bw_inst_read::cpu0.inst 69245794 +system.physmem.bw_inst_read::cpu1.inst 2429677 +system.physmem.bw_inst_read::cpu2.inst 14092127 +system.physmem.bw_inst_read::cpu3.inst 242968 +system.physmem.bw_inst_read::total 86010565 +system.physmem.bw_total::cpu0.inst 69245794 +system.physmem.bw_total::cpu0.data 40089670 +system.physmem.bw_total::cpu1.inst 2429677 +system.physmem.bw_total::cpu1.data 3644515 +system.physmem.bw_total::cpu2.inst 14092127 +system.physmem.bw_total::cpu2.data 5588257 +system.physmem.bw_total::cpu3.inst 242968 +system.physmem.bw_total::cpu3.data 3644515 +system.physmem.bw_total::total 138977524 +system.pwrStateResidencyTicks::UNDEFINED 263409500 +system.cpu_clk_domain.clock 500 +system.cpu0.workload.numSyscalls 26 +system.cpu0.pwrStateResidencyTicks::ON 263409500 +system.cpu0.numCycles 526819 +system.cpu0.numWorkItemsStarted 0 +system.cpu0.numWorkItemsCompleted 0 +system.cpu0.committedInsts 158244 +system.cpu0.committedOps 158244 +system.cpu0.num_int_alu_accesses 108988 +system.cpu0.num_fp_alu_accesses 0 +system.cpu0.num_func_calls 390 +system.cpu0.num_conditional_control_insts 25977 +system.cpu0.num_int_insts 108988 +system.cpu0.num_fp_insts 0 +system.cpu0.num_int_register_reads 315122 +system.cpu0.num_int_register_writes 110594 +system.cpu0.num_fp_register_reads 0 +system.cpu0.num_fp_register_writes 0 +system.cpu0.num_mem_refs 73856 +system.cpu0.num_load_insts 48897 +system.cpu0.num_store_insts 24959 +system.cpu0.num_idle_cycles 0 +system.cpu0.num_busy_cycles 526819 +system.cpu0.not_idle_fraction 1 +system.cpu0.idle_fraction 0 +system.cpu0.Branches 26842 +system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% +system.cpu0.op_class::IntAlu 60797 38.40% 53.29% +system.cpu0.op_class::IntMult 0 0.00% 53.29% +system.cpu0.op_class::IntDiv 0 0.00% 53.29% +system.cpu0.op_class::FloatAdd 0 0.00% 53.29% +system.cpu0.op_class::FloatCmp 0 0.00% 53.29% +system.cpu0.op_class::FloatCvt 0 0.00% 53.29% +system.cpu0.op_class::FloatMult 0 0.00% 53.29% +system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% +system.cpu0.op_class::FloatDiv 0 0.00% 53.29% +system.cpu0.op_class::FloatMisc 0 0.00% 53.29% +system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% +system.cpu0.op_class::SimdAdd 0 0.00% 53.29% +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdAlu 0 0.00% 53.29% +system.cpu0.op_class::SimdCmp 0 0.00% 53.29% +system.cpu0.op_class::SimdCvt 0 0.00% 53.29% +system.cpu0.op_class::SimdMisc 0 0.00% 53.29% +system.cpu0.op_class::SimdMult 0 0.00% 53.29% +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdShift 0 0.00% 53.29% +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% +system.cpu0.op_class::MemRead 48981 30.94% 84.23% +system.cpu0.op_class::MemWrite 24959 15.77% 100.00% +system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu0.op_class::IprAccess 0 0.00% 100.00% +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu0.op_class::total 158306 +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 +system.cpu0.dcache.tags.replacements 2 +system.cpu0.dcache.tags.tagsinuse 144.946606 +system.cpu0.dcache.tags.total_refs 73324 +system.cpu0.dcache.tags.sampled_refs 167 +system.cpu0.dcache.tags.avg_refs 439.065868 +system.cpu0.dcache.tags.warmup_cycle 0 +system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 +system.cpu0.dcache.tags.occ_percent::total 0.283099 +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 +system.cpu0.dcache.tags.tag_accesses 295657 +system.cpu0.dcache.tags.data_accesses 295657 +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 +system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 +system.cpu0.dcache.ReadReq_hits::total 48717 +system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 +system.cpu0.dcache.WriteReq_hits::total 24725 +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 +system.cpu0.dcache.SwapReq_hits::total 16 +system.cpu0.dcache.demand_hits::cpu0.data 73442 +system.cpu0.dcache.demand_hits::total 73442 +system.cpu0.dcache.overall_hits::cpu0.data 73442 +system.cpu0.dcache.overall_hits::total 73442 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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 +system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 +system.membus.snoop_filter.tot_requests 839 +system.membus.snoop_filter.hit_single_requests 261 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 +system.membus.trans_dist::ReadResp 430 +system.membus.trans_dist::UpgradeReq 195 +system.membus.trans_dist::ReadExReq 208 +system.membus.trans_dist::ReadExResp 142 +system.membus.trans_dist::ReadSharedReq 430 +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 +system.membus.pkt_count::total 1405 +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 +system.membus.pkt_size::total 36608 +system.membus.snoops 261 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 839 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 839 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 839 +system.membus.reqLayer0.occupancy 587124 +system.membus.reqLayer0.utilization 0.2 +system.membus.respLayer1.occupancy 2860000 +system.membus.respLayer1.utilization 1.1 +system.toL2Bus.snoop_filter.tot_requests 3977 +system.toL2Bus.snoop_filter.hit_single_requests 1080 +system.toL2Bus.snoop_filter.hit_multi_requests 1895 +system.toL2Bus.snoop_filter.tot_snoops 0 +system.toL2Bus.snoop_filter.hit_single_snoops 0 +system.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 +system.toL2Bus.trans_dist::ReadResp 2225 +system.toL2Bus.trans_dist::WritebackDirty 1 +system.toL2Bus.trans_dist::WritebackClean 1056 +system.toL2Bus.trans_dist::CleanEvict 1 +system.toL2Bus.trans_dist::UpgradeReq 274 +system.toL2Bus.trans_dist::UpgradeResp 274 +system.toL2Bus.trans_dist::ReadExReq 420 +system.toL2Bus.trans_dist::ReadExResp 420 +system.toL2Bus.trans_dist::ReadCleanReq 1566 +system.toL2Bus.trans_dist::ReadSharedReq 659 +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 +system.toL2Bus.pkt_count::total 5868 +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 +system.toL2Bus.pkt_size::total 183616 +system.toL2Bus.snoops 1028 +system.toL2Bus.snoopTraffic 53312 +system.toL2Bus.snoop_fanout::samples 2919 +system.toL2Bus.snoop_fanout::mean 1.294964 +system.toL2Bus.snoop_fanout::stdev 1.172134 +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% +system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% +system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% +system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::min_value 0 +system.toL2Bus.snoop_fanout::max_value 3 +system.toL2Bus.snoop_fanout::total 2919 +system.toL2Bus.reqLayer0.occupancy 3053983 +system.toL2Bus.reqLayer0.utilization 1.2 +system.toL2Bus.respLayer0.occupancy 700500 +system.toL2Bus.respLayer0.utilization 0.3 +system.toL2Bus.respLayer1.occupancy 499498 +system.toL2Bus.respLayer1.utilization 0.2 +system.toL2Bus.respLayer2.occupancy 550995 +system.toL2Bus.respLayer2.utilization 0.2 +system.toL2Bus.respLayer3.occupancy 431976 +system.toL2Bus.respLayer3.utilization 0.2 +system.toL2Bus.respLayer4.occupancy 552491 +system.toL2Bus.respLayer4.utilization 0.2 +system.toL2Bus.respLayer5.occupancy 427974 +system.toL2Bus.respLayer5.utilization 0.2 +system.toL2Bus.respLayer6.occupancy 554986 +system.toL2Bus.respLayer6.utilization 0.2 +system.toL2Bus.respLayer7.occupancy 431477 +system.toL2Bus.respLayer7.utilization 0.2 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index f1a56a700..458ee3b2d 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex lendian.raw cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout index 99c3eacd0..110c7664f 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-at gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:01:37 -gem5 executing on e108600-lin, pid 24147 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54215 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 48960022500 because target called exit() +Exiting @ tick 48960022500 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 7f158a1e8..6ce3f6504 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960022500 # Number of ticks simulated -final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1769120 # Simulator instruction rate (inst/s) -host_op_rate 2262458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1221438298 # Simulator tick rate (ticks/s) -host_mem_usage 267796 # Number of bytes of host memory used -host_seconds 40.08 # Real time elapsed on the host -sim_insts 70913204 # Number of instructions simulated -sim_ops 90688159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory -system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory -system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 97920046 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913204 # Number of instructions committed -system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141479271 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 100925158 # Transaction distribution -system.membus.trans_dist::ReadResp 100941077 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 120930641 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 120930641 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 120930641 # Request fanout histogram +sim_seconds 0.048960 +sim_ticks 48960022500 +final_tick 48960022500 +sim_freq 1000000000000 +host_inst_rate 739512 +host_op_rate 945733 +host_tick_rate 510575162 +host_mem_usage 279300 +host_seconds 95.89 +sim_insts 70913204 +sim_ops 90688159 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.physmem.bytes_read::cpu.inst 312580364 +system.physmem.bytes_read::cpu.data 106573345 +system.physmem.bytes_read::total 419153709 +system.physmem.bytes_inst_read::cpu.inst 312580364 +system.physmem.bytes_inst_read::total 312580364 +system.physmem.bytes_written::cpu.data 78660211 +system.physmem.bytes_written::total 78660211 +system.physmem.num_reads::cpu.inst 78145091 +system.physmem.num_reads::cpu.data 22919730 +system.physmem.num_reads::total 101064821 +system.physmem.num_writes::cpu.data 19865820 +system.physmem.num_writes::total 19865820 +system.physmem.bw_read::cpu.inst 6384399925 +system.physmem.bw_read::cpu.data 2176742157 +system.physmem.bw_read::total 8561142083 +system.physmem.bw_inst_read::cpu.inst 6384399925 +system.physmem.bw_inst_read::total 6384399925 +system.physmem.bw_write::cpu.data 1606621218 +system.physmem.bw_write::total 1606621218 +system.physmem.bw_total::cpu.inst 6384399925 +system.physmem.bw_total::cpu.data 3783363376 +system.physmem.bw_total::total 10167763301 +system.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 1946 +system.cpu.pwrStateResidencyTicks::ON 48960022500 +system.cpu.numCycles 97920046 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 70913204 +system.cpu.committedOps 90688159 +system.cpu.num_int_alu_accesses 81528528 +system.cpu.num_fp_alu_accesses 56 +system.cpu.num_func_calls 3311620 +system.cpu.num_conditional_control_insts 9253630 +system.cpu.num_int_insts 81528528 +system.cpu.num_fp_insts 56 +system.cpu.num_int_register_reads 141479271 +system.cpu.num_int_register_writes 53916335 +system.cpu.num_fp_register_reads 36 +system.cpu.num_fp_register_writes 20 +system.cpu.num_cc_register_reads 266608097 +system.cpu.num_cc_register_writes 36877111 +system.cpu.num_mem_refs 43422001 +system.cpu.num_load_insts 22866262 +system.cpu.num_store_insts 20555739 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 97920046 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 13741468 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% +system.cpu.op_class::IntMult 80119 0.09% 52.12% +system.cpu.op_class::IntDiv 0 0.00% 52.12% +system.cpu.op_class::FloatAdd 0 0.00% 52.12% +system.cpu.op_class::FloatCmp 0 0.00% 52.12% +system.cpu.op_class::FloatCvt 0 0.00% 52.12% +system.cpu.op_class::FloatMult 0 0.00% 52.12% +system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% +system.cpu.op_class::FloatDiv 0 0.00% 52.12% +system.cpu.op_class::FloatMisc 0 0.00% 52.12% +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% +system.cpu.op_class::SimdAdd 0 0.00% 52.12% +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% +system.cpu.op_class::SimdAlu 0 0.00% 52.12% +system.cpu.op_class::SimdCmp 0 0.00% 52.12% +system.cpu.op_class::SimdCvt 0 0.00% 52.12% +system.cpu.op_class::SimdMisc 0 0.00% 52.12% +system.cpu.op_class::SimdMult 0 0.00% 52.12% +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% +system.cpu.op_class::SimdShift 0 0.00% 52.12% +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% +system.cpu.op_class::MemRead 22866242 25.21% 77.33% +system.cpu.op_class::MemWrite 20555707 22.67% 100.00% +system.cpu.op_class::FloatMemRead 20 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 90690106 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.membus.trans_dist::ReadReq 100925158 +system.membus.trans_dist::ReadResp 100941077 +system.membus.trans_dist::WriteReq 19849901 +system.membus.trans_dist::WriteResp 19849901 +system.membus.trans_dist::SoftPFReq 123744 +system.membus.trans_dist::SoftPFResp 123744 +system.membus.trans_dist::LoadLockedReq 15919 +system.membus.trans_dist::StoreCondReq 15919 +system.membus.trans_dist::StoreCondResp 15919 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 +system.membus.pkt_count::total 241861282 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 +system.membus.pkt_size::total 497813920 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 120930641 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 120930641 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 120930641 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 6aaddcbd1..fac5ea3d0 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -257,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -269,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -408,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex lendian.raw cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing drivers= @@ -417,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout index c41441e64..6f4676029 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 19:03:48 -gem5 started Nov 29 2016 19:04:15 -gem5 executing on zizzer, pid 5745 -command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54226 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 128204299500 because target called exit() +Exiting @ tick 128204299500 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index b70e9a80a..00105c43e 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,689 +1,689 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.128204 # Number of seconds simulated -sim_ticks 128204299500 # Number of ticks simulated -final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 442445 # Simulator instruction rate (inst/s) -host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 806030069 # Simulator tick rate (ticks/s) -host_mem_usage 262052 # Number of bytes of host memory used -host_seconds 159.06 # Real time elapsed on the host -sim_insts 70373651 # Number of instructions simulated -sim_ops 89847385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory -system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory -system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 256408599 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373651 # Number of instructions committed -system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328435 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42486195 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42486195 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42569752 # number of overall hits -system.cpu.dcache.overall_hits::total 42569752 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 36741 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 36741 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40187 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40187 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 143773 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 143773 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 183960 # number of overall misses -system.cpu.dcache.overall_misses::total 183960 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 594992500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6509368500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7104361000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7104361000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7104361000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7104361000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001613 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003373 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003373 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49413.735541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38619.053055 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 127926 # number of writebacks -system.cpu.dcache.writebacks::total 127926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7633 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7633 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6906535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8127427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits -system.cpu.icache.overall_hits::total 78126184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses -system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 429951000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 429951000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 429951000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 429951000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 429951000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22739.105141 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22739.105141 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16890 # number of writebacks -system.cpu.icache.writebacks::total 16890 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 411043000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 411043000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96062 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31236 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 15262 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 35948 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51210 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 15262 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 35948 # number of overall hits -system.cpu.l2cache.overall_hits::total 51210 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102320 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3646 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21730 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3646 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124050 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127696 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3646 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124050 # number of overall misses -system.cpu.l2cache.overall_misses::total 127696 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7728636500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7728636500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 127926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.713760 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.713760 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86477 # number of writebacks -system.cpu.l2cache.writebacks::total 86477 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102320 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124050 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127696 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124050 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127696 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20718208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96062 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5534528 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 274968 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025367 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 274968 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 320665000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 25376 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution -system.membus.trans_dist::CleanEvict 6466 # Transaction distribution -system.membus.trans_dist::ReadExReq 102320 # Transaction distribution -system.membus.trans_dist::ReadExResp 102320 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13707072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 127704 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 127704 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 127704 # Request fanout histogram -system.membus.reqLayer0.occupancy 569386372 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 638480000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +sim_seconds 0.128204 +sim_ticks 128204299500 +final_tick 128204299500 +sim_freq 1000000000000 +host_inst_rate 533817 +host_op_rate 681535 +host_tick_rate 972489774 +host_mem_usage 290320 +host_seconds 131.83 +sim_insts 70373651 +sim_ops 89847385 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.physmem.bytes_read::cpu.inst 233344 +system.physmem.bytes_read::cpu.data 7939200 +system.physmem.bytes_read::total 8172544 +system.physmem.bytes_inst_read::cpu.inst 233344 +system.physmem.bytes_inst_read::total 233344 +system.physmem.bytes_written::writebacks 5534528 +system.physmem.bytes_written::total 5534528 +system.physmem.num_reads::cpu.inst 3646 +system.physmem.num_reads::cpu.data 124050 +system.physmem.num_reads::total 127696 +system.physmem.num_writes::writebacks 86477 +system.physmem.num_writes::total 86477 +system.physmem.bw_read::cpu.inst 1820095 +system.physmem.bw_read::cpu.data 61926160 +system.physmem.bw_read::total 63746255 +system.physmem.bw_inst_read::cpu.inst 1820095 +system.physmem.bw_inst_read::total 1820095 +system.physmem.bw_write::writebacks 43169597 +system.physmem.bw_write::total 43169597 +system.physmem.bw_total::writebacks 43169597 +system.physmem.bw_total::cpu.inst 1820095 +system.physmem.bw_total::cpu.data 61926160 +system.physmem.bw_total::total 106915853 +system.pwrStateResidencyTicks::UNDEFINED 128204299500 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0 0.00% 0.00% +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% +system.cpu.op_class::IntMult 80119 0.09% 52.12% +system.cpu.op_class::IntDiv 0 0.00% 52.12% +system.cpu.op_class::FloatAdd 0 0.00% 52.12% +system.cpu.op_class::FloatCmp 0 0.00% 52.12% +system.cpu.op_class::FloatCvt 0 0.00% 52.12% +system.cpu.op_class::FloatMult 0 0.00% 52.12% +system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% +system.cpu.op_class::FloatDiv 0 0.00% 52.12% +system.cpu.op_class::FloatMisc 0 0.00% 52.12% +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% +system.cpu.op_class::SimdAdd 0 0.00% 52.12% +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% +system.cpu.op_class::SimdAlu 0 0.00% 52.12% +system.cpu.op_class::SimdCmp 0 0.00% 52.12% +system.cpu.op_class::SimdCvt 0 0.00% 52.12% +system.cpu.op_class::SimdMisc 0 0.00% 52.12% +system.cpu.op_class::SimdMult 0 0.00% 52.12% +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% +system.cpu.op_class::SimdShift 0 0.00% 52.12% +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% 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4075.864194 +system.cpu.dcache.tags.total_refs 42601590 +system.cpu.dcache.tags.sampled_refs 159998 +system.cpu.dcache.tags.avg_refs 266.263266 +system.cpu.dcache.tags.warmup_cycle 1116590500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 +system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 +system.cpu.dcache.tags.occ_percent::total 0.995084 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 85731098 +system.cpu.dcache.tags.data_accesses 85731098 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.dcache.ReadReq_hits::cpu.data 22743326 +system.cpu.dcache.ReadReq_hits::total 22743326 +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 +system.cpu.dcache.WriteReq_hits::total 19742869 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+system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 +system.cpu.toL2Bus.pkt_count::total 530604 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 +system.cpu.toL2Bus.pkt_size::total 20718208 +system.cpu.toL2Bus.snoops 96062 +system.cpu.toL2Bus.snoopTraffic 5534528 +system.cpu.toL2Bus.snoop_fanout::samples 274968 +system.cpu.toL2Bus.snoop_fanout::mean 0.025367 +system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% +system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 274968 +system.cpu.toL2Bus.reqLayer0.occupancy 320665000 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 28362000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 239997000 +system.cpu.toL2Bus.respLayer1.utilization 0.2 +system.membus.snoop_filter.tot_requests 220672 +system.membus.snoop_filter.hit_single_requests 93041 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.membus.trans_dist::ReadResp 25376 +system.membus.trans_dist::WritebackDirty 86477 +system.membus.trans_dist::CleanEvict 6466 +system.membus.trans_dist::ReadExReq 102320 +system.membus.trans_dist::ReadExResp 102320 +system.membus.trans_dist::ReadSharedReq 25376 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 +system.membus.pkt_count::total 348335 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 +system.membus.pkt_size::total 13707072 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 127704 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 127704 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 127704 +system.membus.reqLayer0.occupancy 569386372 +system.membus.reqLayer0.utilization 0.4 +system.membus.respLayer1.occupancy 638480000 +system.membus.respLayer1.utilization 0.5 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 3a4f61f9d..325da9e41 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex bendian.raw cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr index e38712610..d418fa117 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -1,563 +1,565 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall time(4026527848, ...) -warn: ignoring syscall time(4026527400, ...) -warn: ignoring syscall time(4026527312, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527288, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526960, ...) -warn: ignoring syscall time(4026527040, ...) -warn: ignoring syscall time(4026527000, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526312, ...) -warn: ignoring syscall time(4026526832, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526936, ...) -warn: ignoring syscall time(4026527008, ...) -warn: ignoring syscall time(4026526560, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall time(4026526632, ...) -warn: ignoring syscall time(4026526736, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527744, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026527096, ...) -warn: ignoring syscall time(4026526648, ...) -warn: ignoring syscall time(4026526824, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026526056, ...) -warn: ignoring syscall time(4026527512, ...) -warn: ignoring syscall time(4026525760, ...) +info: Entering event queue @ 0. Starting simulation... +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +info: Increasing stack size by one page. +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 09707d695..92f95a99b 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:35 -gem5 executing on e108600-lin, pid 38667 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:43:58 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66518 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 68148677000 because target called exit() +Exiting @ tick 68148677000 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index eb352a8fe..e5f6b910a 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148677000 # Number of ticks simulated -final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2768800 # Simulator instruction rate (inst/s) -host_op_rate 2804650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1403953412 # Simulator tick rate (ticks/s) -host_mem_usage 249976 # Number of bytes of host memory used -host_seconds 48.54 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory -system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory -system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 68148677000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 136297355 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction -system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction -system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 171784880 # Transaction distribution -system.membus.trans_dist::ReadResp 171784880 # Transaction distribution -system.membus.trans_dist::WriteReq 20864304 # Transaction distribution -system.membus.trans_dist::WriteResp 20864304 # Transaction distribution -system.membus.trans_dist::SwapReq 15916 # Transaction distribution -system.membus.trans_dist::SwapResp 15916 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 192665100 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 192665100 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 192665100 # Request fanout histogram +sim_seconds 0.068149 +sim_ticks 68148677000 +final_tick 68148677000 +sim_freq 1000000000000 +host_inst_rate 1228497 +host_op_rate 1244404 +host_tick_rate 622924579 +host_mem_usage 262248 +host_seconds 109.40 +sim_insts 134398959 +sim_ops 136139187 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 68148677000 +system.physmem.bytes_read::cpu.inst 538214320 +system.physmem.bytes_read::cpu.data 147559360 +system.physmem.bytes_read::total 685773680 +system.physmem.bytes_inst_read::cpu.inst 538214320 +system.physmem.bytes_inst_read::total 538214320 +system.physmem.bytes_written::cpu.data 89882950 +system.physmem.bytes_written::total 89882950 +system.physmem.num_reads::cpu.inst 134553580 +system.physmem.num_reads::cpu.data 37231300 +system.physmem.num_reads::total 171784880 +system.physmem.num_writes::cpu.data 20864304 +system.physmem.num_writes::total 20864304 +system.physmem.num_other::cpu.data 15916 +system.physmem.num_other::total 15916 +system.physmem.bw_read::cpu.inst 7897648842 +system.physmem.bw_read::cpu.data 2165256414 +system.physmem.bw_read::total 10062905256 +system.physmem.bw_inst_read::cpu.inst 7897648842 +system.physmem.bw_inst_read::total 7897648842 +system.physmem.bw_write::cpu.data 1318924357 +system.physmem.bw_write::total 1318924357 +system.physmem.bw_total::cpu.inst 7897648842 +system.physmem.bw_total::cpu.data 3484180771 +system.physmem.bw_total::total 11381829614 +system.pwrStateResidencyTicks::UNDEFINED 68148677000 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 1946 +system.cpu.pwrStateResidencyTicks::ON 68148677000 +system.cpu.numCycles 136297355 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 134398959 +system.cpu.committedOps 136139187 +system.cpu.num_int_alu_accesses 115187757 +system.cpu.num_fp_alu_accesses 2326976 +system.cpu.num_func_calls 1709332 +system.cpu.num_conditional_control_insts 8898968 +system.cpu.num_int_insts 115187757 +system.cpu.num_fp_insts 2326976 +system.cpu.num_int_register_reads 263032419 +system.cpu.num_int_register_writes 113147731 +system.cpu.num_fp_register_reads 4725606 +system.cpu.num_fp_register_writes 1150968 +system.cpu.num_mem_refs 58160261 +system.cpu.num_load_insts 37275864 +system.cpu.num_store_insts 20884397 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 136297355 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 12719094 +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% +system.cpu.op_class::IntMult 0 0.00% 57.07% +system.cpu.op_class::IntDiv 0 0.00% 57.07% +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% +system.cpu.op_class::FloatCmp 0 0.00% 57.31% +system.cpu.op_class::FloatCvt 0 0.00% 57.31% +system.cpu.op_class::FloatMult 0 0.00% 57.31% +system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% +system.cpu.op_class::FloatDiv 0 0.00% 57.31% +system.cpu.op_class::FloatMisc 0 0.00% 57.31% +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% +system.cpu.op_class::SimdAdd 0 0.00% 57.31% +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% +system.cpu.op_class::SimdAlu 0 0.00% 57.31% +system.cpu.op_class::SimdCmp 0 0.00% 57.31% +system.cpu.op_class::SimdCvt 0 0.00% 57.31% +system.cpu.op_class::SimdMisc 0 0.00% 57.31% +system.cpu.op_class::SimdMult 0 0.00% 57.31% +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% +system.cpu.op_class::SimdShift 0 0.00% 57.31% +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% +system.cpu.op_class::MemRead 37046611 27.18% 84.49% +system.cpu.op_class::MemWrite 19133112 14.04% 98.53% +system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% +system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 136293808 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000 +system.membus.trans_dist::ReadReq 171784880 +system.membus.trans_dist::ReadResp 171784880 +system.membus.trans_dist::WriteReq 20864304 +system.membus.trans_dist::WriteResp 20864304 +system.membus.trans_dist::SwapReq 15916 +system.membus.trans_dist::SwapResp 15916 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 +system.membus.pkt_count::total 385330200 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 +system.membus.pkt_size::total 775783958 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 192665100 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 192665100 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 192665100 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 14d66f92a..129a63c1e 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex bendian.raw cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr index e38712610..d418fa117 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -1,563 +1,565 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall time(4026527848, ...) -warn: ignoring syscall time(4026527400, ...) -warn: ignoring syscall time(4026527312, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527288, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526960, ...) -warn: ignoring syscall time(4026527040, ...) -warn: ignoring syscall time(4026527000, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526312, ...) -warn: ignoring syscall time(4026526832, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526936, ...) -warn: ignoring syscall time(4026527008, ...) -warn: ignoring syscall time(4026526560, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall time(4026526632, ...) -warn: ignoring syscall time(4026526736, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527744, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026527096, ...) -warn: ignoring syscall time(4026526648, ...) -warn: ignoring syscall time(4026526824, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026526056, ...) -warn: ignoring syscall time(4026527512, ...) -warn: ignoring syscall time(4026525760, ...) +info: Entering event queue @ 0. Starting simulation... +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +info: Increasing stack size by one page. +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: 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times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout index 8920b4c6b..da084e8e1 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:38 -gem5 executing on e108600-lin, pid 38688 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:55 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 65144 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 203115946500 because target called exit() +Exiting @ tick 203260902500 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 2c0880e3e..aec377294 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,558 +1,558 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.203261 # Number of seconds simulated -sim_ticks 203260902500 # Number of ticks simulated -final_tick 203260902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1825324 # Simulator instruction rate (inst/s) -host_op_rate 1848958 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2760562270 # Simulator tick rate (ticks/s) -host_mem_usage 261500 # Number of bytes of host memory used -host_seconds 73.63 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 526720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7845184 # Number of bytes read from this memory -system.physmem.bytes_read::total 8371904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 526720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 526720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5476224 # Number of bytes written to this memory -system.physmem.bytes_written::total 5476224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 85566 # Number of write requests responded to by this memory -system.physmem.num_writes::total 85566 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2591349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38596621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41187970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2591349 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2591349 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26941846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26941846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26941846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2591349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38596621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68129817 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 406521805 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 406521804.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction -system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction -system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 146583 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.215868 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 829975500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.215868 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 462 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3598 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits -system.cpu.dcache.overall_hits::total 57944940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses -system.cpu.dcache.overall_misses::total 150664 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1655141000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1655141000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433166000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6433166000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 446000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 446000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8088307000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8088307000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8088307000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8088307000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36376.725275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36376.725275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61172.701685 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61172.701685 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29733.333333 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 29733.333333 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53684.403706 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53684.403706 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 123615 # number of writebacks -system.cpu.dcache.writebacks::total 123615 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1609641000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1609641000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6328002000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6328002000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 431000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 431000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7937643000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7937643000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7937643000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7937643000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35376.725275 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35376.725275 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60172.701685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60172.701685 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28733.333333 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28733.333333 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.091327 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 144688165500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.091327 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978560 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978560 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses -system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits -system.cpu.icache.overall_hits::total 134366557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses -system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2844752500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2844752500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2844752500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2844752500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2844752500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2844752500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15210.628048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15210.628048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15210.628048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15210.628048 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 184976 # number of writebacks -system.cpu.icache.writebacks::total 184976 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2657728500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2657728500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2657728500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2657728500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2657728500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2657728500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14210.628048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14210.628048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 99926 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32138.485238 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 536406 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 132694 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.042428 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 26729442000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 711.528666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3108.349977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28318.606595 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.094859 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.864215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.980789 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 570 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10913 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20279 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 818 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5486262 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5486262 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 123615 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 123615 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3868 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3868 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178794 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 178794 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24230 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 24230 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 178794 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28098 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 206892 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 178794 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 28098 # number of overall hits -system.cpu.l2cache.overall_hits::total 206892 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 101311 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101311 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8230 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8230 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21270 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21270 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8230 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122581 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130811 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8230 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122581 # number of overall misses -system.cpu.l2cache.overall_misses::total 130811 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6130000500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6130000500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 498248500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 498248500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1286927500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1286927500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 498248500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7416928000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7915176500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 498248500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7416928000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7915176500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 123615 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 123615 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.963225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.044005 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.044005 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.467473 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.467473 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.044005 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.813524 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.387355 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.044005 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.813524 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.387355 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60506.761359 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60506.761359 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60540.522479 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60540.522479 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60504.348848 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60504.348848 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60508.493170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60508.493170 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 85566 # number of writebacks -system.cpu.l2cache.writebacks::total 85566 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101311 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101311 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8230 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8230 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21270 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21270 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122581 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130811 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8230 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122581 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130811 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5116890500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5116890500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 415948500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 415948500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1074227500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1074227500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 415948500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6191118000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6607066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 415948500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6191118000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6607066500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044005 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.467473 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.467473 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.387355 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.387355 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50506.761359 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50506.761359 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50540.522479 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50540.522479 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50504.348848 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50504.348848 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3837 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3837 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 37328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 99926 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5476224 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 437629 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008919 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 437629 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 643222000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 226995 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 96184 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 29500 # Transaction distribution -system.membus.trans_dist::WritebackDirty 85566 # Transaction distribution -system.membus.trans_dist::CleanEvict 10618 # Transaction distribution -system.membus.trans_dist::ReadExReq 101311 # Transaction distribution -system.membus.trans_dist::ReadExResp 101311 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 29500 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 357806 # Packet count per connected master and slave (bytes) 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+system.cpu.toL2Bus.trans_dist::ReadResp 232524 +system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 +system.cpu.toL2Bus.trans_dist::WritebackClean 184976 +system.cpu.toL2Bus.trans_dist::CleanEvict 37328 +system.cpu.toL2Bus.trans_dist::ReadExReq 105179 +system.cpu.toL2Bus.trans_dist::ReadExResp 105179 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 +system.cpu.toL2Bus.pkt_count::total 1006965 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 +system.cpu.toL2Bus.pkt_size::total 41362816 +system.cpu.toL2Bus.snoops 99926 +system.cpu.toL2Bus.snoopTraffic 5476224 +system.cpu.toL2Bus.snoop_fanout::samples 437629 +system.cpu.toL2Bus.snoop_fanout::mean 0.008919 +system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% +system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 437629 +system.cpu.toL2Bus.reqLayer0.occupancy 643222000 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 280536000 +system.cpu.toL2Bus.respLayer0.utilization 0.1 +system.cpu.toL2Bus.respLayer1.occupancy 226018500 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 226995 +system.membus.snoop_filter.hit_single_requests 96184 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 +system.membus.trans_dist::ReadResp 29500 +system.membus.trans_dist::WritebackDirty 85566 +system.membus.trans_dist::CleanEvict 10618 +system.membus.trans_dist::ReadExReq 101311 +system.membus.trans_dist::ReadExResp 101311 +system.membus.trans_dist::ReadSharedReq 29500 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 +system.membus.pkt_count::total 357806 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128 +system.membus.pkt_size::total 13848128 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 130811 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 130811 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 130811 +system.membus.reqLayer0.occupancy 570211500 +system.membus.reqLayer0.utilization 0.3 +system.membus.respLayer1.occupancy 654055000 +system.membus.respLayer1.utilization 0.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index ac8a9f7d1..dba628374 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout index 5f855da74..15f6a3cf8 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -3,21 +3,19 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:25 -gem5 executing on e108600-lin, pid 23093 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:00:23 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54878 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-atomic Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sav Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -26,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 99596491500 because target called exit() +122 123 124 Exiting @ tick 99596491500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index de3dba60e..9f00c41e3 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.099596 # Number of seconds simulated -sim_ticks 99596491500 # Number of ticks simulated -final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2182343 # Simulator instruction rate (inst/s) -host_op_rate 2300541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1261356268 # Simulator tick rate (ticks/s) -host_mem_usage 263320 # Number of bytes of host memory used -host_seconds 78.96 # Real time elapsed on the host -sim_insts 172317410 # Number of instructions simulated -sim_ops 181650342 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory -system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory -system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory -system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 199192984 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317410 # Number of instructions committed -system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls -system.cpu.num_int_insts 143085668 # number of integer instructions -system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 238310719 # number of times the integer registers were read -system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written -system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read -system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written -system.cpu.num_mem_refs 40540779 # number of memory refs -system.cpu.num_load_insts 27896144 # Number of load instructions -system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300312 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27348059 15.06% 92.74% # Class of executed instruction -system.cpu.op_class::MemWrite 12498389 6.88% 99.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650743 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 217614903 # Transaction distribution -system.membus.trans_dist::ReadResp 217637310 # Transaction distribution -system.membus.trans_dist::WriteReq 12364287 # Transaction distribution -system.membus.trans_dist::WriteResp 12364287 # Transaction distribution -system.membus.trans_dist::SoftPFReq 463 # Transaction distribution -system.membus.trans_dist::SoftPFResp 463 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 230024467 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 230024467 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 230024467 # Request fanout histogram +sim_seconds 0.099596 +sim_ticks 99596491500 +final_tick 99596491500 +sim_freq 1000000000000 +host_inst_rate 936229 +host_op_rate 986937 +host_tick_rate 541124372 +host_mem_usage 274820 +host_seconds 184.05 +sim_insts 172317410 +sim_ops 181650342 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.physmem.bytes_read::cpu.inst 759440208 +system.physmem.bytes_read::cpu.data 110533661 +system.physmem.bytes_read::total 869973869 +system.physmem.bytes_inst_read::cpu.inst 759440208 +system.physmem.bytes_inst_read::total 759440208 +system.physmem.bytes_written::cpu.data 45252940 +system.physmem.bytes_written::total 45252940 +system.physmem.num_reads::cpu.inst 189860052 +system.physmem.num_reads::cpu.data 27777721 +system.physmem.num_reads::total 217637773 +system.physmem.num_writes::cpu.data 12386694 +system.physmem.num_writes::total 12386694 +system.physmem.bw_read::cpu.inst 7625170290 +system.physmem.bw_read::cpu.data 1109814807 +system.physmem.bw_read::total 8734985097 +system.physmem.bw_inst_read::cpu.inst 7625170290 +system.physmem.bw_inst_read::total 7625170290 +system.physmem.bw_write::cpu.data 454362792 +system.physmem.bw_write::total 454362792 +system.physmem.bw_total::cpu.inst 7625170290 +system.physmem.bw_total::cpu.data 1564177600 +system.physmem.bw_total::total 9189347890 +system.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 400 +system.cpu.pwrStateResidencyTicks::ON 99596491500 +system.cpu.numCycles 199192984 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 172317410 +system.cpu.committedOps 181650342 +system.cpu.num_int_alu_accesses 143085668 +system.cpu.num_fp_alu_accesses 1752310 +system.cpu.num_func_calls 3545028 +system.cpu.num_conditional_control_insts 32201008 +system.cpu.num_int_insts 143085668 +system.cpu.num_fp_insts 1752310 +system.cpu.num_int_register_reads 238310719 +system.cpu.num_int_register_writes 98192342 +system.cpu.num_fp_register_reads 2822225 +system.cpu.num_fp_register_writes 2378039 +system.cpu.num_cc_register_reads 543309970 +system.cpu.num_cc_register_writes 190815535 +system.cpu.num_mem_refs 40540779 +system.cpu.num_load_insts 27896144 +system.cpu.num_store_insts 12644635 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 199192984 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 40300312 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 138988213 76.51% 76.51% +system.cpu.op_class::IntMult 908940 0.50% 77.01% +system.cpu.op_class::IntDiv 0 0.00% 77.01% +system.cpu.op_class::FloatAdd 0 0.00% 77.01% +system.cpu.op_class::FloatCmp 0 0.00% 77.01% +system.cpu.op_class::FloatCvt 0 0.00% 77.01% +system.cpu.op_class::FloatMult 0 0.00% 77.01% +system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% +system.cpu.op_class::FloatDiv 0 0.00% 77.01% +system.cpu.op_class::FloatMisc 0 0.00% 77.01% +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% +system.cpu.op_class::SimdAdd 0 0.00% 77.01% +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% +system.cpu.op_class::SimdAlu 0 0.00% 77.01% +system.cpu.op_class::SimdCmp 0 0.00% 77.01% +system.cpu.op_class::SimdCvt 0 0.00% 77.01% +system.cpu.op_class::SimdMisc 0 0.00% 77.01% +system.cpu.op_class::SimdMult 0 0.00% 77.01% +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% +system.cpu.op_class::SimdShift 0 0.00% 77.01% +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% +system.cpu.op_class::MemRead 27348059 15.06% 92.74% +system.cpu.op_class::MemWrite 12498389 6.88% 99.62% +system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% +system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 181650743 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.membus.trans_dist::ReadReq 217614903 +system.membus.trans_dist::ReadResp 217637310 +system.membus.trans_dist::WriteReq 12364287 +system.membus.trans_dist::WriteResp 12364287 +system.membus.trans_dist::SoftPFReq 463 +system.membus.trans_dist::SoftPFResp 463 +system.membus.trans_dist::LoadLockedReq 22407 +system.membus.trans_dist::StoreCondReq 22407 +system.membus.trans_dist::StoreCondResp 22407 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 +system.membus.pkt_count::total 460048934 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 +system.membus.pkt_size::total 915226809 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 230024467 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 230024467 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 230024467 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 4b53ac3b8..5b49b590a 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout index c9961e3be..07d5ab013 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -3,21 +3,19 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:45:16 -gem5 executing on e108600-lin, pid 23175 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:57:55 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54318 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-timing Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sav Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -26,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 230197694500 because target called exit() +122 123 124 Exiting @ tick 230201146500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 59d720796..fa75e6a0d 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,669 +1,669 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.230201 # Number of seconds simulated -sim_ticks 230201146500 # Number of ticks simulated -final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1601768 # Simulator instruction rate (inst/s) -host_op_rate 1688668 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145736650 # Simulator tick rate (ticks/s) -host_mem_usage 273052 # Number of bytes of host memory used -host_seconds 107.28 # Real time elapsed on the host -sim_insts 171842484 # Number of instructions simulated -sim_ops 181165371 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory -system.physmem.bytes_read::total 220992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 479303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 479303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 959995 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 460402293 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842484 # Number of instructions committed -system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls -system.cpu.num_int_insts 143085668 # number of integer instructions -system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 238631773 # number of times the integer registers were read -system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written -system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read -system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written -system.cpu.num_mem_refs 40540779 # number of memory refs -system.cpu.num_load_insts 27896144 # Number of load instructions -system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460402292.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300312 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27348059 15.06% 92.74% # Class of executed instruction -system.cpu.op_class::MemWrite 12498389 6.88% 99.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650743 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.564425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.564425 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332901 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332901 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits -system.cpu.dcache.overall_hits::total 40117812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses -system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40571000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40571000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 68930500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 68930500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 109501500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 109501500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 109501500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 109501500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61242.449664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61208.216881 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles 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-system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39883000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39883000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67830500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67830500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 107713500 # number of demand (read+write) MSHR miss cycles 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-system.cpu.icache.tags.occ_blocks::cpu.inst 1147.953271 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560524 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560524 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses -system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits -system.cpu.icache.overall_hits::total 189857002 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses -system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 126321000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 126321000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 126321000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 126321000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 126321000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 126321000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) 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latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41403.146509 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41403.146509 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1506 # number of writebacks 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MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123270000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 123270000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40403.146509 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40403.146509 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2511.620011 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2869 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3453 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.830872 # Average number of references to valid blocks. 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-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2517 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.105377 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 54029 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 54029 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number 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# number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 104697000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38261500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38261500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 104697000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 104358000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 209055000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 104697000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 104358000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 209055000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 689 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 689 # number of ReadSharedReq accesses(hits+misses) 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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60553.499132 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60540.348101 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60540.348101 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60543.006082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60543.006082 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55176500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55176500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87407000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87407000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31941500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31941500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87407000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87118000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 174525000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87407000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87118000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 174525000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3453 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 2361 # Transaction distribution -system.membus.trans_dist::ReadExReq 1092 # Transaction distribution -system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3453 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.230201 +sim_ticks 230201146500 +final_tick 230201146500 +sim_freq 1000000000000 +host_inst_rate 699032 +host_op_rate 736956 +host_tick_rate 936426495 +host_mem_usage 284812 +host_seconds 245.83 +sim_insts 171842484 +sim_ops 181165371 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.physmem.bytes_read::cpu.inst 110656 +system.physmem.bytes_read::cpu.data 110336 +system.physmem.bytes_read::total 220992 +system.physmem.bytes_inst_read::cpu.inst 110656 +system.physmem.bytes_inst_read::total 110656 +system.physmem.num_reads::cpu.inst 1729 +system.physmem.num_reads::cpu.data 1724 +system.physmem.num_reads::total 3453 +system.physmem.bw_read::cpu.inst 480693 +system.physmem.bw_read::cpu.data 479303 +system.physmem.bw_read::total 959995 +system.physmem.bw_inst_read::cpu.inst 480693 +system.physmem.bw_inst_read::total 480693 +system.physmem.bw_total::cpu.inst 480693 +system.physmem.bw_total::cpu.data 479303 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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 +system.cpu.toL2Bus.snoop_filter.tot_requests 6386 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.cpu.toL2Bus.trans_dist::ReadResp 3740 +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 +system.cpu.toL2Bus.trans_dist::WritebackClean 1506 +system.cpu.toL2Bus.trans_dist::CleanEvict 24 +system.cpu.toL2Bus.trans_dist::ReadExReq 1100 +system.cpu.toL2Bus.trans_dist::ReadExResp 1100 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 +system.cpu.toL2Bus.pkt_count::total 11226 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 +system.cpu.toL2Bus.pkt_size::total 407168 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 4840 +system.cpu.toL2Bus.snoop_fanout::mean 0.033471 +system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% +system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 4840 +system.cpu.toL2Bus.reqLayer0.occupancy 4715000 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 4576500 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 2683500 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 3453 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.membus.trans_dist::ReadResp 2361 +system.membus.trans_dist::ReadExReq 1092 +system.membus.trans_dist::ReadExResp 1092 +system.membus.trans_dist::ReadSharedReq 2361 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 +system.membus.pkt_count::total 6906 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 +system.membus.pkt_size::total 220992 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 3453 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 3453 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 3453 +system.membus.reqLayer0.occupancy 3601500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 17265000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 3fd1ef26a..a38ce2f6f 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 87c7a18cb..22a19a069 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -3,15 +3,14 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38671 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:37 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64822 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -25,5 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -info: Increasing stack size by one page. -122 123 124 Exiting @ tick 96722945000 because target called exit() +122 123 124 Exiting @ tick 96722945000 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index be67f7e8e..e75fdc7de 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096723 # Number of seconds simulated -sim_ticks 96722945000 # Number of ticks simulated -final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2624723 # Simulator instruction rate (inst/s) -host_op_rate 2624726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1312370434 # Simulator tick rate (ticks/s) -host_mem_usage 246444 # Number of bytes of host memory used -host_seconds 73.70 # Real time elapsed on the host -sim_insts 193444518 # Number of instructions simulated -sim_ops 193444756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory -system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory -system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory -system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory -system.physmem.num_other::total 22406 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 401 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 96722945000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193445891 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444518 # Number of instructions committed -system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974806 # number of integer instructions -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733958 # number of memory refs -system.cpu.num_load_insts 57735091 # Number of load instructions -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 15132745 # Number of branches fetched -system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction -system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction -system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction -system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 193445773 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 251180603 # Transaction distribution -system.membus.trans_dist::ReadResp 251180603 # Transaction distribution -system.membus.trans_dist::WriteReq 18976439 # Transaction distribution -system.membus.trans_dist::WriteResp 18976439 # Transaction distribution -system.membus.trans_dist::SwapReq 22406 # Transaction distribution -system.membus.trans_dist::SwapResp 22406 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 270179448 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 270179448 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 270179448 # Request fanout histogram +sim_seconds 0.096723 +sim_ticks 96722945000 +final_tick 96722945000 +sim_freq 1000000000000 +host_inst_rate 1253206 +host_op_rate 1253207 +host_tick_rate 626607046 +host_mem_usage 258716 +host_seconds 154.36 +sim_insts 193444518 +sim_ops 193444756 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 96722945000 +system.physmem.bytes_read::cpu.inst 773782140 +system.physmem.bytes_read::cpu.data 223463413 +system.physmem.bytes_read::total 997245553 +system.physmem.bytes_inst_read::cpu.inst 773782140 +system.physmem.bytes_inst_read::total 773782140 +system.physmem.bytes_written::cpu.data 72065412 +system.physmem.bytes_written::total 72065412 +system.physmem.num_reads::cpu.inst 193445535 +system.physmem.num_reads::cpu.data 57735068 +system.physmem.num_reads::total 251180603 +system.physmem.num_writes::cpu.data 18976439 +system.physmem.num_writes::total 18976439 +system.physmem.num_other::cpu.data 22406 +system.physmem.num_other::total 22406 +system.physmem.bw_read::cpu.inst 7999985319 +system.physmem.bw_read::cpu.data 2310345420 +system.physmem.bw_read::total 10310330739 +system.physmem.bw_inst_read::cpu.inst 7999985319 +system.physmem.bw_inst_read::total 7999985319 +system.physmem.bw_write::cpu.data 745070490 +system.physmem.bw_write::total 745070490 +system.physmem.bw_total::cpu.inst 7999985319 +system.physmem.bw_total::cpu.data 3055415910 +system.physmem.bw_total::total 11055401229 +system.pwrStateResidencyTicks::UNDEFINED 96722945000 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 401 +system.cpu.pwrStateResidencyTicks::ON 96722945000 +system.cpu.numCycles 193445891 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 193444518 +system.cpu.committedOps 193444756 +system.cpu.num_int_alu_accesses 167974806 +system.cpu.num_fp_alu_accesses 1970372 +system.cpu.num_func_calls 1957920 +system.cpu.num_conditional_control_insts 8665106 +system.cpu.num_int_insts 167974806 +system.cpu.num_fp_insts 1970372 +system.cpu.num_int_register_reads 352617941 +system.cpu.num_int_register_writes 163060124 +system.cpu.num_fp_register_reads 3181089 +system.cpu.num_fp_register_writes 2974850 +system.cpu.num_mem_refs 76733958 +system.cpu.num_load_insts 57735091 +system.cpu.num_store_insts 18998867 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 193445891 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 15132745 +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% +system.cpu.op_class::IntMult 0 0.00% 59.88% +system.cpu.op_class::IntDiv 0 0.00% 59.88% +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% +system.cpu.op_class::FloatCmp 0 0.00% 60.33% +system.cpu.op_class::FloatCvt 0 0.00% 60.33% +system.cpu.op_class::FloatMult 0 0.00% 60.33% +system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% +system.cpu.op_class::FloatDiv 0 0.00% 60.33% +system.cpu.op_class::FloatMisc 0 0.00% 60.33% +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% +system.cpu.op_class::SimdAdd 0 0.00% 60.33% +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% +system.cpu.op_class::SimdAlu 0 0.00% 60.33% +system.cpu.op_class::SimdCmp 0 0.00% 60.33% +system.cpu.op_class::SimdCvt 0 0.00% 60.33% +system.cpu.op_class::SimdMisc 0 0.00% 60.33% +system.cpu.op_class::SimdMult 0 0.00% 60.33% +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% +system.cpu.op_class::SimdShift 0 0.00% 60.33% +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% +system.cpu.op_class::MemRead 56837780 29.38% 89.71% +system.cpu.op_class::MemWrite 18800854 9.72% 99.43% +system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% +system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 193445773 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 +system.membus.trans_dist::ReadReq 251180603 +system.membus.trans_dist::ReadResp 251180603 +system.membus.trans_dist::WriteReq 18976439 +system.membus.trans_dist::WriteResp 18976439 +system.membus.trans_dist::SwapReq 22406 +system.membus.trans_dist::SwapResp 22406 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 +system.membus.pkt_count::total 540358896 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 +system.membus.pkt_size::total 1069490213 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 270179448 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 270179448 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 270179448 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index f82285b56..02b45e3d3 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout index fcd3cff78..ba3d0f65e 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -3,15 +3,14 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38674 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:39 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64871 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -25,5 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270599529500 because target called exit() +122 123 124 Exiting @ tick 270604702500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index a594c0ddc..dadd27923 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,536 +1,536 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270605 # Number of seconds simulated -sim_ticks 270604702500 # Number of ticks simulated -final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1830893 # Simulator instruction rate (inst/s) -host_op_rate 1830895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2561189341 # Simulator tick rate (ticks/s) -host_mem_usage 255916 # Number of bytes of host memory used -host_seconds 105.66 # Real time elapsed on the host -sim_insts 193444518 # Number of instructions simulated -sim_ops 193444756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory -system.physmem.bytes_read::total 331072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 401 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 541209405 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444518 # Number of instructions committed -system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974806 # number of integer instructions -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733958 # number of memory refs -system.cpu.num_load_insts 57735091 # Number of load instructions -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 15132745 # Number of branches fetched -system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction -system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction -system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction -system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 193445773 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits -system.cpu.dcache.overall_hits::total 76709932 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses -system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2 # number of writebacks -system.cpu.dcache.writebacks::total 2 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses -system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits -system.cpu.icache.overall_hits::total 193433248 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses -system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10362 # number of writebacks -system.cpu.icache.writebacks::total 10362 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits -system.cpu.l2cache.overall_hits::total 8691 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses -system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4095 # Transaction distribution -system.membus.trans_dist::ReadExReq 1078 # Transaction distribution -system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5173 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # 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+system.cpu.toL2Bus.trans_dist::ReadResp 12786 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 +system.cpu.toL2Bus.trans_dist::WritebackClean 10362 +system.cpu.toL2Bus.trans_dist::ReadExReq 1078 +system.cpu.toL2Bus.trans_dist::ReadExResp 1078 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 +system.cpu.toL2Bus.pkt_count::total 38092 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 +system.cpu.toL2Bus.pkt_size::total 1550592 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 13864 +system.cpu.toL2Bus.snoop_fanout::mean 0.000072 +system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 13864 +system.cpu.toL2Bus.reqLayer0.occupancy 22478000 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 18432000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 2364000 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 5173 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 +system.membus.trans_dist::ReadResp 4095 +system.membus.trans_dist::ReadExReq 1078 +system.membus.trans_dist::ReadExResp 1078 +system.membus.trans_dist::ReadSharedReq 4095 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 +system.membus.pkt_count::total 10346 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 +system.membus.pkt_size::total 331072 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 5173 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 5173 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 5173 +system.membus.reqLayer0.occupancy 5203000 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 25865000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index f53bc72d5..f29a800e1 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr index aadc3d011..094173d40 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout index f40711d5c..c05a3785d 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -3,22 +3,19 @@ Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18540 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87172 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -27,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 131393279000 because target called exit() +122 123 124 Exiting @ tick 131393279000 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index fba8c2c09..78c52ebfd 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131393 # Number of seconds simulated -sim_ticks 131393279000 # Number of ticks simulated -final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1535006 # Simulator instruction rate (inst/s) -host_op_rate 2572810 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1527126307 # Simulator tick rate (ticks/s) -host_mem_usage 288212 # Number of bytes of host memory used -host_seconds 86.04 # Real time elapsed on the host -sim_insts 132071193 # Number of instructions simulated -sim_ops 221363385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory -system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory -system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 262786559 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 1595632 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 219019986 # number of integer instructions -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read -system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read -system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written -system.cpu.num_mem_refs 77165304 # number of memory refs -system.cpu.num_load_insts 56649587 # Number of load instructions -system.cpu.num_store_insts 20515717 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12326938 # Number of branches fetched -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction -system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction -system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 221363385 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 230176372 # Transaction distribution -system.membus.trans_dist::ReadResp 230176372 # Transaction distribution -system.membus.trans_dist::WriteReq 20515731 # Transaction distribution -system.membus.trans_dist::WriteResp 20515731 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 250692103 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 250692103 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 250692103 # Request fanout histogram +sim_seconds 0.131393 +sim_ticks 131393279000 +final_tick 131393279000 +sim_freq 1000000000000 +host_inst_rate 712720 +host_op_rate 1194584 +host_tick_rate 709061486 +host_mem_usage 300116 +host_seconds 185.31 +sim_insts 132071193 +sim_ops 221363385 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.physmem.bytes_read::cpu.inst 1387954936 +system.physmem.bytes_read::cpu.data 310423752 +system.physmem.bytes_read::total 1698378688 +system.physmem.bytes_inst_read::cpu.inst 1387954936 +system.physmem.bytes_inst_read::total 1387954936 +system.physmem.bytes_written::cpu.data 99822191 +system.physmem.bytes_written::total 99822191 +system.physmem.num_reads::cpu.inst 173494367 +system.physmem.num_reads::cpu.data 56682005 +system.physmem.num_reads::total 230176372 +system.physmem.num_writes::cpu.data 20515731 +system.physmem.num_writes::total 20515731 +system.physmem.bw_read::cpu.inst 10563363260 +system.physmem.bw_read::cpu.data 2362554267 +system.physmem.bw_read::total 12925917527 +system.physmem.bw_inst_read::cpu.inst 10563363260 +system.physmem.bw_inst_read::total 10563363260 +system.physmem.bw_write::cpu.data 759720678 +system.physmem.bw_write::total 759720678 +system.physmem.bw_total::cpu.inst 10563363260 +system.physmem.bw_total::cpu.data 3122274945 +system.physmem.bw_total::total 13685638205 +system.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu.workload.numSyscalls 400 +system.cpu.pwrStateResidencyTicks::ON 131393279000 +system.cpu.numCycles 262786559 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 132071193 +system.cpu.committedOps 221363385 +system.cpu.num_int_alu_accesses 219019986 +system.cpu.num_fp_alu_accesses 2162459 +system.cpu.num_func_calls 1595632 +system.cpu.num_conditional_control_insts 8268466 +system.cpu.num_int_insts 219019986 +system.cpu.num_fp_insts 2162459 +system.cpu.num_int_register_reads 519996939 +system.cpu.num_int_register_writes 201355989 +system.cpu.num_fp_register_reads 3037165 +system.cpu.num_fp_register_writes 1831403 +system.cpu.num_cc_register_reads 96962463 +system.cpu.num_cc_register_writes 56242058 +system.cpu.num_mem_refs 77165304 +system.cpu.num_load_insts 56649587 +system.cpu.num_store_insts 20515717 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 262786559 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 12326938 +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% +system.cpu.op_class::IntAlu 134111833 60.58% 61.12% +system.cpu.op_class::IntMult 772953 0.35% 61.47% +system.cpu.op_class::IntDiv 7031501 3.18% 64.64% +system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% +system.cpu.op_class::FloatCmp 0 0.00% 65.14% +system.cpu.op_class::FloatCvt 0 0.00% 65.14% +system.cpu.op_class::FloatMult 0 0.00% 65.14% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% +system.cpu.op_class::FloatDiv 0 0.00% 65.14% +system.cpu.op_class::FloatMisc 0 0.00% 65.14% +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% +system.cpu.op_class::SimdAdd 0 0.00% 65.14% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% +system.cpu.op_class::SimdAlu 0 0.00% 65.14% +system.cpu.op_class::SimdCmp 0 0.00% 65.14% +system.cpu.op_class::SimdCvt 0 0.00% 65.14% +system.cpu.op_class::SimdMisc 0 0.00% 65.14% +system.cpu.op_class::SimdMult 0 0.00% 65.14% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% +system.cpu.op_class::SimdShift 0 0.00% 65.14% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% +system.cpu.op_class::MemRead 55945136 25.27% 90.41% +system.cpu.op_class::MemWrite 20410230 9.22% 99.63% +system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% +system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 221363385 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.membus.trans_dist::ReadReq 230176372 +system.membus.trans_dist::ReadResp 230176372 +system.membus.trans_dist::WriteReq 20515731 +system.membus.trans_dist::WriteResp 20515731 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 +system.membus.pkt_count_system.cpu.icache_port::total 346988734 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 +system.membus.pkt_count_system.cpu.dcache_port::total 154395472 +system.membus.pkt_count::total 501384206 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 +system.membus.pkt_size_system.cpu.icache_port::total 1387954936 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 +system.membus.pkt_size_system.cpu.dcache_port::total 410245943 +system.membus.pkt_size::total 1798200879 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 250692103 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 250692103 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 250692103 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini index d04de745f..66b18ed6d 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr index aadc3d011..094173d40 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout index 6626953b4..cd651257e 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -3,22 +3,19 @@ Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:18 -gem5 executing on e108600-lin, pid 18557 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87178 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -27,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250987138500 because target called exit() +122 123 124 Exiting @ tick 250991873500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 466f07521..225096fb5 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,531 +1,531 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250992 # Number of seconds simulated -sim_ticks 250991873500 # Number of ticks simulated -final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067110 # Simulator instruction rate (inst/s) -host_op_rate 1788574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2027966293 # Simulator tick rate (ticks/s) -host_mem_usage 298984 # Number of bytes of host memory used -host_seconds 123.77 # Real time elapsed on the host -sim_insts 132071193 # Number of instructions simulated -sim_ops 221363385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory -system.physmem.bytes_read::total 303040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 501983747 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 1595632 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 219019986 # number of integer instructions -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read -system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read -system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written -system.cpu.num_mem_refs 77165304 # number of memory refs -system.cpu.num_load_insts 56649587 # Number of load instructions -system.cpu.num_store_insts 20515717 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12326938 # Number of branches fetched -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction -system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction -system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 221363385 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits -system.cpu.dcache.overall_hits::total 77195831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses -system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7 # number of writebacks -system.cpu.dcache.writebacks::total 7 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses -system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits -system.cpu.icache.overall_hits::total 173489673 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses -system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2836 # number of writebacks -system.cpu.icache.writebacks::total 2836 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits -system.cpu.l2cache.overall_hits::total 1864 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses -system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 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+system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 4735 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.membus.trans_dist::ReadResp 3160 +system.membus.trans_dist::ReadExReq 1575 +system.membus.trans_dist::ReadExResp 1575 +system.membus.trans_dist::ReadSharedReq 3160 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 +system.membus.pkt_count::total 9470 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 +system.membus.pkt_size::total 303040 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 4735 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 4735 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 4735 +system.membus.reqLayer0.occupancy 4771000 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 23675000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- |