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authorNilay Vaish <nilay@cs.wisc.edu>2014-10-11 16:18:51 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-10-11 16:18:51 -0500
commit1efe42fa97ed03662666cafee1b9dec9dfe524e9 (patch)
treedd35dfa8f257445840ea3afe71ebdce4d8e4030e /tests/quick
parent8e07b36d2b6c1db8c4196336acc66d16e63f8ff3 (diff)
downloadgem5-1efe42fa97ed03662666cafee1b9dec9dfe524e9.tar.xz
stats: updates due to changes to x86, stale configs.
Diffstat (limited to 'tests/quick')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini16
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini13
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini43
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini43
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini243
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini32
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini270
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini62
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini37
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini91
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt622
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini121
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt1962
-rw-r--r--tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini20
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini44
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini40
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini43
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini40
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini42
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini48
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout72
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini19
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout60
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini7
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr150
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini21
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr147
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/config.ini10
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest/simerr146
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini35
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini2
79 files changed, 3557 insertions, 2418 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index c53360e80..ee9b56ccf 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -84,9 +84,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -217,9 +214,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -393,7 +387,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -474,11 +468,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -539,10 +534,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -611,6 +607,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1066,6 +1063,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 23c1b6367..3f9a7bd5f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -84,9 +84,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -224,10 +221,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -306,7 +304,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -352,11 +350,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -478,6 +477,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -933,6 +933,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 39f3dd971..f7c4e30f8 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -379,7 +379,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -460,11 +460,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -492,8 +493,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -502,6 +528,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -515,19 +542,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -555,10 +589,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -627,6 +662,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1082,6 +1118,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index dfa1ea355..e05c30aba 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -217,10 +217,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -299,7 +300,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -345,11 +346,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -377,8 +379,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -387,6 +414,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -400,19 +428,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -501,6 +536,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -956,6 +992,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 9cd433cc2..2198282f2 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -37,7 +37,7 @@ load_offset=0
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
@@ -124,9 +124,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -143,14 +140,14 @@ icache_port=system.cpu0.icache.cpu_side
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -158,15 +155,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
[system.cpu0.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -196,7 +193,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
@@ -213,40 +210,40 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
[system.cpu0.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
[system.cpu0.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -305,7 +302,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
@@ -322,7 +319,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
[system.cpu0.tracer]
type=ExeTracer
@@ -330,7 +391,7 @@ eventq_index=0
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
@@ -355,9 +416,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -374,14 +432,14 @@ icache_port=system.cpu1.icache.cpu_side
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -389,15 +447,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
[system.cpu1.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -427,7 +485,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
@@ -444,40 +502,40 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
[system.cpu1.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
[system.cpu1.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -536,7 +594,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
@@ -553,7 +611,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
[system.cpu1.tracer]
type=ExeTracer
@@ -581,13 +703,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -612,7 +734,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -661,11 +783,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -706,12 +829,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -766,6 +889,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -850,6 +974,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -1168,15 +1302,16 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
[system.vncserver]
type=VncServer
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 33ea68a30..77c7c4efb 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -124,9 +124,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -360,10 +357,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -396,13 +394,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -427,7 +425,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -441,11 +439,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -486,12 +485,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -546,6 +545,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -630,6 +630,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index bfa4aa6e3..a2ee5f35a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -37,7 +37,7 @@ load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
@@ -136,14 +136,14 @@ icache_port=system.cpu0.icache.cpu_side
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -151,15 +151,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
[system.cpu0.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -189,7 +189,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
@@ -206,40 +206,40 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
[system.cpu0.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
[system.cpu0.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -298,7 +298,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
@@ -315,7 +315,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
[system.cpu0.tracer]
type=ExeTracer
@@ -323,7 +387,7 @@ eventq_index=0
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
@@ -360,14 +424,14 @@ icache_port=system.cpu1.icache.cpu_side
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -375,15 +439,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
[system.cpu1.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -413,7 +477,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
@@ -430,40 +494,40 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
[system.cpu1.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
[system.cpu1.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -522,7 +586,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
@@ -539,7 +603,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
[system.cpu1.tracer]
type=ExeTracer
@@ -567,13 +695,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -598,7 +726,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -647,11 +775,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -679,8 +808,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -689,6 +843,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -702,19 +857,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -722,12 +884,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -782,6 +944,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -866,6 +1029,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -1184,15 +1357,16 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
[system.vncserver]
type=VncServer
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 04e6b79a5..2c07f27f5 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -353,10 +353,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -389,13 +390,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -420,7 +421,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -434,11 +435,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -466,8 +468,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -476,6 +503,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -489,19 +517,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -509,12 +544,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -569,6 +604,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -653,6 +689,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index a17b68bb8..3b28bd981 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -37,7 +37,7 @@ load_offset=0
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@@ -124,9 +124,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -355,9 +352,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -501,13 +495,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -532,7 +526,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -581,11 +575,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -626,12 +621,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -686,6 +681,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -770,6 +766,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -1088,10 +1094,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 607c8b43e..9627624a2 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -75,7 +75,7 @@ type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
req_size=16
resp_size=16
master=system.iobus.slave[0]
@@ -114,9 +114,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -357,10 +354,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -389,8 +387,8 @@ transition_latency=100000000
[system.e820_table]
type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
eventq_index=0
[system.e820_table.entries0]
@@ -416,6 +414,13 @@ size=133169152
[system.e820_table.entries3]
type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
addr=4294901760
eventq_index=0
range_type=2
@@ -464,13 +469,13 @@ version=17
[system.intel_mp_table.base_entries02]
type=X86IntelMPBus
bus_id=0
-bus_type=ISA
+bus_type=PCI
eventq_index=0
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=1
-bus_type=PCI
+bus_type=ISA
eventq_index=0
[system.intel_mp_table.base_entries04]
@@ -480,7 +485,7 @@ dest_io_apic_intin=16
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
source_bus_irq=16
trigger=ConformTrigger
@@ -491,7 +496,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -502,7 +507,7 @@ dest_io_apic_intin=2
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -513,7 +518,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -524,7 +529,7 @@ dest_io_apic_intin=1
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -535,7 +540,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -546,7 +551,7 @@ dest_io_apic_intin=3
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -557,7 +562,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -568,7 +573,7 @@ dest_io_apic_intin=4
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -579,7 +584,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -590,7 +595,7 @@ dest_io_apic_intin=5
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -601,7 +606,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -612,7 +617,7 @@ dest_io_apic_intin=6
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -623,7 +628,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -634,7 +639,7 @@ dest_io_apic_intin=7
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -645,7 +650,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -656,7 +661,7 @@ dest_io_apic_intin=8
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -667,7 +672,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -678,7 +683,7 @@ dest_io_apic_intin=9
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -689,7 +694,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -700,7 +705,7 @@ dest_io_apic_intin=10
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -711,7 +716,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -722,7 +727,7 @@ dest_io_apic_intin=11
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -733,7 +738,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -744,7 +749,7 @@ dest_io_apic_intin=12
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -755,7 +760,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -766,7 +771,7 @@ dest_io_apic_intin=13
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -777,7 +782,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
@@ -788,15 +793,15 @@ dest_io_apic_intin=14
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
eventq_index=0
-parent_bus=1
+parent_bus=0
subtractive_decode=true
[system.intrctrl]
@@ -805,7 +810,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -851,11 +856,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1100,6 +1106,7 @@ HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=9223372036854775808
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index ec6df0068..52d540f15 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,105 +1,105 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.112127 # Number of seconds simulated
-sim_ticks 5112126720000 # Number of ticks simulated
-final_tick 5112126720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.112155 # Number of seconds simulated
+sim_ticks 5112155173500 # Number of ticks simulated
+final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1627732 # Simulator instruction rate (inst/s)
-host_op_rate 3332615 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41616843658 # Simulator tick rate (ticks/s)
-host_mem_usage 647148 # Number of bytes of host memory used
-host_seconds 122.84 # Real time elapsed on the host
-sim_insts 199947158 # Number of instructions simulated
-sim_ops 409371517 # Number of ops (including micro ops) simulated
+host_inst_rate 1096092 # Simulator instruction rate (inst/s)
+host_op_rate 2244090 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28012193632 # Simulator tick rate (ticks/s)
+host_mem_usage 637772 # Number of bytes of host memory used
+host_seconds 182.50 # Real time elapsed on the host
+sim_insts 200033988 # Number of instructions simulated
+sim_ops 409540726 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 852352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10669504 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11550592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 852352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 852352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6285632 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9275712 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 13318 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 166711 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 180478 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 98213 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 144933 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 166731 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2087097 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2259449 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 166731 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 166731 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1229553 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 584899 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1814453 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1229553 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 590445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 166731 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2087097 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4073902 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 13903648 # Transaction distribution
-system.membus.trans_dist::ReadResp 13903648 # Transaction distribution
-system.membus.trans_dist::WriteReq 13796 # Transaction distribution
-system.membus.trans_dist::WriteResp 13796 # Transaction distribution
-system.membus.trans_dist::Writeback 98213 # Transaction distribution
+system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 13903768 # Transaction distribution
+system.membus.trans_dist::ReadResp 13903768 # Transaction distribution
+system.membus.trans_dist::WriteReq 13911 # Transaction distribution
+system.membus.trans_dist::WriteResp 13911 # Transaction distribution
+system.membus.trans_dist::Writeback 98349 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2521 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2092 # Transaction distribution
-system.membus.trans_dist::ReadExReq 134490 # Transaction distribution
-system.membus.trans_dist::ReadExResp 134485 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution
+system.membus.trans_dist::ReadExReq 134620 # Transaction distribution
+system.membus.trans_dist::ReadExResp 134615 # Transaction distribution
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20043728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462901 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28204873 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 28303521 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10027982 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17807872 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43232339 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 46287315 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 328402 # Request fanout histogram
+system.membus.snoop_fanout::samples 328677 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 328402 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 328402 # Request fanout histogram
+system.membus.snoop_fanout::total 328677 # Request fanout histogram
system.iocache.tags.replacements 47573 # number of replacements
system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4994846765009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
@@ -151,10 +151,10 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 10011915 # Transaction distribution
-system.iobus.trans_dist::ReadResp 10011915 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57577 # Transaction distribution
-system.iobus.trans_dist::WriteResp 10857 # Transaction distribution
+system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution
+system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57692 # Transaction distribution
+system.iobus.trans_dist::WriteResp 10972 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
@@ -170,18 +170,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27352 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 20043728 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 20142376 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
@@ -194,49 +194,49 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13676 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 10027982 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 13062574 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 10224257410 # number of cpu cycles simulated
+system.cpu.numCycles 10224314318 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 199947158 # Number of instructions committed
-system.cpu.committedOps 409371517 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 374392167 # Number of integer alu accesses
+system.cpu.committedInsts 200033988 # Number of instructions committed
+system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 2307997 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 39978602 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374392167 # number of integer instructions
+system.cpu.num_func_calls 2308777 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls
+system.cpu.num_int_insts 374550150 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 682348609 # number of times the integer registers were read
-system.cpu.num_int_register_writes 323388730 # number of times the integer registers were written
+system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read
+system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 233729759 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 157242019 # number of times the CC registers were written
-system.cpu.num_mem_refs 35671209 # number of memory refs
-system.cpu.num_load_insts 27243676 # Number of load instructions
-system.cpu.num_store_insts 8427533 # Number of store instructions
-system.cpu.num_idle_cycles 9770491320.524229 # Number of idle cycles
-system.cpu.num_busy_cycles 453766089.475771 # Number of busy cycles
-system.cpu.not_idle_fraction 0.044381 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.955619 # Percentage of idle cycles
-system.cpu.Branches 43128209 # Number of branches fetched
-system.cpu.op_class::No_OpClass 175380 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 373258577 91.18% 91.22% # Class of executed instruction
-system.cpu.op_class::IntMult 144442 0.04% 91.26% # Class of executed instruction
-system.cpu.op_class::IntDiv 122944 0.03% 91.29% # Class of executed instruction
+system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written
+system.cpu.num_mem_refs 35680563 # number of memory refs
+system.cpu.num_load_insts 27249389 # Number of load instructions
+system.cpu.num_store_insts 8431174 # Number of store instructions
+system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles
+system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles
+system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.955601 # Percentage of idle cycles
+system.cpu.Branches 43145769 # Number of branches fetched
+system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction
+system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction
+system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
@@ -263,54 +263,54 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::MemRead 27243676 6.65% 97.94% # Class of executed instruction
-system.cpu.op_class::MemWrite 8427533 2.06% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction
+system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 409372552 # Class of executed instruction
+system.cpu.op_class::total 409541761 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.tags.replacements 791918 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 243546972 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 792430 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 307.341938 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 791952 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 245131846 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 245131846 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 243546972 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 243546972 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 243546972 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 243546972 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 243546972 # number of overall hits
-system.cpu.icache.overall_hits::total 243546972 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 792437 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 792437 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 792437 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 792437 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 792437 # number of overall misses
-system.cpu.icache.overall_misses::total 792437 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 244339409 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 244339409 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 244339409 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 244339409 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 244339409 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 244339409 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits
+system.cpu.icache.overall_hits::total 243645979 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses
+system.cpu.icache.overall_misses::total 792471 # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -321,12 +321,12 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse 3.026447 # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5102112149000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026447 # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
@@ -376,13 +376,13 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu
system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements 8177 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 5.013955 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 12514 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 8191 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.527774 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5101283486500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013955 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
@@ -390,32 +390,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 53146 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 53146 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12515 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 12515 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12515 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 12515 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12515 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 12515 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9372 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 9372 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9372 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 9372 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9372 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 9372 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21887 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 21887 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21887 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 21887 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21887 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 21887 # number of overall (read+write) accesses
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-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428199 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428199 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428199 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428199 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428199 # miss rate for overall accesses
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+system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses
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+system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses
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+system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses
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+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -424,14 +424,14 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 2797 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 2797 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1623316 # number of replacements
+system.cpu.dcache.tags.replacements 1623441 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 20184260 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1623828 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.430048 # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
@@ -441,48 +441,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 233
system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 88856245 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 88856245 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 12022868 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 12022868 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8100233 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8100233 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 58899 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 58899 # number of SoftPFReq hits
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-system.cpu.dcache.overall_hits::total 20182000 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 905995 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 317045 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 317045 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 403061 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 403061 # number of SoftPFReq misses
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-system.cpu.dcache.demand_misses::total 1223040 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 1626101 # number of overall misses
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-system.cpu.dcache.ReadReq_accesses::total 12928863 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 8417278 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.SoftPFReq_accesses::total 461960 # number of SoftPFReq accesses(hits+misses)
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-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872502 # miss rate for SoftPFReq accesses
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-system.cpu.dcache.overall_miss_rate::total 0.074564 # miss rate for overall accesses
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+system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits
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+system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses
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+system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses
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+system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -491,59 +491,59 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1536734 # number of writebacks
-system.cpu.dcache.writebacks::total 1536734 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks
+system.cpu.dcache.writebacks::total 1536849 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 15972635 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 15972635 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13796 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13796 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1540333 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2260 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2260 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 314785 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 314785 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584874 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32530908 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21541 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 34147285 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50715968 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227701267 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 279540499 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 48008 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4020451 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.108195 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3972823 98.82% 98.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4020451 # Request fanout histogram
-system.cpu.l2cache.tags.replacements 106060 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 64822.097552 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3461863 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 170171 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 20.343437 # Average number of references to valid blocks.
+system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram
+system.cpu.l2cache.tags.replacements 106197 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 51909.062113 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.551712 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.348992 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.792069 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.159032 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.989107 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
@@ -551,88 +551,88 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 32243624 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 32243624 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7334 # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 779106 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1276189 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2065966 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1540333 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1540333 # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 180012 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 180012 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 7334 # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 779106 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1456201 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2245978 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 7334 # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 779106 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1456201 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2245978 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 13318 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 32226 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 45550 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 1809 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 1809 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 134768 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 134768 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 13318 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 166994 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 180318 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 13318 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 166994 # number of overall misses
-system.cpu.l2cache.overall_misses::total 180318 # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7335 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses
+system.cpu.l2cache.overall_misses::total 180453 # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 792424 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1308415 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2111516 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1540333 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1540333 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1831 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 314780 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 314780 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7335 # number of demand (read+write) accesses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 792424 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1623195 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2426296 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7335 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 792424 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1623195 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2426296 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024630 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.021572 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987985 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987985 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428134 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.428134 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.102880 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.074318 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.102880 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.074318 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -641,8 +641,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 98213 # number of writebacks
-system.cpu.l2cache.writebacks::total 98213 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks
+system.cpu.l2cache.writebacks::total 98349 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 59e823df9..2bc3edd20 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -75,7 +75,7 @@ type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
req_size=16
resp_size=16
master=system.iobus.slave[0]
@@ -350,10 +350,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -382,8 +383,8 @@ transition_latency=100000000
[system.e820_table]
type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
eventq_index=0
[system.e820_table.entries0]
@@ -409,6 +410,13 @@ size=133169152
[system.e820_table.entries3]
type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
addr=4294901760
eventq_index=0
range_type=2
@@ -457,13 +465,13 @@ version=17
[system.intel_mp_table.base_entries02]
type=X86IntelMPBus
bus_id=0
-bus_type=ISA
+bus_type=PCI
eventq_index=0
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=1
-bus_type=PCI
+bus_type=ISA
eventq_index=0
[system.intel_mp_table.base_entries04]
@@ -473,7 +481,7 @@ dest_io_apic_intin=16
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
source_bus_irq=16
trigger=ConformTrigger
@@ -484,7 +492,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -495,7 +503,7 @@ dest_io_apic_intin=2
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -506,7 +514,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -517,7 +525,7 @@ dest_io_apic_intin=1
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -528,7 +536,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -539,7 +547,7 @@ dest_io_apic_intin=3
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -550,7 +558,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -561,7 +569,7 @@ dest_io_apic_intin=4
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -572,7 +580,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -583,7 +591,7 @@ dest_io_apic_intin=5
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -594,7 +602,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -605,7 +613,7 @@ dest_io_apic_intin=6
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -616,7 +624,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -627,7 +635,7 @@ dest_io_apic_intin=7
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -638,7 +646,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -649,7 +657,7 @@ dest_io_apic_intin=8
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -660,7 +668,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -671,7 +679,7 @@ dest_io_apic_intin=9
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -682,7 +690,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -693,7 +701,7 @@ dest_io_apic_intin=10
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -704,7 +712,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -715,7 +723,7 @@ dest_io_apic_intin=11
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -726,7 +734,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -737,7 +745,7 @@ dest_io_apic_intin=12
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -748,7 +756,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -759,7 +767,7 @@ dest_io_apic_intin=13
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -770,7 +778,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
@@ -781,15 +789,15 @@ dest_io_apic_intin=14
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
eventq_index=0
-parent_bus=1
+parent_bus=0
subtractive_decode=true
[system.intrctrl]
@@ -798,7 +806,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -844,11 +852,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1093,6 +1102,7 @@ HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=9223372036854775808
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1383,8 +1393,33 @@ pio=system.iobus.master[9]
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1393,6 +1428,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1406,19 +1442,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index c82f08e25..89c62f3e3 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,121 +1,121 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.192511 # Number of seconds simulated
-sim_ticks 5192511044000 # Number of ticks simulated
-final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.194411 # Number of seconds simulated
+sim_ticks 5194410635000 # Number of ticks simulated
+final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1399863 # Simulator instruction rate (inst/s)
-host_op_rate 2698503 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56649883486 # Simulator tick rate (ticks/s)
-host_mem_usage 595716 # Number of bytes of host memory used
-host_seconds 91.66 # Real time elapsed on the host
-sim_insts 128310974 # Number of instructions simulated
-sim_ops 247343919 # Number of ops (including micro ops) simulated
+host_inst_rate 693425 # Simulator instruction rate (inst/s)
+host_op_rate 1336696 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28047460404 # Simulator tick rate (ticks/s)
+host_mem_usage 637768 # Number of bytes of host memory used
+host_seconds 185.20 # Real time elapsed on the host
+sim_insts 128422722 # Number of instructions simulated
+sim_ops 247557000 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 155196 # Number of read requests accepted
-system.physmem.writeReqs 127063 # Number of write requests accepted
-system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 155585 # Number of read requests accepted
+system.physmem.writeReqs 127186 # Number of write requests accepted
+system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9957440 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8139904 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 230 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10479 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9637 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10137 # Per bank write bursts
-system.physmem.perBankRdBursts::3 9789 # Per bank write bursts
-system.physmem.perBankRdBursts::4 9555 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9513 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9351 # Per bank write bursts
-system.physmem.perBankRdBursts::7 9512 # Per bank write bursts
-system.physmem.perBankRdBursts::8 9073 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8991 # Per bank write bursts
-system.physmem.perBankRdBursts::10 9630 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9438 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9550 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10095 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10146 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10025 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8301 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8002 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8301 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8212 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7990 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7535 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7392 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7734 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7444 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7612 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7970 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7896 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8102 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8416 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8297 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7835 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 1629 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10087 # Per bank write bursts
+system.physmem.perBankRdBursts::1 9924 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10111 # Per bank write bursts
+system.physmem.perBankRdBursts::3 9612 # Per bank write bursts
+system.physmem.perBankRdBursts::4 10046 # Per bank write bursts
+system.physmem.perBankRdBursts::5 9507 # Per bank write bursts
+system.physmem.perBankRdBursts::6 9544 # Per bank write bursts
+system.physmem.perBankRdBursts::7 9545 # Per bank write bursts
+system.physmem.perBankRdBursts::8 9177 # Per bank write bursts
+system.physmem.perBankRdBursts::9 9299 # Per bank write bursts
+system.physmem.perBankRdBursts::10 9268 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9485 # Per bank write bursts
+system.physmem.perBankRdBursts::12 9621 # Per bank write bursts
+system.physmem.perBankRdBursts::13 9970 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10158 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10001 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8060 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7801 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7998 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7765 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8116 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7896 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7662 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7717 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7519 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7838 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7675 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7654 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8493 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8626 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8402 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7944 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
-system.physmem.totGap 5192510980500 # Total gap between requests
+system.physmem.totGap 5194410571500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 155196 # Read request sizes (log2)
+system.physmem.readPktSize::6 155585 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 127063 # Write request sizes (log2)
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-system.physmem.rdQLenPdf::1 2962 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
@@ -159,259 +159,261 @@ system.physmem.wrQLenPdf::11 1 # Wh
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-system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads
-system.physmem.totQLat 1558594500 # Total ticks spent queuing
-system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5932 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5932 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.437289 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.381245 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 13.855005 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::total 5932 # Writes before turning the bus around for reads
+system.physmem.totQLat 1472209750 # Total ticks spent queuing
+system.physmem.totMemAccLat 4385116000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 776775000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9476.42 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 28226.42 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing
-system.physmem.readRowHits 125976 # Number of row buffer hits during reads
-system.physmem.writeRowHits 98691 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes
-system.physmem.avgGap 18396263.65 # Average gap between requests
-system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states
-system.physmem.memoryStateTime::REF 173389320000 # Time in different power states
+system.physmem.avgWrQLen 21.88 # Average write queue length when enqueuing
+system.physmem.readRowHits 127796 # Number of row buffer hits during reads
+system.physmem.writeRowHits 98753 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.64 # Row buffer hit rate for writes
+system.physmem.avgGap 18369672.18 # Average gap between requests
+system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4972956663750 # Time in different power states
+system.physmem.memoryStateTime::REF 173452760000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states
+system.physmem.memoryStateTime::ACT 48001096250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 214242840 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 218884680 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 116898375 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 119431125 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 608189400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 600186600 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 411266160 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 411946560 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 339149509920 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 339149509920 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 134171647065 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 134426407995 # Energy for active background per rank (pJ)
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-system.physmem.preBackEnergy::1 2997588229500 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 3472483457760 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 3472514596380 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.748507 # Core power per rank (mW)
-system.physmem.averagePower::1 668.754504 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 623858 # Transaction distribution
-system.membus.trans_dist::ReadResp 623858 # Transaction distribution
-system.membus.trans_dist::WriteReq 13773 # Transaction distribution
-system.membus.trans_dist::WriteResp 13773 # Transaction distribution
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+system.physmem.actEnergy::0 211543920 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 211596840 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 115425750 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 115454625 # Energy for precharge commands per rank (pJ)
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+system.physmem.writeEnergy::0 408337200 # Energy for write commands per rank (pJ)
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+system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.751736 # Core power per rank (mW)
+system.physmem.averagePower::1 668.747452 # Core power per rank (mW)
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system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
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-system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes)
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-system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 948 # Total snoops (count)
-system.membus.snoop_fanout::samples 284802 # Request fanout histogram
+system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 943 # Total snoops (count)
+system.membus.snoop_fanout::samples 285344 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 284802 # Request fanout histogram
-system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 285344 # Request fanout histogram
+system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47504 # number of replacements
-system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use
+system.iocache.tags.replacements 47512 # number of replacements
+system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428031 # Number of tag accesses
-system.iocache.tags.data_accesses 428031 # Number of data accesses
+system.iocache.tags.tag_accesses 428111 # Number of tag accesses
+system.iocache.tags.data_accesses 428111 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 839 # number of ReadReq misses
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-system.iocache.demand_misses::total 839 # number of demand (read+write) misses
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-system.iocache.overall_misses::total 839 # number of overall misses
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-system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles
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-system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles
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+system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses)
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+system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
@@ -420,38 +422,38 @@ system.iocache.avg_blocked_cycles::no_mshrs 12.076923 #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles
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-system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles
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+system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses
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+system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.999979 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999979 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@@ -465,12 +467,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 230144 # Transaction distribution
-system.iobus.trans_dist::ReadResp 230144 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57579 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57579 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1654 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1654 # Transaction distribution
+system.iobus.trans_dist::ReadReq 230267 # Transaction distribution
+system.iobus.trans_dist::ReadResp 230267 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57693 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57694 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1655 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1655 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
@@ -483,18 +486,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
@@ -507,19 +510,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -545,7 +548,7 @@ system.iobus.reqLayer11.occupancy 170000 # La
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
@@ -555,47 +558,47 @@ system.iobus.reqLayer16.occupancy 9000 # La
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 421888846 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 52218502 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 10385022088 # number of cpu cycles simulated
+system.cpu.numCycles 10388821270 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 128310974 # Number of instructions committed
-system.cpu.committedOps 247343919 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 231936467 # Number of integer alu accesses
+system.cpu.committedInsts 128422722 # Number of instructions committed
+system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 2299885 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 23161985 # number of instructions that are conditional controls
-system.cpu.num_int_insts 231936467 # number of integer instructions
+system.cpu.num_func_calls 2301199 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 23183159 # number of instructions that are conditional controls
+system.cpu.num_int_insts 232138334 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 434450917 # number of times the integer registers were read
-system.cpu.num_int_register_writes 197819265 # number of times the integer registers were written
+system.cpu.num_int_register_reads 434808798 # number of times the integer registers were read
+system.cpu.num_int_register_writes 197991574 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 132769519 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 95505601 # number of times the CC registers were written
-system.cpu.num_mem_refs 22243286 # number of memory refs
-system.cpu.num_load_insts 13879256 # Number of load instructions
-system.cpu.num_store_insts 8364030 # Number of store instructions
-system.cpu.num_idle_cycles 9788400874.998116 # Number of idle cycles
-system.cpu.num_busy_cycles 596621213.001885 # Number of busy cycles
-system.cpu.not_idle_fraction 0.057450 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.942550 # Percentage of idle cycles
-system.cpu.Branches 26299942 # Number of branches fetched
-system.cpu.op_class::No_OpClass 174748 0.07% 0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu 224664535 90.83% 90.90% # Class of executed instruction
-system.cpu.op_class::IntMult 139903 0.06% 90.96% # Class of executed instruction
-system.cpu.op_class::IntDiv 122942 0.05% 91.01% # Class of executed instruction
+system.cpu.num_cc_register_reads 132893231 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 95600147 # number of times the CC registers were written
+system.cpu.num_mem_refs 22258678 # number of memory refs
+system.cpu.num_load_insts 13887993 # Number of load instructions
+system.cpu.num_store_insts 8370685 # Number of store instructions
+system.cpu.num_idle_cycles 9791802498.998116 # Number of idle cycles
+system.cpu.num_busy_cycles 597018771.001885 # Number of busy cycles
+system.cpu.not_idle_fraction 0.057467 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.942533 # Percentage of idle cycles
+system.cpu.Branches 26323220 # Number of branches fetched
+system.cpu.op_class::No_OpClass 174807 0.07% 0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu 224862012 90.83% 90.90% # Class of executed instruction
+system.cpu.op_class::IntMult 139985 0.06% 90.96% # Class of executed instruction
+system.cpu.op_class::IntDiv 123095 0.05% 91.01% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction
@@ -622,66 +625,66 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction
-system.cpu.op_class::MemRead 13879256 5.61% 96.62% # Class of executed instruction
-system.cpu.op_class::MemWrite 8364030 3.38% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction
+system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 247345414 # Class of executed instruction
+system.cpu.op_class::total 247558577 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.tags.replacements 790109 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.353605 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 144545821 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 790621 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 182.825679 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 161037022250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.353605 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 791372 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 146127077 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 146127077 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 144545821 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 144545821 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 144545821 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 144545821 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 144545821 # number of overall hits
-system.cpu.icache.overall_hits::total 144545821 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 790628 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 790628 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 790628 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 790628 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 790628 # number of overall misses
-system.cpu.icache.overall_misses::total 790628 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108318120 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 11108318120 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 11108318120 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 11108318120 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 11108318120 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 11108318120 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 145336449 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 145336449 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 145336449 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 145336449 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 145336449 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 145336449 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14049.993322 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14049.993322 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 146263199 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 146263199 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 144679417 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 144679417 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 144679417 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 144679417 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 144679417 # number of overall hits
+system.cpu.icache.overall_hits::total 144679417 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 791891 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 791891 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 791891 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 791891 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 791891 # number of overall misses
+system.cpu.icache.overall_misses::total 791891 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 11123124618 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 11123124618 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 11123124618 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 11123124618 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 11123124618 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 11123124618 # number of overall miss cycles
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@@ -690,87 +693,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
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@@ -779,86 +783,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -867,169 +870,170 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.demand_accesses::total 21193999 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21655782 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21655782 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070603 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.070603 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038849 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.038849 # miss rate for WriteReq accesses
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-system.cpu.dcache.SoftPFReq_miss_rate::total 0.871535 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.058087 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.058087 # miss rate for demand accesses
+system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits
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+system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits
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+system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19580.848895 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14756.726136 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 8324 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency
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+system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 80 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.050000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1537872 # number of writebacks
-system.cpu.dcache.writebacks::total 1537872 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks
+system.cpu.dcache.writebacks::total 1538923 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits
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+system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses
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+system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -1037,196 +1041,196 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 53135 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution
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+system.cpu.l2cache.demand_mshr_miss_rate::total 0.064124 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.064124 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index c8bf9fdf3..d12ae3672 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -74,9 +74,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -191,7 +188,7 @@ master=drivesys.membus.slave[3]
slave=drivesys.iobus.master[29]
[drivesys.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=drivesys.clk_domain
eventq_index=0
header_cycles=1
@@ -202,11 +199,12 @@ master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fa
slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
[drivesys.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=drivesys.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=drivesys
use_default_range=false
width=8
@@ -329,6 +327,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -793,6 +792,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1003,9 +1003,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -1120,7 +1117,7 @@ master=testsys.membus.slave[3]
slave=testsys.iobus.master[29]
[testsys.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=testsys.clk_domain
eventq_index=0
header_cycles=1
@@ -1131,11 +1128,12 @@ master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_
slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
[testsys.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=testsys.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=testsys
use_default_range=false
width=8
@@ -1258,6 +1256,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1722,6 +1721,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index ad6cd6709..bbd960583 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 48d1fef73..67de80452 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -614,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index e3af4adf8..50fa51df7 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
index 1a2ad4916..c9e0c15f4 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 850afe8f9..4de69a578 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index f2c71623d..fe6b478bf 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 07e8d6849..8663b4c78 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 253b90903..a87c15412 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 0eb5daf95..091cdad96 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index a68327a1f..c9efff137 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index fb08ec46d..5f42de628 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -614,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 79159fdc0..f69c898cb 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index 00c794fb7..4519f7012 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 46d0fbb12..7e18a82ef 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index be173178b..8de8f1e38 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 1143e388b..e617d5b21 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 670d15d2e..25deca5e4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -126,6 +126,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 42a419874..402442761 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index f4127b6ce..300b9d035 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 6c1f65269..78a71faf3 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -75,6 +75,7 @@ dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -98,7 +99,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -829,10 +829,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -862,6 +863,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -880,10 +882,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -892,8 +895,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -902,6 +930,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -915,19 +944,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index db525069f..a1b6a8304 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index a0f588ff6..91da4c557 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -369,6 +366,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -387,10 +385,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index d8b9bcc6e..2e24c6545 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 017bc1348..54668155a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index a47df6208..93ee36e3b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -237,10 +237,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -270,6 +271,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -288,10 +290,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -300,8 +303,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -310,6 +338,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -323,19 +352,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 1f8305e4e..946ab8388 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -583,10 +583,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -616,6 +617,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -634,10 +636,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -646,8 +649,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -656,6 +684,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -669,19 +698,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index a20aef42c..4e242dacc 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -127,6 +124,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -145,10 +143,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index e05997c32..03c785312 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -128,6 +128,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 1ce9455cf..e0e01d26c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -203,10 +203,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -236,6 +237,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -254,10 +256,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index e341fc69a..709f4f73b 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -75,6 +75,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -127,7 +128,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -614,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 0aa78ac08..00428c3e1 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -69,9 +69,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index facfb2ae6..a3c44273d 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -297,8 +300,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -307,6 +335,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -320,19 +349,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index f6abe18a9..10cf57bb4 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index abf61111c..583cc8b93 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -125,6 +125,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 102ae8d7c..e38847653 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 2be4f154a..4263ec382 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -647,6 +648,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index db49faad7..960bf1b41 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 93964b6e7..cf742c468 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -159,6 +159,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index a819aa859..5b07510f0 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index d28531788..d358e4bd4 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload0 system.cpu.workload1
dcache_port=system.cpu.dcache.cpu_side
@@ -586,10 +586,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -619,6 +620,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu.workload1]
type=LiveProcess
@@ -639,6 +641,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -657,10 +660,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -669,8 +673,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -679,6 +708,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -692,19 +722,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index d6d7e175a..c6b990bda 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -297,8 +300,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -307,6 +335,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -320,19 +349,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 2560e1b90..144f058d7 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +580,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -613,6 +614,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +633,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +646,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +681,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +695,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index a0349a47c..fc4381d3d 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 0cf6b950c..727287e35 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index ea05b9577..144007094 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu0.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu0.dcache.cpu_side
@@ -567,6 +567,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu1]
type=DerivO3CPU
@@ -599,6 +600,7 @@ do_statistics_insts=true
dtb=system.cpu1.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -651,7 +653,6 @@ switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu1.dcache.cpu_side
@@ -1104,6 +1105,7 @@ do_statistics_insts=true
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -1156,7 +1158,6 @@ switched_out=false
system=system
tracer=system.cpu2.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu2.dcache.cpu_side
@@ -1609,6 +1610,7 @@ do_statistics_insts=true
dtb=system.cpu3.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -1661,7 +1663,6 @@ switched_out=false
system=system
tracer=system.cpu3.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu3.dcache.cpu_side
@@ -2135,10 +2136,11 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -2147,8 +2149,33 @@ slave=system.system_port system.l2c.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -2157,6 +2184,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -2170,29 +2198,37 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 33ff09cf3..90080e4d5 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:07:38
-gem5 started Jun 21 2014 11:08:21
-gem5 executing on phenom
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Oct 11 2014 05:01:31
+gem5 started Oct 11 2014 05:01:48
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
@@ -17,54 +17,54 @@ Init done
[Iteration 1, Thread 3] Got lock
[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
Iteration 2 completed
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
Iteration 3 completed
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
Iteration 4 completed
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
Iteration 5 completed
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 6, Thread 1] Got lock
[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
Iteration 8 completed
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
@@ -75,10 +75,10 @@ Iteration 8 completed
Iteration 9 completed
[Iteration 10, Thread 1] Got lock
[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
Iteration 10 completed
PASSED :-)
-Exiting @ tick 110970500 because target called exit()
+Exiting @ tick 105696000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 742ce1ca7..dc830ef72 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -194,6 +191,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu1]
type=AtomicSimpleCPU
@@ -220,9 +218,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -352,9 +347,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -484,9 +476,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -643,10 +632,11 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -667,10 +657,11 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 79edf9761..17be690b9 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 17:29:52
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled Oct 11 2014 05:01:31
+gem5 started Oct 11 2014 05:01:48
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
@@ -29,54 +31,54 @@ Iteration 2 completed
[Iteration 3, Thread 1] Got lock
[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
Iteration 3 completed
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 4, Thread 1] Got lock
[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
Iteration 4 completed
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
Iteration 5 completed
[Iteration 6, Thread 2] Got lock
[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
Iteration 6 completed
[Iteration 7, Thread 2] Got lock
[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
Iteration 10 completed
PASSED :-)
Exiting @ tick 87707000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index d83d155ae..2ad22e920 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -187,6 +187,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu1]
type=TimingSimpleCPU
@@ -615,10 +616,11 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -639,10 +641,11 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
index 1c907dde7..58228c89a 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
index b779cf15d..215e9ea82 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu7: completed 10000 read, 5432 write accesses @720734
-system.cpu0: completed 10000 read, 5512 write accesses @730548
-system.cpu1: completed 10000 read, 5469 write accesses @733316
-system.cpu3: completed 10000 read, 5348 write accesses @734089
-system.cpu5: completed 10000 read, 5304 write accesses @739554
-system.cpu4: completed 10000 read, 5523 write accesses @742146
-system.cpu2: completed 10000 read, 5353 write accesses @742448
-system.cpu6: completed 10000 read, 5456 write accesses @746526
-system.cpu0: completed 20000 read, 10918 write accesses @1452216
-system.cpu7: completed 20000 read, 10905 write accesses @1455831
-system.cpu2: completed 20000 read, 10616 write accesses @1456643
-system.cpu1: completed 20000 read, 10900 write accesses @1468694
-system.cpu3: completed 20000 read, 10595 write accesses @1471954
-system.cpu6: completed 20000 read, 10732 write accesses @1476612
-system.cpu5: completed 20000 read, 10777 write accesses @1484015
-system.cpu4: completed 20000 read, 10962 write accesses @1484193
-system.cpu7: completed 30000 read, 16301 write accesses @2190709
-system.cpu3: completed 30000 read, 15930 write accesses @2193108
-system.cpu0: completed 30000 read, 16492 write accesses @2204699
-system.cpu2: completed 30000 read, 16137 write accesses @2208852
-system.cpu1: completed 30000 read, 16294 write accesses @2211342
-system.cpu6: completed 30000 read, 16138 write accesses @2217558
-system.cpu5: completed 30000 read, 16017 write accesses @2217893
-system.cpu4: completed 30000 read, 16364 write accesses @2220770
-system.cpu7: completed 40000 read, 21683 write accesses @2923239
-system.cpu3: completed 40000 read, 21410 write accesses @2936019
-system.cpu2: completed 40000 read, 21422 write accesses @2936262
-system.cpu0: completed 40000 read, 21993 write accesses @2938221
-system.cpu5: completed 40000 read, 21407 write accesses @2949381
-system.cpu4: completed 40000 read, 21696 write accesses @2954856
-system.cpu6: completed 40000 read, 21664 write accesses @2955212
-system.cpu1: completed 40000 read, 21772 write accesses @2957373
-system.cpu7: completed 50000 read, 26880 write accesses @3637356
-system.cpu0: completed 50000 read, 27433 write accesses @3667809
-system.cpu2: completed 50000 read, 26841 write accesses @3676541
-system.cpu3: completed 50000 read, 26846 write accesses @3676934
-system.cpu1: completed 50000 read, 27155 write accesses @3679587
-system.cpu5: completed 50000 read, 26712 write accesses @3699925
-system.cpu4: completed 50000 read, 27199 write accesses @3700680
-system.cpu6: completed 50000 read, 27119 write accesses @3709288
-system.cpu7: completed 60000 read, 32133 write accesses @4356266
-system.cpu0: completed 60000 read, 32774 write accesses @4396377
-system.cpu3: completed 60000 read, 32241 write accesses @4405248
-system.cpu2: completed 60000 read, 32179 write accesses @4410455
-system.cpu1: completed 60000 read, 32548 write accesses @4418337
-system.cpu4: completed 60000 read, 32496 write accesses @4444142
-system.cpu6: completed 60000 read, 32520 write accesses @4446125
-system.cpu5: completed 60000 read, 32111 write accesses @4457785
-system.cpu7: completed 70000 read, 37528 write accesses @5092190
-system.cpu3: completed 70000 read, 37618 write accesses @5124227
-system.cpu0: completed 70000 read, 38140 write accesses @5138553
-system.cpu2: completed 70000 read, 37630 write accesses @5148204
-system.cpu4: completed 70000 read, 37860 write accesses @5162780
-system.cpu1: completed 70000 read, 37968 write accesses @5169201
-system.cpu6: completed 70000 read, 38023 write accesses @5190771
-system.cpu5: completed 70000 read, 37447 write accesses @5193894
-system.cpu7: completed 80000 read, 42859 write accesses @5808723
-system.cpu3: completed 80000 read, 43086 write accesses @5863853
-system.cpu2: completed 80000 read, 43034 write accesses @5892131
-system.cpu0: completed 80000 read, 43586 write accesses @5894007
-system.cpu4: completed 80000 read, 43221 write accesses @5909816
-system.cpu1: completed 80000 read, 43381 write accesses @5910301
-system.cpu6: completed 80000 read, 43445 write accesses @5922153
-system.cpu5: completed 80000 read, 42916 write accesses @5926434
-system.cpu7: completed 90000 read, 48423 write accesses @6537227
-system.cpu3: completed 90000 read, 48562 write accesses @6619736
-system.cpu0: completed 90000 read, 48962 write accesses @6625530
-system.cpu2: completed 90000 read, 48441 write accesses @6629626
-system.cpu1: completed 90000 read, 48846 write accesses @6644848
-system.cpu6: completed 90000 read, 48899 write accesses @6650109
-system.cpu4: completed 90000 read, 48617 write accesses @6655860
-system.cpu5: completed 90000 read, 48309 write accesses @6656682
-system.cpu7: completed 100000 read, 53646 write accesses @7259586
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu2: completed 10000 read, 5361 write accesses @731568
+system.cpu5: completed 10000 read, 5557 write accesses @735340
+system.cpu3: completed 10000 read, 5535 write accesses @738863
+system.cpu6: completed 10000 read, 5476 write accesses @748316
+system.cpu0: completed 10000 read, 5560 write accesses @752250
+system.cpu4: completed 10000 read, 5465 write accesses @757289
+system.cpu7: completed 10000 read, 5564 write accesses @760144
+system.cpu1: completed 10000 read, 5530 write accesses @768416
+system.cpu5: completed 20000 read, 11151 write accesses @1477095
+system.cpu2: completed 20000 read, 10827 write accesses @1478088
+system.cpu3: completed 20000 read, 11078 write accesses @1481757
+system.cpu0: completed 20000 read, 11117 write accesses @1493889
+system.cpu6: completed 20000 read, 11080 write accesses @1512346
+system.cpu1: completed 20000 read, 11091 write accesses @1512763
+system.cpu4: completed 20000 read, 10986 write accesses @1520589
+system.cpu7: completed 20000 read, 11078 write accesses @1523748
+system.cpu5: completed 30000 read, 16568 write accesses @2200051
+system.cpu3: completed 30000 read, 16616 write accesses @2221845
+system.cpu2: completed 30000 read, 16217 write accesses @2232672
+system.cpu0: completed 30000 read, 16692 write accesses @2249618
+system.cpu1: completed 30000 read, 16648 write accesses @2263101
+system.cpu6: completed 30000 read, 16745 write accesses @2274150
+system.cpu4: completed 30000 read, 16620 write accesses @2276386
+system.cpu7: completed 30000 read, 16733 write accesses @2277359
+system.cpu5: completed 40000 read, 21987 write accesses @2947352
+system.cpu3: completed 40000 read, 22027 write accesses @2968674
+system.cpu1: completed 40000 read, 22148 write accesses @2995890
+system.cpu0: completed 40000 read, 22166 write accesses @2998152
+system.cpu2: completed 40000 read, 21828 write accesses @3001342
+system.cpu7: completed 40000 read, 22152 write accesses @3022463
+system.cpu6: completed 40000 read, 22388 write accesses @3028895
+system.cpu4: completed 40000 read, 22197 write accesses @3031091
+system.cpu5: completed 50000 read, 27444 write accesses @3696748
+system.cpu3: completed 50000 read, 27708 write accesses @3723471
+system.cpu1: completed 50000 read, 27649 write accesses @3746058
+system.cpu0: completed 50000 read, 27719 write accesses @3747410
+system.cpu2: completed 50000 read, 27424 write accesses @3760076
+system.cpu7: completed 50000 read, 27568 write accesses @3771426
+system.cpu6: completed 50000 read, 28012 write accesses @3777023
+system.cpu4: completed 50000 read, 27741 write accesses @3802071
+system.cpu5: completed 60000 read, 33062 write accesses @4446684
+system.cpu3: completed 60000 read, 33331 write accesses @4487796
+system.cpu2: completed 60000 read, 33035 write accesses @4498626
+system.cpu0: completed 60000 read, 33211 write accesses @4505229
+system.cpu1: completed 60000 read, 33219 write accesses @4525223
+system.cpu6: completed 60000 read, 33545 write accesses @4528416
+system.cpu7: completed 60000 read, 33210 write accesses @4528425
+system.cpu4: completed 60000 read, 33325 write accesses @4560641
+system.cpu5: completed 70000 read, 38698 write accesses @5188287
+system.cpu2: completed 70000 read, 38579 write accesses @5235379
+system.cpu7: completed 70000 read, 38633 write accesses @5255909
+system.cpu0: completed 70000 read, 38682 write accesses @5255973
+system.cpu6: completed 70000 read, 38964 write accesses @5261147
+system.cpu3: completed 70000 read, 38993 write accesses @5267174
+system.cpu1: completed 70000 read, 38888 write accesses @5283161
+system.cpu4: completed 70000 read, 38789 write accesses @5300670
+system.cpu5: completed 80000 read, 44039 write accesses @5937946
+system.cpu2: completed 80000 read, 43995 write accesses @5990383
+system.cpu7: completed 80000 read, 44179 write accesses @5992827
+system.cpu0: completed 80000 read, 44154 write accesses @6000956
+system.cpu6: completed 80000 read, 44514 write accesses @6013988
+system.cpu3: completed 80000 read, 44595 write accesses @6025710
+system.cpu1: completed 80000 read, 44663 write accesses @6042332
+system.cpu4: completed 80000 read, 44390 write accesses @6048987
+system.cpu5: completed 90000 read, 49553 write accesses @6694237
+system.cpu7: completed 90000 read, 49635 write accesses @6734659
+system.cpu2: completed 90000 read, 49508 write accesses @6735285
+system.cpu0: completed 90000 read, 49652 write accesses @6748849
+system.cpu6: completed 90000 read, 50083 write accesses @6767267
+system.cpu1: completed 90000 read, 50078 write accesses @6778899
+system.cpu3: completed 90000 read, 50108 write accesses @6783497
+system.cpu4: completed 90000 read, 50077 write accesses @6811616
+system.cpu5: completed 100000 read, 55112 write accesses @7430292
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index cce9b7e46..a6cce7aa1 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index 96061ea38..327665b25 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu6: completed 10000 read, 5376 write accesses @740514
-system.cpu0: completed 10000 read, 5364 write accesses @745186
-system.cpu3: completed 10000 read, 5423 write accesses @748707
-system.cpu4: completed 10000 read, 5537 write accesses @749784
-system.cpu7: completed 10000 read, 5400 write accesses @749868
-system.cpu1: completed 10000 read, 5530 write accesses @750998
-system.cpu5: completed 10000 read, 5459 write accesses @756529
-system.cpu2: completed 10000 read, 5543 write accesses @771097
-system.cpu6: completed 20000 read, 10651 write accesses @1479754
-system.cpu3: completed 20000 read, 10879 write accesses @1495041
-system.cpu7: completed 20000 read, 10760 write accesses @1499008
-system.cpu1: completed 20000 read, 10977 write accesses @1499104
-system.cpu5: completed 20000 read, 10867 write accesses @1505086
-system.cpu0: completed 20000 read, 10799 write accesses @1507389
-system.cpu4: completed 20000 read, 11068 write accesses @1508085
-system.cpu2: completed 20000 read, 10878 write accesses @1527233
-system.cpu6: completed 30000 read, 16119 write accesses @2225328
-system.cpu3: completed 30000 read, 16305 write accesses @2244855
-system.cpu5: completed 30000 read, 16187 write accesses @2247278
-system.cpu7: completed 30000 read, 16155 write accesses @2249487
-system.cpu1: completed 30000 read, 16466 write accesses @2250992
-system.cpu0: completed 30000 read, 16273 write accesses @2255206
-system.cpu4: completed 30000 read, 16428 write accesses @2263136
-system.cpu2: completed 30000 read, 16197 write accesses @2278056
-system.cpu6: completed 40000 read, 21573 write accesses @2978557
-system.cpu7: completed 40000 read, 21410 write accesses @2982935
-system.cpu4: completed 40000 read, 21729 write accesses @2999959
-system.cpu3: completed 40000 read, 21781 write accesses @3000904
-system.cpu1: completed 40000 read, 21951 write accesses @3003109
-system.cpu5: completed 40000 read, 21639 write accesses @3013039
-system.cpu0: completed 40000 read, 21607 write accesses @3015250
-system.cpu2: completed 40000 read, 21696 write accesses @3037769
-system.cpu6: completed 50000 read, 26913 write accesses @3719593
-system.cpu7: completed 50000 read, 26968 write accesses @3753645
-system.cpu4: completed 50000 read, 27060 write accesses @3754051
-system.cpu1: completed 50000 read, 27365 write accesses @3755861
-system.cpu0: completed 50000 read, 27035 write accesses @3755945
-system.cpu3: completed 50000 read, 27265 write accesses @3757400
-system.cpu5: completed 50000 read, 27001 write accesses @3763589
-system.cpu2: completed 50000 read, 27364 write accesses @3806785
-system.cpu6: completed 60000 read, 32204 write accesses @4458868
-system.cpu1: completed 60000 read, 32673 write accesses @4480776
-system.cpu0: completed 60000 read, 32481 write accesses @4498229
-system.cpu7: completed 60000 read, 32335 write accesses @4506920
-system.cpu3: completed 60000 read, 32750 write accesses @4507998
-system.cpu4: completed 60000 read, 32435 write accesses @4514030
-system.cpu5: completed 60000 read, 32505 write accesses @4516999
-system.cpu2: completed 60000 read, 32812 write accesses @4572908
-system.cpu6: completed 70000 read, 37702 write accesses @5219683
-system.cpu0: completed 70000 read, 38094 write accesses @5237731
-system.cpu1: completed 70000 read, 38271 write accesses @5247271
-system.cpu5: completed 70000 read, 37826 write accesses @5260789
-system.cpu3: completed 70000 read, 38167 write accesses @5262755
-system.cpu4: completed 70000 read, 37927 write accesses @5268995
-system.cpu7: completed 70000 read, 37729 write accesses @5271169
-system.cpu2: completed 70000 read, 38312 write accesses @5320578
-system.cpu6: completed 80000 read, 43265 write accesses @5963960
-system.cpu0: completed 80000 read, 43558 write accesses @5996302
-system.cpu5: completed 80000 read, 43163 write accesses @6000784
-system.cpu3: completed 80000 read, 43563 write accesses @6009019
-system.cpu1: completed 80000 read, 43846 write accesses @6010830
-system.cpu4: completed 80000 read, 43375 write accesses @6021719
-system.cpu7: completed 80000 read, 43151 write accesses @6032005
-system.cpu2: completed 80000 read, 43642 write accesses @6070842
-system.cpu6: completed 90000 read, 48756 write accesses @6719511
-system.cpu5: completed 90000 read, 48675 write accesses @6752879
-system.cpu0: completed 90000 read, 49075 write accesses @6759943
-system.cpu4: completed 90000 read, 48792 write accesses @6772472
-system.cpu1: completed 90000 read, 49329 write accesses @6774290
-system.cpu3: completed 90000 read, 49090 write accesses @6783540
-system.cpu7: completed 90000 read, 48766 write accesses @6785808
-system.cpu2: completed 90000 read, 49113 write accesses @6821790
-system.cpu6: completed 100000 read, 54332 write accesses @7481441
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu6: completed 10000 read, 5503 write accesses @757269
+system.cpu4: completed 10000 read, 5478 write accesses @761080
+system.cpu2: completed 10000 read, 5550 write accesses @763319
+system.cpu1: completed 10000 read, 5614 write accesses @768345
+system.cpu0: completed 10000 read, 5587 write accesses @769447
+system.cpu7: completed 10000 read, 5757 write accesses @772728
+system.cpu5: completed 10000 read, 5702 write accesses @774176
+system.cpu3: completed 10000 read, 5518 write accesses @779096
+system.cpu7: completed 20000 read, 10973 write accesses @1520367
+system.cpu4: completed 20000 read, 10979 write accesses @1526709
+system.cpu6: completed 20000 read, 11106 write accesses @1529725
+system.cpu2: completed 20000 read, 10993 write accesses @1531224
+system.cpu1: completed 20000 read, 11181 write accesses @1533339
+system.cpu5: completed 20000 read, 11353 write accesses @1534479
+system.cpu0: completed 20000 read, 11156 write accesses @1538403
+system.cpu3: completed 20000 read, 11059 write accesses @1546200
+system.cpu7: completed 30000 read, 16565 write accesses @2285511
+system.cpu5: completed 30000 read, 16777 write accesses @2288641
+system.cpu2: completed 30000 read, 16597 write accesses @2294136
+system.cpu4: completed 30000 read, 16631 write accesses @2299512
+system.cpu0: completed 30000 read, 16690 write accesses @2299577
+system.cpu1: completed 30000 read, 16784 write accesses @2300367
+system.cpu3: completed 30000 read, 16611 write accesses @2300731
+system.cpu6: completed 30000 read, 16728 write accesses @2302250
+system.cpu4: completed 40000 read, 22149 write accesses @3049466
+system.cpu6: completed 40000 read, 22257 write accesses @3061175
+system.cpu7: completed 40000 read, 22207 write accesses @3063273
+system.cpu5: completed 40000 read, 22390 write accesses @3065947
+system.cpu2: completed 40000 read, 22266 write accesses @3066692
+system.cpu3: completed 40000 read, 22073 write accesses @3067947
+system.cpu0: completed 40000 read, 22351 write accesses @3070634
+system.cpu1: completed 40000 read, 22419 write accesses @3080538
+system.cpu4: completed 50000 read, 27758 write accesses @3814226
+system.cpu5: completed 50000 read, 27788 write accesses @3821800
+system.cpu2: completed 50000 read, 27879 write accesses @3832783
+system.cpu6: completed 50000 read, 27794 write accesses @3833668
+system.cpu7: completed 50000 read, 27831 write accesses @3833943
+system.cpu3: completed 50000 read, 27630 write accesses @3836295
+system.cpu1: completed 50000 read, 28014 write accesses @3838264
+system.cpu0: completed 50000 read, 27900 write accesses @3845606
+system.cpu4: completed 60000 read, 33195 write accesses @4581871
+system.cpu6: completed 60000 read, 33436 write accesses @4591130
+system.cpu5: completed 60000 read, 33441 write accesses @4592195
+system.cpu2: completed 60000 read, 33425 write accesses @4596449
+system.cpu7: completed 60000 read, 33475 write accesses @4602310
+system.cpu1: completed 60000 read, 33528 write accesses @4604165
+system.cpu3: completed 60000 read, 33269 write accesses @4608944
+system.cpu0: completed 60000 read, 33561 write accesses @4617814
+system.cpu4: completed 70000 read, 38745 write accesses @5357021
+system.cpu1: completed 70000 read, 39092 write accesses @5358188
+system.cpu7: completed 70000 read, 39078 write accesses @5359639
+system.cpu6: completed 70000 read, 39017 write accesses @5360015
+system.cpu5: completed 70000 read, 39077 write accesses @5360709
+system.cpu2: completed 70000 read, 39142 write accesses @5362206
+system.cpu3: completed 70000 read, 38953 write accesses @5383557
+system.cpu0: completed 70000 read, 39148 write accesses @5384346
+system.cpu1: completed 80000 read, 44697 write accesses @6109229
+system.cpu4: completed 80000 read, 44391 write accesses @6113222
+system.cpu6: completed 80000 read, 44634 write accesses @6116932
+system.cpu2: completed 80000 read, 44686 write accesses @6124384
+system.cpu7: completed 80000 read, 44658 write accesses @6130030
+system.cpu5: completed 80000 read, 44817 write accesses @6133468
+system.cpu0: completed 80000 read, 44666 write accesses @6150195
+system.cpu3: completed 80000 read, 44619 write accesses @6165694
+system.cpu1: completed 90000 read, 50286 write accesses @6886139
+system.cpu5: completed 90000 read, 50291 write accesses @6887562
+system.cpu6: completed 90000 read, 50249 write accesses @6888221
+system.cpu4: completed 90000 read, 50068 write accesses @6890175
+system.cpu2: completed 90000 read, 50264 write accesses @6897909
+system.cpu7: completed 90000 read, 50336 write accesses @6907186
+system.cpu3: completed 90000 read, 50220 write accesses @6927421
+system.cpu0: completed 90000 read, 50337 write accesses @6930851
+system.cpu5: completed 100000 read, 55860 write accesses @7645897
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index c165a6832..319711992 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 78259ab68..1e742ef57 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu3: completed 10000 read, 5373 write accesses @610961
-system.cpu5: completed 10000 read, 5365 write accesses @611018
-system.cpu4: completed 10000 read, 5553 write accesses @613027
-system.cpu2: completed 10000 read, 5350 write accesses @617677
-system.cpu1: completed 10000 read, 5430 write accesses @618344
-system.cpu0: completed 10000 read, 5583 write accesses @619157
-system.cpu7: completed 10000 read, 5389 write accesses @620153
-system.cpu6: completed 10000 read, 5612 write accesses @620650
-system.cpu5: completed 20000 read, 10789 write accesses @1225454
-system.cpu1: completed 20000 read, 10846 write accesses @1236230
-system.cpu4: completed 20000 read, 10993 write accesses @1237289
-system.cpu0: completed 20000 read, 11135 write accesses @1237437
-system.cpu7: completed 20000 read, 10790 write accesses @1238914
-system.cpu3: completed 20000 read, 10722 write accesses @1239177
-system.cpu6: completed 20000 read, 11153 write accesses @1244507
-system.cpu2: completed 20000 read, 10728 write accesses @1245295
-system.cpu5: completed 30000 read, 16089 write accesses @1837067
-system.cpu1: completed 30000 read, 16220 write accesses @1844516
-system.cpu3: completed 30000 read, 16042 write accesses @1846213
-system.cpu6: completed 30000 read, 16442 write accesses @1852618
-system.cpu0: completed 30000 read, 16510 write accesses @1857227
-system.cpu7: completed 30000 read, 16238 write accesses @1862399
-system.cpu2: completed 30000 read, 16227 write accesses @1874504
-system.cpu4: completed 30000 read, 16481 write accesses @1879909
-system.cpu5: completed 40000 read, 21666 write accesses @2447180
-system.cpu1: completed 40000 read, 21716 write accesses @2464865
-system.cpu0: completed 40000 read, 21907 write accesses @2473366
-system.cpu7: completed 40000 read, 21535 write accesses @2473664
-system.cpu3: completed 40000 read, 21446 write accesses @2475585
-system.cpu6: completed 40000 read, 21928 write accesses @2479522
-system.cpu4: completed 40000 read, 21651 write accesses @2491724
-system.cpu2: completed 40000 read, 21571 write accesses @2492947
-system.cpu5: completed 50000 read, 27225 write accesses @3067865
-system.cpu7: completed 50000 read, 26823 write accesses @3086290
-system.cpu3: completed 50000 read, 26661 write accesses @3087077
-system.cpu1: completed 50000 read, 27045 write accesses @3088502
-system.cpu6: completed 50000 read, 27350 write accesses @3091373
-system.cpu0: completed 50000 read, 27240 write accesses @3099902
-system.cpu4: completed 50000 read, 27063 write accesses @3101501
-system.cpu2: completed 50000 read, 27064 write accesses @3114914
-system.cpu5: completed 60000 read, 32586 write accesses @3679414
-system.cpu1: completed 60000 read, 32546 write accesses @3694760
-system.cpu3: completed 60000 read, 32032 write accesses @3702088
-system.cpu7: completed 60000 read, 32061 write accesses @3707072
-system.cpu0: completed 60000 read, 32607 write accesses @3710014
-system.cpu2: completed 60000 read, 32411 write accesses @3717514
-system.cpu6: completed 60000 read, 32905 write accesses @3719411
-system.cpu4: completed 60000 read, 32455 write accesses @3724218
-system.cpu1: completed 70000 read, 37971 write accesses @4303479
-system.cpu3: completed 70000 read, 37478 write accesses @4307612
-system.cpu5: completed 70000 read, 38121 write accesses @4312096
-system.cpu0: completed 70000 read, 38044 write accesses @4316156
-system.cpu7: completed 70000 read, 37345 write accesses @4323040
-system.cpu2: completed 70000 read, 37853 write accesses @4334714
-system.cpu6: completed 70000 read, 38341 write accesses @4338265
-system.cpu4: completed 70000 read, 37883 write accesses @4348139
-system.cpu3: completed 80000 read, 42790 write accesses @4909950
-system.cpu0: completed 80000 read, 43447 write accesses @4922258
-system.cpu1: completed 80000 read, 43458 write accesses @4929896
-system.cpu5: completed 80000 read, 43556 write accesses @4929946
-system.cpu7: completed 80000 read, 42733 write accesses @4945136
-system.cpu2: completed 80000 read, 43278 write accesses @4954988
-system.cpu6: completed 80000 read, 43794 write accesses @4962728
-system.cpu4: completed 80000 read, 43313 write accesses @4970893
-system.cpu3: completed 90000 read, 48235 write accesses @5529277
-system.cpu1: completed 90000 read, 48908 write accesses @5532854
-system.cpu0: completed 90000 read, 48795 write accesses @5538200
-system.cpu5: completed 90000 read, 49134 write accesses @5544337
-system.cpu2: completed 90000 read, 48427 write accesses @5551687
-system.cpu7: completed 90000 read, 48273 write accesses @5561660
-system.cpu4: completed 90000 read, 48720 write accesses @5589754
-system.cpu6: completed 90000 read, 49134 write accesses @5592253
-system.cpu0: completed 100000 read, 54250 write accesses @6151475
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu5: completed 10000 read, 5530 write accesses @619922
+system.cpu6: completed 10000 read, 5474 write accesses @621650
+system.cpu7: completed 10000 read, 5669 write accesses @623678
+system.cpu2: completed 10000 read, 5566 write accesses @627878
+system.cpu4: completed 10000 read, 5488 write accesses @628250
+system.cpu1: completed 10000 read, 5485 write accesses @629308
+system.cpu3: completed 10000 read, 5616 write accesses @630755
+system.cpu0: completed 10000 read, 5556 write accesses @631832
+system.cpu0: completed 20000 read, 11113 write accesses @1242739
+system.cpu2: completed 20000 read, 11184 write accesses @1249193
+system.cpu5: completed 20000 read, 11055 write accesses @1252676
+system.cpu1: completed 20000 read, 11025 write accesses @1255481
+system.cpu6: completed 20000 read, 10958 write accesses @1259795
+system.cpu3: completed 20000 read, 11192 write accesses @1262410
+system.cpu4: completed 20000 read, 11069 write accesses @1265165
+system.cpu7: completed 20000 read, 11154 write accesses @1271872
+system.cpu2: completed 30000 read, 16789 write accesses @1882328
+system.cpu5: completed 30000 read, 16628 write accesses @1882366
+system.cpu4: completed 30000 read, 16634 write accesses @1884079
+system.cpu0: completed 30000 read, 16724 write accesses @1885096
+system.cpu1: completed 30000 read, 16623 write accesses @1888139
+system.cpu3: completed 30000 read, 16738 write accesses @1892924
+system.cpu6: completed 30000 read, 16532 write accesses @1894586
+system.cpu7: completed 30000 read, 16931 write accesses @1919912
+system.cpu0: completed 40000 read, 22182 write accesses @2505116
+system.cpu4: completed 40000 read, 22117 write accesses @2510993
+system.cpu1: completed 40000 read, 22260 write accesses @2513447
+system.cpu5: completed 40000 read, 22212 write accesses @2514125
+system.cpu3: completed 40000 read, 22396 write accesses @2516765
+system.cpu2: completed 40000 read, 22468 write accesses @2519189
+system.cpu6: completed 40000 read, 22230 write accesses @2538281
+system.cpu7: completed 40000 read, 22488 write accesses @2557526
+system.cpu0: completed 50000 read, 27789 write accesses @3133555
+system.cpu2: completed 50000 read, 28077 write accesses @3139915
+system.cpu4: completed 50000 read, 27742 write accesses @3146518
+system.cpu1: completed 50000 read, 27886 write accesses @3150027
+system.cpu5: completed 50000 read, 27798 write accesses @3154334
+system.cpu3: completed 50000 read, 28034 write accesses @3161717
+system.cpu6: completed 50000 read, 27710 write accesses @3168082
+system.cpu7: completed 50000 read, 28032 write accesses @3187555
+system.cpu0: completed 60000 read, 33311 write accesses @3767660
+system.cpu4: completed 60000 read, 33304 write accesses @3772541
+system.cpu1: completed 60000 read, 33446 write accesses @3773198
+system.cpu2: completed 60000 read, 33652 write accesses @3776350
+system.cpu5: completed 60000 read, 33271 write accesses @3781457
+system.cpu6: completed 60000 read, 33278 write accesses @3794854
+system.cpu3: completed 60000 read, 33612 write accesses @3795827
+system.cpu7: completed 60000 read, 33548 write accesses @3811016
+system.cpu0: completed 70000 read, 38763 write accesses @4391942
+system.cpu5: completed 70000 read, 38783 write accesses @4406065
+system.cpu4: completed 70000 read, 38931 write accesses @4406093
+system.cpu1: completed 70000 read, 39120 write accesses @4408424
+system.cpu2: completed 70000 read, 39282 write accesses @4411507
+system.cpu6: completed 70000 read, 38935 write accesses @4431425
+system.cpu3: completed 70000 read, 39112 write accesses @4436411
+system.cpu7: completed 70000 read, 39053 write accesses @4450257
+system.cpu4: completed 80000 read, 44397 write accesses @5015840
+system.cpu0: completed 80000 read, 44355 write accesses @5031328
+system.cpu1: completed 80000 read, 44681 write accesses @5033509
+system.cpu5: completed 80000 read, 44411 write accesses @5035544
+system.cpu2: completed 80000 read, 44867 write accesses @5051495
+system.cpu6: completed 80000 read, 44501 write accesses @5065596
+system.cpu3: completed 80000 read, 44674 write accesses @5067973
+system.cpu7: completed 80000 read, 44457 write accesses @5071578
+system.cpu5: completed 90000 read, 50018 write accesses @5653124
+system.cpu4: completed 90000 read, 50091 write accesses @5657891
+system.cpu0: completed 90000 read, 50057 write accesses @5659483
+system.cpu1: completed 90000 read, 50245 write accesses @5662169
+system.cpu2: completed 90000 read, 50468 write accesses @5689246
+system.cpu7: completed 90000 read, 50055 write accesses @5700359
+system.cpu6: completed 90000 read, 50091 write accesses @5701022
+system.cpu3: completed 90000 read, 50159 write accesses @5709281
+system.cpu0: completed 100000 read, 55570 write accesses @6284915
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 77392538d..c8c135618 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index f2f8ae71c..80cafee63 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu5: completed 10000 read, 5516 write accesses @570851
-system.cpu3: completed 10000 read, 5324 write accesses @572812
-system.cpu1: completed 10000 read, 5481 write accesses @576530
-system.cpu2: completed 10000 read, 5411 write accesses @581924
-system.cpu6: completed 10000 read, 5498 write accesses @589277
-system.cpu4: completed 10000 read, 5455 write accesses @592697
-system.cpu7: completed 10000 read, 5509 write accesses @593396
-system.cpu0: completed 10000 read, 5411 write accesses @595334
-system.cpu5: completed 20000 read, 10869 write accesses @1154450
-system.cpu3: completed 20000 read, 10943 write accesses @1161279
-system.cpu1: completed 20000 read, 10969 write accesses @1165235
-system.cpu2: completed 20000 read, 10883 write accesses @1170873
-system.cpu4: completed 20000 read, 10908 write accesses @1171882
-system.cpu0: completed 20000 read, 10807 write accesses @1172431
-system.cpu6: completed 20000 read, 10859 write accesses @1174037
-system.cpu7: completed 20000 read, 11017 write accesses @1183706
-system.cpu5: completed 30000 read, 16441 write accesses @1743020
-system.cpu3: completed 30000 read, 16218 write accesses @1743361
-system.cpu0: completed 30000 read, 16106 write accesses @1749355
-system.cpu6: completed 30000 read, 16285 write accesses @1751262
-system.cpu2: completed 30000 read, 16334 write accesses @1752944
-system.cpu1: completed 30000 read, 16624 write accesses @1754412
-system.cpu4: completed 30000 read, 16300 write accesses @1756493
-system.cpu7: completed 30000 read, 16545 write accesses @1761662
-system.cpu5: completed 40000 read, 21903 write accesses @2321871
-system.cpu2: completed 40000 read, 21777 write accesses @2328122
-system.cpu6: completed 40000 read, 21684 write accesses @2328788
-system.cpu0: completed 40000 read, 21584 write accesses @2333159
-system.cpu4: completed 40000 read, 21691 write accesses @2333509
-system.cpu3: completed 40000 read, 21802 write accesses @2335052
-system.cpu1: completed 40000 read, 21911 write accesses @2336699
-system.cpu7: completed 40000 read, 21984 write accesses @2354153
-system.cpu3: completed 50000 read, 27199 write accesses @2900098
-system.cpu6: completed 50000 read, 26980 write accesses @2908928
-system.cpu2: completed 50000 read, 27238 write accesses @2909195
-system.cpu5: completed 50000 read, 27250 write accesses @2913605
-system.cpu4: completed 50000 read, 26997 write accesses @2920489
-system.cpu0: completed 50000 read, 27072 write accesses @2924735
-system.cpu1: completed 50000 read, 27407 write accesses @2925503
-system.cpu7: completed 50000 read, 27387 write accesses @2927681
-system.cpu2: completed 60000 read, 32632 write accesses @3474793
-system.cpu6: completed 60000 read, 32472 write accesses @3482759
-system.cpu3: completed 60000 read, 32504 write accesses @3487367
-system.cpu0: completed 60000 read, 32401 write accesses @3493294
-system.cpu4: completed 60000 read, 32171 write accesses @3498890
-system.cpu5: completed 60000 read, 32778 write accesses @3503066
-system.cpu1: completed 60000 read, 32891 write accesses @3509381
-system.cpu7: completed 60000 read, 32765 write accesses @3516772
-system.cpu2: completed 70000 read, 38066 write accesses @4058828
-system.cpu3: completed 70000 read, 37916 write accesses @4058910
-system.cpu6: completed 70000 read, 37885 write accesses @4063852
-system.cpu4: completed 70000 read, 37622 write accesses @4080369
-system.cpu0: completed 70000 read, 37925 write accesses @4085861
-system.cpu5: completed 70000 read, 38249 write accesses @4094801
-system.cpu1: completed 70000 read, 38488 write accesses @4095495
-system.cpu7: completed 70000 read, 38117 write accesses @4097708
-system.cpu2: completed 80000 read, 43433 write accesses @4639406
-system.cpu3: completed 80000 read, 43416 write accesses @4647614
-system.cpu6: completed 80000 read, 43333 write accesses @4648301
-system.cpu5: completed 80000 read, 43562 write accesses @4662354
-system.cpu0: completed 80000 read, 43227 write accesses @4664558
-system.cpu4: completed 80000 read, 43117 write accesses @4665549
-system.cpu1: completed 80000 read, 43838 write accesses @4675271
-system.cpu7: completed 80000 read, 43557 write accesses @4676998
-system.cpu2: completed 90000 read, 48793 write accesses @5208478
-system.cpu3: completed 90000 read, 48771 write accesses @5220479
-system.cpu6: completed 90000 read, 48900 write accesses @5227295
-system.cpu5: completed 90000 read, 48930 write accesses @5242795
-system.cpu1: completed 90000 read, 49220 write accesses @5246394
-system.cpu0: completed 90000 read, 48602 write accesses @5246963
-system.cpu4: completed 90000 read, 48456 write accesses @5248509
-system.cpu7: completed 90000 read, 48936 write accesses @5260982
-system.cpu2: completed 100000 read, 54294 write accesses @5795833
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu4: completed 10000 read, 5516 write accesses @584228
+system.cpu5: completed 10000 read, 5515 write accesses @587183
+system.cpu1: completed 10000 read, 5491 write accesses @591446
+system.cpu7: completed 10000 read, 5626 write accesses @595409
+system.cpu2: completed 10000 read, 5637 write accesses @596437
+system.cpu6: completed 10000 read, 5437 write accesses @597608
+system.cpu3: completed 10000 read, 5738 write accesses @597986
+system.cpu0: completed 10000 read, 5730 write accesses @601184
+system.cpu4: completed 20000 read, 11120 write accesses @1170250
+system.cpu6: completed 20000 read, 10900 write accesses @1171579
+system.cpu3: completed 20000 read, 11193 write accesses @1184267
+system.cpu1: completed 20000 read, 11047 write accesses @1190135
+system.cpu5: completed 20000 read, 11070 write accesses @1191953
+system.cpu7: completed 20000 read, 11317 write accesses @1192073
+system.cpu2: completed 20000 read, 11059 write accesses @1192934
+system.cpu0: completed 20000 read, 11218 write accesses @1196582
+system.cpu6: completed 30000 read, 16404 write accesses @1756097
+system.cpu4: completed 30000 read, 16698 write accesses @1768219
+system.cpu7: completed 30000 read, 16835 write accesses @1769427
+system.cpu3: completed 30000 read, 16672 write accesses @1773026
+system.cpu1: completed 30000 read, 16602 write accesses @1773962
+system.cpu0: completed 30000 read, 16781 write accesses @1777262
+system.cpu5: completed 30000 read, 16565 write accesses @1782900
+system.cpu2: completed 30000 read, 16614 write accesses @1785263
+system.cpu6: completed 40000 read, 22003 write accesses @2340507
+system.cpu1: completed 40000 read, 22145 write accesses @2358116
+system.cpu0: completed 40000 read, 22355 write accesses @2364775
+system.cpu7: completed 40000 read, 22565 write accesses @2374538
+system.cpu2: completed 40000 read, 22222 write accesses @2375711
+system.cpu4: completed 40000 read, 22294 write accesses @2376781
+system.cpu3: completed 40000 read, 22360 write accesses @2377205
+system.cpu5: completed 40000 read, 22099 write accesses @2379118
+system.cpu6: completed 50000 read, 27600 write accesses @2941333
+system.cpu1: completed 50000 read, 27821 write accesses @2946145
+system.cpu0: completed 50000 read, 27935 write accesses @2959151
+system.cpu2: completed 50000 read, 27794 write accesses @2968804
+system.cpu3: completed 50000 read, 27849 write accesses @2971166
+system.cpu5: completed 50000 read, 27657 write accesses @2977357
+system.cpu4: completed 50000 read, 27828 write accesses @2978259
+system.cpu7: completed 50000 read, 28284 write accesses @2978857
+system.cpu6: completed 60000 read, 33178 write accesses @3536924
+system.cpu1: completed 60000 read, 33394 write accesses @3543961
+system.cpu2: completed 60000 read, 33230 write accesses @3549333
+system.cpu0: completed 60000 read, 33564 write accesses @3564287
+system.cpu3: completed 60000 read, 33336 write accesses @3569137
+system.cpu4: completed 60000 read, 33587 write accesses @3570593
+system.cpu5: completed 60000 read, 33166 write accesses @3576647
+system.cpu7: completed 60000 read, 33832 write accesses @3577075
+system.cpu6: completed 70000 read, 38652 write accesses @4137461
+system.cpu2: completed 70000 read, 38824 write accesses @4141010
+system.cpu1: completed 70000 read, 39043 write accesses @4142171
+system.cpu4: completed 70000 read, 39136 write accesses @4148986
+system.cpu5: completed 70000 read, 38716 write accesses @4161730
+system.cpu0: completed 70000 read, 39119 write accesses @4165271
+system.cpu3: completed 70000 read, 38875 write accesses @4169555
+system.cpu7: completed 70000 read, 39501 write accesses @4176068
+system.cpu6: completed 80000 read, 44287 write accesses @4740297
+system.cpu2: completed 80000 read, 44433 write accesses @4742323
+system.cpu4: completed 80000 read, 44799 write accesses @4743294
+system.cpu0: completed 80000 read, 44555 write accesses @4750388
+system.cpu1: completed 80000 read, 44835 write accesses @4751884
+system.cpu5: completed 80000 read, 44235 write accesses @4755731
+system.cpu3: completed 80000 read, 44536 write accesses @4756531
+system.cpu7: completed 80000 read, 45051 write accesses @4789789
+system.cpu2: completed 90000 read, 50085 write accesses @5331779
+system.cpu1: completed 90000 read, 50520 write accesses @5335067
+system.cpu6: completed 90000 read, 50077 write accesses @5343428
+system.cpu4: completed 90000 read, 50348 write accesses @5344112
+system.cpu5: completed 90000 read, 49814 write accesses @5348125
+system.cpu3: completed 90000 read, 50170 write accesses @5349617
+system.cpu0: completed 90000 read, 50102 write accesses @5350612
+system.cpu7: completed 90000 read, 50733 write accesses @5394074
+system.cpu1: completed 100000 read, 56034 write accesses @5920895
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 12c7c969e..0a7886e85 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index 5a7e36bf9..b3b846e79 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: rounding error > tolerance
0.072760 rounded to 0
-system.cpu4: completed 10000 read, 5267 write accesses @855219
-system.cpu7: completed 10000 read, 5381 write accesses @861031
-system.cpu1: completed 10000 read, 5262 write accesses @863126
-system.cpu2: completed 10000 read, 5381 write accesses @864460
-system.cpu0: completed 10000 read, 5401 write accesses @867419
-system.cpu3: completed 10000 read, 5382 write accesses @869141
-system.cpu5: completed 10000 read, 5455 write accesses @872828
-system.cpu6: completed 10000 read, 5482 write accesses @879392
-system.cpu7: completed 20000 read, 10628 write accesses @1724117
-system.cpu2: completed 20000 read, 10953 write accesses @1730360
-system.cpu1: completed 20000 read, 10550 write accesses @1730621
-system.cpu3: completed 20000 read, 10808 write accesses @1733195
-system.cpu4: completed 20000 read, 10816 write accesses @1737229
-system.cpu0: completed 20000 read, 10790 write accesses @1746955
-system.cpu6: completed 20000 read, 11016 write accesses @1749077
-system.cpu5: completed 20000 read, 10800 write accesses @1759742
-system.cpu3: completed 30000 read, 16255 write accesses @2586824
-system.cpu7: completed 30000 read, 15936 write accesses @2587214
-system.cpu0: completed 30000 read, 16091 write accesses @2589409
-system.cpu2: completed 30000 read, 16288 write accesses @2595682
-system.cpu4: completed 30000 read, 16193 write accesses @2610317
-system.cpu6: completed 30000 read, 16368 write accesses @2614352
-system.cpu5: completed 30000 read, 16095 write accesses @2624564
-system.cpu1: completed 30000 read, 16153 write accesses @2637701
-system.cpu7: completed 40000 read, 21310 write accesses @3438977
-system.cpu0: completed 40000 read, 21543 write accesses @3451234
-system.cpu2: completed 40000 read, 21712 write accesses @3460847
-system.cpu3: completed 40000 read, 21652 write accesses @3468818
-system.cpu6: completed 40000 read, 21709 write accesses @3479513
-system.cpu4: completed 40000 read, 21724 write accesses @3497567
-system.cpu5: completed 40000 read, 21477 write accesses @3498797
-system.cpu1: completed 40000 read, 21640 write accesses @3521390
-system.cpu7: completed 50000 read, 26683 write accesses @4309027
-system.cpu2: completed 50000 read, 27008 write accesses @4319999
-system.cpu0: completed 50000 read, 26993 write accesses @4330940
-system.cpu6: completed 50000 read, 27072 write accesses @4336165
-system.cpu3: completed 50000 read, 27085 write accesses @4352827
-system.cpu5: completed 50000 read, 26964 write accesses @4357459
-system.cpu4: completed 50000 read, 27198 write accesses @4384075
-system.cpu1: completed 50000 read, 27029 write accesses @4398757
-system.cpu7: completed 60000 read, 32063 write accesses @5160248
-system.cpu0: completed 60000 read, 32443 write accesses @5203475
-system.cpu2: completed 60000 read, 32367 write accesses @5205683
-system.cpu6: completed 60000 read, 32517 write accesses @5225171
-system.cpu3: completed 60000 read, 32534 write accesses @5227022
-system.cpu5: completed 60000 read, 32552 write accesses @5229640
-system.cpu1: completed 60000 read, 32592 write accesses @5258417
-system.cpu4: completed 60000 read, 32682 write accesses @5263781
-system.cpu7: completed 70000 read, 37467 write accesses @6033043
-system.cpu0: completed 70000 read, 37995 write accesses @6081225
-system.cpu6: completed 70000 read, 37873 write accesses @6089309
-system.cpu3: completed 70000 read, 38002 write accesses @6091981
-system.cpu2: completed 70000 read, 37862 write accesses @6093259
-system.cpu5: completed 70000 read, 38035 write accesses @6114916
-system.cpu1: completed 70000 read, 38024 write accesses @6119174
-system.cpu4: completed 70000 read, 38117 write accesses @6129370
-system.cpu7: completed 80000 read, 42779 write accesses @6903893
-system.cpu0: completed 80000 read, 43420 write accesses @6927865
-system.cpu6: completed 80000 read, 43280 write accesses @6952004
-system.cpu3: completed 80000 read, 43445 write accesses @6966407
-system.cpu5: completed 80000 read, 43493 write accesses @6966458
-system.cpu2: completed 80000 read, 43456 write accesses @6967571
-system.cpu1: completed 80000 read, 43311 write accesses @6981707
-system.cpu4: completed 80000 read, 43712 write accesses @7010960
-system.cpu7: completed 90000 read, 48212 write accesses @7781504
-system.cpu0: completed 90000 read, 49018 write accesses @7809551
-system.cpu6: completed 90000 read, 48768 write accesses @7821401
-system.cpu2: completed 90000 read, 48919 write accesses @7841558
-system.cpu1: completed 90000 read, 48631 write accesses @7843811
-system.cpu3: completed 90000 read, 49017 write accesses @7850422
-system.cpu5: completed 90000 read, 49075 write accesses @7851926
-system.cpu4: completed 90000 read, 49432 write accesses @7874435
-system.cpu7: completed 100000 read, 53796 write accesses @8664886
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu0: completed 10000 read, 5556 write accesses @879323
+system.cpu7: completed 10000 read, 5668 write accesses @879866
+system.cpu4: completed 10000 read, 5446 write accesses @880130
+system.cpu2: completed 10000 read, 5618 write accesses @882610
+system.cpu3: completed 10000 read, 5567 write accesses @889766
+system.cpu5: completed 10000 read, 5601 write accesses @889804
+system.cpu6: completed 10000 read, 5691 write accesses @907393
+system.cpu1: completed 10000 read, 5703 write accesses @911150
+system.cpu0: completed 20000 read, 11066 write accesses @1759277
+system.cpu7: completed 20000 read, 11260 write accesses @1770595
+system.cpu4: completed 20000 read, 11011 write accesses @1777119
+system.cpu2: completed 20000 read, 11410 write accesses @1779287
+system.cpu3: completed 20000 read, 11162 write accesses @1783007
+system.cpu5: completed 20000 read, 11166 write accesses @1789252
+system.cpu6: completed 20000 read, 11205 write accesses @1795677
+system.cpu1: completed 20000 read, 11246 write accesses @1799288
+system.cpu0: completed 30000 read, 16538 write accesses @2628765
+system.cpu4: completed 30000 read, 16331 write accesses @2649038
+system.cpu3: completed 30000 read, 16729 write accesses @2656841
+system.cpu7: completed 30000 read, 16821 write accesses @2657779
+system.cpu2: completed 30000 read, 16942 write accesses @2665738
+system.cpu6: completed 30000 read, 16767 write accesses @2683028
+system.cpu5: completed 30000 read, 16740 write accesses @2683223
+system.cpu1: completed 30000 read, 16843 write accesses @2687354
+system.cpu0: completed 40000 read, 21978 write accesses @3518323
+system.cpu4: completed 40000 read, 21923 write accesses @3532643
+system.cpu2: completed 40000 read, 22312 write accesses @3539629
+system.cpu7: completed 40000 read, 22397 write accesses @3540563
+system.cpu3: completed 40000 read, 22394 write accesses @3545743
+system.cpu1: completed 40000 read, 22522 write accesses @3569491
+system.cpu6: completed 40000 read, 22217 write accesses @3571115
+system.cpu5: completed 40000 read, 22361 write accesses @3575245
+system.cpu0: completed 50000 read, 27412 write accesses @4395937
+system.cpu4: completed 50000 read, 27504 write accesses @4402816
+system.cpu2: completed 50000 read, 27861 write accesses @4421377
+system.cpu7: completed 50000 read, 28050 write accesses @4432946
+system.cpu3: completed 50000 read, 28057 write accesses @4453484
+system.cpu5: completed 50000 read, 28091 write accesses @4459262
+system.cpu6: completed 50000 read, 27767 write accesses @4466993
+system.cpu1: completed 50000 read, 28057 write accesses @4473556
+system.cpu0: completed 60000 read, 33045 write accesses @5302811
+system.cpu2: completed 60000 read, 33521 write accesses @5307713
+system.cpu4: completed 60000 read, 33106 write accesses @5309735
+system.cpu3: completed 60000 read, 33613 write accesses @5326889
+system.cpu7: completed 60000 read, 33738 write accesses @5327419
+system.cpu1: completed 60000 read, 33648 write accesses @5345018
+system.cpu6: completed 60000 read, 33262 write accesses @5350442
+system.cpu5: completed 60000 read, 33765 write accesses @5365882
+system.cpu4: completed 70000 read, 38688 write accesses @6177299
+system.cpu0: completed 70000 read, 38751 write accesses @6203477
+system.cpu2: completed 70000 read, 39098 write accesses @6206063
+system.cpu3: completed 70000 read, 39126 write accesses @6219412
+system.cpu1: completed 70000 read, 39169 write accesses @6222370
+system.cpu6: completed 70000 read, 38802 write accesses @6223076
+system.cpu7: completed 70000 read, 39595 write accesses @6226670
+system.cpu5: completed 70000 read, 39326 write accesses @6257626
+system.cpu4: completed 80000 read, 44383 write accesses @7068978
+system.cpu2: completed 80000 read, 44769 write accesses @7095466
+system.cpu3: completed 80000 read, 44569 write accesses @7095782
+system.cpu0: completed 80000 read, 44509 write accesses @7100023
+system.cpu6: completed 80000 read, 44542 write accesses @7108504
+system.cpu1: completed 80000 read, 44592 write accesses @7113439
+system.cpu7: completed 80000 read, 45281 write accesses @7113500
+system.cpu5: completed 80000 read, 44911 write accesses @7150684
+system.cpu4: completed 90000 read, 50048 write accesses @7961758
+system.cpu0: completed 90000 read, 49958 write accesses @7968130
+system.cpu2: completed 90000 read, 50371 write accesses @7973060
+system.cpu3: completed 90000 read, 50104 write accesses @7976843
+system.cpu7: completed 90000 read, 50805 write accesses @7986452
+system.cpu6: completed 90000 read, 50102 write accesses @7998542
+system.cpu1: completed 90000 read, 50241 write accesses @7999593
+system.cpu5: completed 90000 read, 50481 write accesses @8039612
+system.cpu7: completed 100000 read, 56250 write accesses @8851106
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
index b9c14dc5f..6605d530a 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -10,13 +10,14 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -37,7 +38,9 @@ system_port=system.membus.slave[1]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu0]
@@ -491,11 +494,21 @@ size=32768
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -553,7 +566,7 @@ sequential_access=false
size=65536
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
eventq_index=0
@@ -585,7 +598,7 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
index 70113e2a8..16ab1a5b8 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
@@ -1,74 +1,73 @@
-warn: failed to generate dot output from build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/config.dot
-system.cpu6: completed 10000 read, 5415 write accesses @145109000
-system.cpu2: completed 10000 read, 5349 write accesses @145417500
-system.cpu1: completed 10000 read, 5329 write accesses @146140000
-system.cpu0: completed 10000 read, 5371 write accesses @146497000
-system.cpu4: completed 10000 read, 5466 write accesses @147507000
-system.cpu3: completed 10000 read, 5586 write accesses @147982000
-system.cpu5: completed 10000 read, 5427 write accesses @148047500
-system.cpu7: completed 10000 read, 5356 write accesses @148467500
-system.cpu6: completed 20000 read, 10673 write accesses @289538000
-system.cpu2: completed 20000 read, 10526 write accesses @290832000
-system.cpu1: completed 20000 read, 10766 write accesses @292890999
-system.cpu5: completed 20000 read, 10736 write accesses @293627000
-system.cpu7: completed 20000 read, 10730 write accesses @293693000
-system.cpu0: completed 20000 read, 10671 write accesses @294206500
-system.cpu4: completed 20000 read, 10944 write accesses @296769500
-system.cpu3: completed 20000 read, 10962 write accesses @297951000
-system.cpu2: completed 30000 read, 15840 write accesses @436954000
-system.cpu1: completed 30000 read, 16134 write accesses @439432500
-system.cpu6: completed 30000 read, 16128 write accesses @439710500
-system.cpu7: completed 30000 read, 16048 write accesses @440819000
-system.cpu5: completed 30000 read, 16126 write accesses @441698000
-system.cpu3: completed 30000 read, 16409 write accesses @444974000
-system.cpu4: completed 30000 read, 16439 write accesses @445869500
-system.cpu0: completed 30000 read, 16254 write accesses @446194000
-system.cpu2: completed 40000 read, 21231 write accesses @582932500
-system.cpu6: completed 40000 read, 21466 write accesses @586141500
-system.cpu1: completed 40000 read, 21414 write accesses @588066500
-system.cpu3: completed 40000 read, 21735 write accesses @588220000
-system.cpu5: completed 40000 read, 21572 write accesses @588767000
-system.cpu7: completed 40000 read, 21513 write accesses @590091000
-system.cpu0: completed 40000 read, 21682 write accesses @592843000
-system.cpu4: completed 40000 read, 21885 write accesses @593488000
-system.cpu2: completed 50000 read, 26639 write accesses @730512000
-system.cpu3: completed 50000 read, 26953 write accesses @733051500
-system.cpu6: completed 50000 read, 26889 write accesses @736295000
-system.cpu1: completed 50000 read, 26860 write accesses @736946500
-system.cpu4: completed 50000 read, 27157 write accesses @739104500
-system.cpu5: completed 50000 read, 27043 write accesses @739175000
-system.cpu7: completed 50000 read, 27030 write accesses @739274500
-system.cpu0: completed 50000 read, 27007 write accesses @740081999
-system.cpu2: completed 60000 read, 31935 write accesses @875520000
-system.cpu3: completed 60000 read, 32327 write accesses @878608000
-system.cpu1: completed 60000 read, 32037 write accesses @880758000
-system.cpu5: completed 60000 read, 32374 write accesses @883996500
-system.cpu4: completed 60000 read, 32578 write accesses @885209000
-system.cpu6: completed 60000 read, 32302 write accesses @886481999
-system.cpu0: completed 60000 read, 32356 write accesses @886645000
-system.cpu7: completed 60000 read, 32534 write accesses @888148500
-system.cpu3: completed 70000 read, 37577 write accesses @1026143000
-system.cpu2: completed 70000 read, 37542 write accesses @1027029999
-system.cpu1: completed 70000 read, 37457 write accesses @1029024000
-system.cpu5: completed 70000 read, 37722 write accesses @1029495500
-system.cpu6: completed 70000 read, 37640 write accesses @1032918500
-system.cpu0: completed 70000 read, 37692 write accesses @1034293500
-system.cpu7: completed 70000 read, 37955 write accesses @1034390500
-system.cpu4: completed 70000 read, 38136 write accesses @1036569000
-system.cpu3: completed 80000 read, 42898 write accesses @1173212500
-system.cpu2: completed 80000 read, 42932 write accesses @1173575000
-system.cpu1: completed 80000 read, 42886 write accesses @1177639500
-system.cpu5: completed 80000 read, 43232 write accesses @1178175000
-system.cpu0: completed 80000 read, 42958 write accesses @1178771500
-system.cpu6: completed 80000 read, 42919 write accesses @1180797000
-system.cpu7: completed 80000 read, 43430 write accesses @1183823000
-system.cpu4: completed 80000 read, 43550 write accesses @1185935999
-system.cpu2: completed 90000 read, 48239 write accesses @1319473000
-system.cpu3: completed 90000 read, 48329 write accesses @1322081500
-system.cpu1: completed 90000 read, 48223 write accesses @1323240500
-system.cpu5: completed 90000 read, 48632 write accesses @1326787000
-system.cpu0: completed 90000 read, 48351 write accesses @1327807500
-system.cpu6: completed 90000 read, 48287 write accesses @1329208000
-system.cpu7: completed 90000 read, 48796 write accesses @1329462500
-system.cpu4: completed 90000 read, 48969 write accesses @1334198500
-system.cpu2: completed 100000 read, 53603 write accesses @1466014000
+system.cpu4: completed 10000 read, 5317 write accesses @146612000
+system.cpu3: completed 10000 read, 5592 write accesses @148872500
+system.cpu7: completed 10000 read, 5446 write accesses @149754500
+system.cpu0: completed 10000 read, 5432 write accesses @150141500
+system.cpu1: completed 10000 read, 5693 write accesses @151929000
+system.cpu2: completed 10000 read, 5680 write accesses @152039000
+system.cpu6: completed 10000 read, 5624 write accesses @152462500
+system.cpu5: completed 10000 read, 5650 write accesses @153139000
+system.cpu4: completed 20000 read, 10841 write accesses @294897500
+system.cpu3: completed 20000 read, 11252 write accesses @295891500
+system.cpu0: completed 20000 read, 10771 write accesses @296321000
+system.cpu6: completed 20000 read, 11129 write accesses @300503000
+system.cpu1: completed 20000 read, 11154 write accesses @303003500
+system.cpu7: completed 20000 read, 11162 write accesses @303067000
+system.cpu5: completed 20000 read, 11275 write accesses @305007000
+system.cpu2: completed 20000 read, 11301 write accesses @305237000
+system.cpu4: completed 30000 read, 16293 write accesses @441647000
+system.cpu0: completed 30000 read, 16339 write accesses @446349998
+system.cpu6: completed 30000 read, 16630 write accesses @450155000
+system.cpu1: completed 30000 read, 16474 write accesses @451775000
+system.cpu3: completed 30000 read, 16954 write accesses @452288000
+system.cpu7: completed 30000 read, 16778 write accesses @453662000
+system.cpu5: completed 30000 read, 16839 write accesses @456398000
+system.cpu2: completed 30000 read, 16838 write accesses @457529500
+system.cpu4: completed 40000 read, 21515 write accesses @587133500
+system.cpu0: completed 40000 read, 21712 write accesses @594544000
+system.cpu6: completed 40000 read, 22199 write accesses @599911000
+system.cpu3: completed 40000 read, 22436 write accesses @600303500
+system.cpu1: completed 40000 read, 22001 write accesses @603916500
+system.cpu7: completed 40000 read, 22291 write accesses @604899500
+system.cpu5: completed 40000 read, 22433 write accesses @607477000
+system.cpu2: completed 40000 read, 22541 write accesses @610042000
+system.cpu4: completed 50000 read, 27094 write accesses @738435000
+system.cpu0: completed 50000 read, 27172 write accesses @744686500
+system.cpu3: completed 50000 read, 27887 write accesses @749000500
+system.cpu1: completed 50000 read, 27549 write accesses @751936500
+system.cpu6: completed 50000 read, 27775 write accesses @752183500
+system.cpu7: completed 50000 read, 27920 write accesses @756029000
+system.cpu5: completed 50000 read, 27984 write accesses @756496000
+system.cpu2: completed 50000 read, 27916 write accesses @758896000
+system.cpu4: completed 60000 read, 32601 write accesses @886900500
+system.cpu0: completed 60000 read, 32631 write accesses @892444000
+system.cpu1: completed 60000 read, 33102 write accesses @899938000
+system.cpu3: completed 60000 read, 33481 write accesses @900956500
+system.cpu6: completed 60000 read, 33392 write accesses @901773000
+system.cpu5: completed 60000 read, 33565 write accesses @904995500
+system.cpu2: completed 60000 read, 33466 write accesses @909744500
+system.cpu7: completed 60000 read, 33536 write accesses @910295999
+system.cpu4: completed 70000 read, 38175 write accesses @1036375499
+system.cpu0: completed 70000 read, 38106 write accesses @1040049000
+system.cpu6: completed 70000 read, 38841 write accesses @1048673000
+system.cpu1: completed 70000 read, 38668 write accesses @1049885000
+system.cpu3: completed 70000 read, 39114 write accesses @1053709500
+system.cpu5: completed 70000 read, 39200 write accesses @1055942500
+system.cpu2: completed 70000 read, 38856 write accesses @1057747499
+system.cpu7: completed 70000 read, 39064 write accesses @1059368500
+system.cpu4: completed 80000 read, 43619 write accesses @1185369000
+system.cpu0: completed 80000 read, 43549 write accesses @1189974500
+system.cpu6: completed 80000 read, 44374 write accesses @1198657499
+system.cpu1: completed 80000 read, 43973 write accesses @1199665500
+system.cpu3: completed 80000 read, 44602 write accesses @1199968000
+system.cpu5: completed 80000 read, 44843 write accesses @1207585500
+system.cpu2: completed 80000 read, 44389 write accesses @1209591000
+system.cpu7: completed 80000 read, 44629 write accesses @1211090500
+system.cpu4: completed 90000 read, 49142 write accesses @1333753500
+system.cpu0: completed 90000 read, 49249 write accesses @1339029000
+system.cpu1: completed 90000 read, 49469 write accesses @1348019000
+system.cpu6: completed 90000 read, 50013 write accesses @1351048500
+system.cpu3: completed 90000 read, 50231 write accesses @1351323000
+system.cpu5: completed 90000 read, 50311 write accesses @1355589000
+system.cpu7: completed 90000 read, 50146 write accesses @1357457500
+system.cpu2: completed 90000 read, 49997 write accesses @1360771999
+system.cpu4: completed 100000 read, 54692 write accesses @1486654500
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 62f705803..06da0f372 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -22,7 +22,7 @@ load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
num_work_ids=16
readfile=
symbolfile=
@@ -508,7 +508,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -566,10 +566,11 @@ sequential_access=false
size=65536
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=16
@@ -590,10 +591,11 @@ range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=16
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
index 084f6f6ab..b2fb4093d 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
@@ -1,73 +1,73 @@
-system.cpu6: completed 10000 read, 5217 write accesses @68085999
-system.cpu4: completed 10000 read, 5435 write accesses @69661000
-system.cpu2: completed 10000 read, 5368 write accesses @70121500
-system.cpu3: completed 10000 read, 5457 write accesses @70317500
-system.cpu1: completed 10000 read, 5387 write accesses @70875500
-system.cpu7: completed 10000 read, 5470 write accesses @70949000
-system.cpu0: completed 10000 read, 5435 write accesses @71227500
-system.cpu5: completed 10000 read, 5514 write accesses @71894000
-system.cpu6: completed 20000 read, 10518 write accesses @132327500
-system.cpu4: completed 20000 read, 10839 write accesses @133525000
-system.cpu1: completed 20000 read, 10784 write accesses @134714500
-system.cpu7: completed 20000 read, 10701 write accesses @135318500
-system.cpu0: completed 20000 read, 10821 write accesses @135563500
-system.cpu2: completed 20000 read, 10843 write accesses @135684500
-system.cpu3: completed 20000 read, 10685 write accesses @135938500
-system.cpu5: completed 20000 read, 11031 write accesses @136425000
-system.cpu6: completed 30000 read, 16001 write accesses @197849500
-system.cpu4: completed 30000 read, 16254 write accesses @198725500
-system.cpu0: completed 30000 read, 16109 write accesses @199579499
-system.cpu1: completed 30000 read, 16209 write accesses @200016500
-system.cpu5: completed 30000 read, 16414 write accesses @200525000
-system.cpu3: completed 30000 read, 15978 write accesses @200724000
-system.cpu7: completed 30000 read, 16153 write accesses @201563500
-system.cpu2: completed 30000 read, 16316 write accesses @202401999
-system.cpu4: completed 40000 read, 21506 write accesses @263053500
-system.cpu6: completed 40000 read, 21338 write accesses @263431500
-system.cpu5: completed 40000 read, 21670 write accesses @263987000
-system.cpu3: completed 40000 read, 21219 write accesses @264608000
-system.cpu1: completed 40000 read, 21536 write accesses @265348500
-system.cpu0: completed 40000 read, 21604 write accesses @265426500
-system.cpu7: completed 40000 read, 21465 write accesses @265674000
-system.cpu2: completed 40000 read, 21690 write accesses @268754000
-system.cpu6: completed 50000 read, 26563 write accesses @327819000
-system.cpu4: completed 50000 read, 27066 write accesses @328101000
-system.cpu5: completed 50000 read, 26900 write accesses @328372000
-system.cpu3: completed 50000 read, 26596 write accesses @328811500
-system.cpu1: completed 50000 read, 26845 write accesses @328908500
-system.cpu7: completed 50000 read, 26873 write accesses @331316999
-system.cpu0: completed 50000 read, 26988 write accesses @331358000
-system.cpu2: completed 50000 read, 27102 write accesses @333876000
-system.cpu1: completed 60000 read, 32156 write accesses @392077000
-system.cpu6: completed 60000 read, 31998 write accesses @392784000
-system.cpu5: completed 60000 read, 32223 write accesses @393227500
-system.cpu4: completed 60000 read, 32446 write accesses @394175000
-system.cpu3: completed 60000 read, 32090 write accesses @394842000
-system.cpu0: completed 60000 read, 32282 write accesses @395716500
-system.cpu7: completed 60000 read, 32292 write accesses @397180000
-system.cpu2: completed 60000 read, 32266 write accesses @397288500
-system.cpu6: completed 70000 read, 37440 write accesses @457780500
-system.cpu1: completed 70000 read, 37577 write accesses @458242500
-system.cpu5: completed 70000 read, 37616 write accesses @458643500
-system.cpu4: completed 70000 read, 37952 write accesses @459569500
-system.cpu3: completed 70000 read, 37486 write accesses @460007500
-system.cpu0: completed 70000 read, 37804 write accesses @461418499
-system.cpu2: completed 70000 read, 37588 write accesses @461790000
-system.cpu7: completed 70000 read, 37743 write accesses @462130500
-system.cpu1: completed 80000 read, 42976 write accesses @523192500
-system.cpu5: completed 80000 read, 43028 write accesses @523895500
-system.cpu6: completed 80000 read, 42870 write accesses @524155000
-system.cpu4: completed 80000 read, 43341 write accesses @524226000
-system.cpu3: completed 80000 read, 42885 write accesses @524383000
-system.cpu2: completed 80000 read, 43005 write accesses @527239000
-system.cpu7: completed 80000 read, 43156 write accesses @528371000
-system.cpu0: completed 80000 read, 43239 write accesses @528519000
-system.cpu3: completed 90000 read, 48037 write accesses @586595000
-system.cpu1: completed 90000 read, 48299 write accesses @588010000
-system.cpu4: completed 90000 read, 48806 write accesses @589147500
-system.cpu6: completed 90000 read, 48454 write accesses @589844000
-system.cpu5: completed 90000 read, 48341 write accesses @590185000
-system.cpu2: completed 90000 read, 48395 write accesses @591584000
-system.cpu7: completed 90000 read, 48496 write accesses @592485000
-system.cpu0: completed 90000 read, 48680 write accesses @594831500
-system.cpu3: completed 100000 read, 53536 write accesses @652606500
+system.cpu1: completed 10000 read, 5362 write accesses @70749500
+system.cpu6: completed 10000 read, 5537 write accesses @71195000
+system.cpu7: completed 10000 read, 5519 write accesses @71360000
+system.cpu4: completed 10000 read, 5569 write accesses @71442000
+system.cpu3: completed 10000 read, 5551 write accesses @71947000
+system.cpu5: completed 10000 read, 5610 write accesses @72351000
+system.cpu2: completed 10000 read, 5548 write accesses @72366000
+system.cpu0: completed 10000 read, 5597 write accesses @72604000
+system.cpu1: completed 20000 read, 10810 write accesses @136799000
+system.cpu6: completed 20000 read, 11150 write accesses @137085000
+system.cpu4: completed 20000 read, 11041 write accesses @137243000
+system.cpu5: completed 20000 read, 11255 write accesses @138165500
+system.cpu7: completed 20000 read, 11207 write accesses @138180500
+system.cpu3: completed 20000 read, 11018 write accesses @138711500
+system.cpu2: completed 20000 read, 11094 write accesses @139138500
+system.cpu0: completed 20000 read, 11219 write accesses @140219500
+system.cpu5: completed 30000 read, 16778 write accesses @203366500
+system.cpu6: completed 30000 read, 16566 write accesses @203972500
+system.cpu4: completed 30000 read, 16724 write accesses @204003000
+system.cpu1: completed 30000 read, 16364 write accesses @204656500
+system.cpu2: completed 30000 read, 16663 write accesses @204765000
+system.cpu7: completed 30000 read, 16867 write accesses @205681500
+system.cpu3: completed 30000 read, 16606 write accesses @205970500
+system.cpu0: completed 30000 read, 16763 write accesses @207333500
+system.cpu5: completed 40000 read, 22274 write accesses @268156500
+system.cpu6: completed 40000 read, 22009 write accesses @269534000
+system.cpu2: completed 40000 read, 22255 write accesses @271458500
+system.cpu4: completed 40000 read, 22360 write accesses @272143500
+system.cpu0: completed 40000 read, 22178 write accesses @272544500
+system.cpu1: completed 40000 read, 22131 write accesses @272652000
+system.cpu3: completed 40000 read, 22246 write accesses @273210500
+system.cpu7: completed 40000 read, 22431 write accesses @273722500
+system.cpu5: completed 50000 read, 27739 write accesses @335077500
+system.cpu6: completed 50000 read, 27540 write accesses @335500500
+system.cpu4: completed 50000 read, 27805 write accesses @337842000
+system.cpu7: completed 50000 read, 27755 write accesses @337879500
+system.cpu2: completed 50000 read, 27750 write accesses @338436000
+system.cpu0: completed 50000 read, 27692 write accesses @339374000
+system.cpu1: completed 50000 read, 27828 write accesses @340225500
+system.cpu3: completed 50000 read, 27884 write accesses @341199000
+system.cpu5: completed 60000 read, 33220 write accesses @401069000
+system.cpu6: completed 60000 read, 33064 write accesses @401171000
+system.cpu7: completed 60000 read, 33318 write accesses @402700500
+system.cpu4: completed 60000 read, 33407 write accesses @404241000
+system.cpu2: completed 60000 read, 33248 write accesses @404642000
+system.cpu0: completed 60000 read, 33222 write accesses @405992500
+system.cpu1: completed 60000 read, 33452 write accesses @407711000
+system.cpu3: completed 60000 read, 33293 write accesses @408190000
+system.cpu6: completed 70000 read, 38545 write accesses @467631000
+system.cpu5: completed 70000 read, 38773 write accesses @467786500
+system.cpu7: completed 70000 read, 38817 write accesses @468768499
+system.cpu2: completed 70000 read, 38804 write accesses @470615500
+system.cpu4: completed 70000 read, 38942 write accesses @471024500
+system.cpu1: completed 70000 read, 38924 write accesses @472741500
+system.cpu0: completed 70000 read, 38792 write accesses @473888500
+system.cpu3: completed 70000 read, 38873 write accesses @474437500
+system.cpu5: completed 80000 read, 44156 write accesses @533178500
+system.cpu6: completed 80000 read, 44068 write accesses @534028500
+system.cpu7: completed 80000 read, 44398 write accesses @535850500
+system.cpu2: completed 80000 read, 44302 write accesses @537573000
+system.cpu4: completed 80000 read, 44462 write accesses @538315000
+system.cpu0: completed 80000 read, 44312 write accesses @540158500
+system.cpu1: completed 80000 read, 44676 write accesses @540667000
+system.cpu3: completed 80000 read, 44446 write accesses @541285000
+system.cpu5: completed 90000 read, 49777 write accesses @600496000
+system.cpu6: completed 90000 read, 49628 write accesses @600631500
+system.cpu7: completed 90000 read, 49999 write accesses @603063500
+system.cpu4: completed 90000 read, 49890 write accesses @603847000
+system.cpu2: completed 90000 read, 50013 write accesses @605897999
+system.cpu1: completed 90000 read, 50188 write accesses @606811500
+system.cpu3: completed 90000 read, 49928 write accesses @606922500
+system.cpu0: completed 90000 read, 49837 write accesses @607047500
+system.cpu6: completed 100000 read, 55113 write accesses @666669000
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
index a7dfb0cb5..b1d661d27 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -67,7 +67,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -106,8 +106,33 @@ slave=system.cpu.port
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -116,6 +141,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -129,19 +155,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index bda575e80..c210da503 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -67,7 +67,7 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1