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authorNilay Vaish <nilay@cs.wisc.edu>2012-02-10 09:51:37 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-02-10 09:51:37 -0600
commit26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch)
treebf97df45e65f08107321f58d83688b08bbd3f675 /tests/quick
parent6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff)
downloadgem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/quick')
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini40
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing/simout12
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt136
3 files changed, 111 insertions, 77 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 21dc694d7..7fe95aa88 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.fuPool]
type=FUPool
@@ -445,9 +465,21 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
@@ -478,7 +510,7 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
@@ -489,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
@@ -502,7 +534,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index f402d7e9e..8159ae453 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
-gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
+gem5 compiled Feb 10 2012 00:18:03
+gem5 started Feb 10 2012 07:27:01
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 10001500 because target called exit()
+Exiting @ tick 10000500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 19b87b225..691966ecb 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10001500 # Number of ticks simulated
-final_tick 10001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 10000500 # Number of ticks simulated
+final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 15723 # Simulator instruction rate (inst/s)
-host_tick_rate 27400304 # Simulator tick rate (ticks/s)
-host_mem_usage 218472 # Number of bytes of host memory used
-host_seconds 0.37 # Real time elapsed on the host
+host_inst_rate 48981 # Simulator instruction rate (inst/s)
+host_tick_rate 85336508 # Simulator tick rate (ticks/s)
+host_mem_usage 252096 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 5739 # Number of instructions simulated
system.physmem.bytes_read 25856 # Number of bytes read from this memory
system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory
@@ -15,9 +15,9 @@ system.physmem.bytes_written 0 # Nu
system.physmem.num_reads 404 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2585212218 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1785332200 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 2585212218 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 2585470726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1785510724 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2585470726 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -61,7 +61,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 20004 # number of cpu cycles simulated
+system.cpu.numCycles 20002 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2398 # Number of BP lookups
@@ -72,8 +72,8 @@ system.cpu.BPredUnit.BTBHits 703 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6120 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12134 # Number of instructions fetch has processed
+system.cpu.fetch.icacheStallCycles 6118 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12133 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked
@@ -81,28 +81,28 @@ system.cpu.fetch.SquashCycles 1578 # Nu
system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1920 # Number of cache lines fetched
+system.cpu.fetch.CacheLines 1919 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 11510 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.338054 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.716635 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 11508 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.338286 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.716814 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 8816 76.59% 76.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 8814 76.59% 76.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 225 1.95% 82.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 227 1.97% 84.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 313 2.72% 86.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 225 1.96% 82.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 227 1.97% 84.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 313 2.72% 86.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11510 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.119876 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.606579 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6265 # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total 11508 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.119888 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.606589 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6263 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2491 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking
@@ -112,7 +112,7 @@ system.cpu.decode.BranchMispred 168 # Nu
system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6541 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 6539 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2270 # Number of cycles rename is running
@@ -139,11 +139,11 @@ system.cpu.iq.iqSquashedInstsIssued 95 # Nu
system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 11510 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.756386 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.438063 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 11508 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.756517 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.438154 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8025 69.72% 69.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8023 69.72% 69.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle
@@ -155,7 +155,7 @@ system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 11510 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 11508 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available
@@ -225,10 +225,10 @@ system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Ty
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8706 # Type of FU issued
-system.cpu.iq.rate 0.435213 # Inst issue rate
+system.cpu.iq.rate 0.435256 # Inst issue rate
system.cpu.iq.fu_busy_cnt 203 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29184 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 29182 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
@@ -269,26 +269,26 @@ system.cpu.iew.exec_nop 1 # nu
system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
system.cpu.iew.exec_branches 1354 # Number of branches executed
system.cpu.iew.exec_stores 1169 # Number of stores executed
-system.cpu.iew.exec_rate 0.414017 # Inst execution rate
+system.cpu.iew.exec_rate 0.414059 # Inst execution rate
system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7840 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3690 # num instructions producing a value
system.cpu.iew.wb_consumers 7291 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.391922 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 10624 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.540192 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.352731 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 10622 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.540294 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.352838 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8288 78.01% 78.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8286 78.01% 78.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 420 3.95% 92.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 420 3.95% 92.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle
@@ -298,7 +298,7 @@ system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 10624 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle
system.cpu.commit.count 5739 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2139 # Number of memory references committed
@@ -310,44 +310,44 @@ system.cpu.commit.int_insts 4985 # Nu
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 21207 # The number of ROB reads
+system.cpu.rob.rob_reads 21205 # The number of ROB reads
system.cpu.rob.rob_writes 22566 # The number of ROB writes
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5739 # Number of Instructions Simulated
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
-system.cpu.cpi 3.485625 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.485625 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.286893 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.286893 # IPC: Total IPC of All Threads
+system.cpu.cpi 3.485276 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.485276 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.286921 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.286921 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 37816 # number of integer regfile reads
system.cpu.int_regfile_writes 7658 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 14993 # number of misc regfile reads
+system.cpu.misc_regfile_reads 14992 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
-system.cpu.icache.tagsinuse 148.864335 # Cycle average of tags in use
-system.cpu.icache.total_refs 1560 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 148.855822 # Cycle average of tags in use
+system.cpu.icache.total_refs 1559 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.252525 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 148.864335 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.072688 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1560 # number of ReadReq hits
-system.cpu.icache.demand_hits 1560 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1560 # number of overall hits
+system.cpu.icache.occ_blocks::0 148.855822 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.072684 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 1559 # number of ReadReq hits
+system.cpu.icache.demand_hits 1559 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 1559 # number of overall hits
system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses
system.cpu.icache.demand_misses 360 # number of demand (read+write) misses
system.cpu.icache.overall_misses 360 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1920 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1920 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1920 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.187500 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.187500 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.187500 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses 1919 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 1919 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 1919 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.187598 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.187598 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.187598 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency
@@ -371,9 +371,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 9945000 #
system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.154688 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.154688 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.154688 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.154768 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.154768 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.154768 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
@@ -382,13 +382,13 @@ system.cpu.icache.mshr_cap_events 0 # nu
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 89.089443 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use
system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 89.089443 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.021750 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 89.085552 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.021749 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
@@ -458,12 +458,12 @@ system.cpu.dcache.mshr_cap_events 0 # nu
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 188.120549 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use
system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 188.120549 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 188.110462 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits
system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits