diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:05 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:05 -0600 |
| commit | 371110fb0a8b5c687682c8ce1e1445eee1d3a7bc (patch) | |
| tree | 9610ca973c18ed1270fba72f8040c8edf140d62d /tests/quick | |
| parent | 005892719047c3b4b383d9aeeeb481039518f661 (diff) | |
| download | gem5-371110fb0a8b5c687682c8ce1e1445eee1d3a7bc.tar.xz | |
Regressions: Update regressions for SIMD opclass changes
Diffstat (limited to 'tests/quick')
23 files changed, 1873 insertions, 179 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 39801baea..da67d287f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -136,8 +136,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -231,41 +231,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -358,7 +484,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 17cf75317..c56e2a305 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 22:53:27 -M5 executing on aus-bc2-b15 +M5 compiled Nov 15 2010 08:52:32 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 13:43:59 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index a57aece07..70e07c2b3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 44712 # Simulator instruction rate (inst/s) -host_mem_usage 204968 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 86758837 # Simulator tick rate (ticks/s) +host_inst_rate 34451 # Simulator instruction rate (inst/s) +host_mem_usage 203748 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 66857161 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -279,6 +279,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -296,6 +316,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 9f8bdfba9..2ddfc3365 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -136,8 +136,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -231,41 +231,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr index 67f69f09d..0659d557a 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,5 +1,7 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 621a02c83..62d772708 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:05 +M5 compiled Nov 15 2010 08:52:32 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 13:43:59 M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index a2f30aade..c55fb3eb0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 101462 # Simulator instruction rate (inst/s) -host_mem_usage 236800 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 307213198 # Simulator tick rate (ticks/s) +host_inst_rate 60581 # Simulator instruction rate (inst/s) +host_mem_usage 202656 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 184013511 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -279,6 +279,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.19% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.19% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.19% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.19% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 673 18.53% 89.73% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -296,6 +316,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.86% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index 3aa7b893f..a9c72ed3e 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -190,8 +190,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -285,41 +285,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 158312102..ac792f6c6 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 26 2010 21:00:10 -M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase -M5 started Sep 26 2010 21:29:28 -M5 executing on burrito -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing +M5 compiled Nov 14 2010 23:58:18 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 14 2010 23:58:34 +M5 executing on zizzer +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 5b27dd196..8e9b6a4ca 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 25375 # Simulator instruction rate (inst/s) -host_mem_usage 223596 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 62666353 # Simulator tick rate (ticks/s) +host_inst_rate 72923 # Simulator instruction rate (inst/s) +host_mem_usage 204488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 179666090 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -272,6 +272,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.81% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.81% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.81% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.81% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 1984 26.91% 85.72% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 1053 14.28% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -289,6 +309,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.93% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 83 58.45% 63.38% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.62% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index e69547764..3d11c96e4 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -137,8 +137,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -232,41 +232,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index d552956c6..1fe8a27f7 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 16785032. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 17040520. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index f838ffb8f..d3bc761bb 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simout -Redirecting stderr to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 12:59:22 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:59:25 +M5 compiled Nov 15 2010 00:01:15 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 00:01:17 M5 executing on zizzer -command line: build/POWER_SE/m5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing +command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 914654ad0..6f780bef0 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8561 # Simulator instruction rate (inst/s) -host_mem_usage 202624 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host -host_tick_rate 17311106 # Simulator tick rate (ticks/s) +host_inst_rate 15746 # Simulator instruction rate (inst/s) +host_mem_usage 202164 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host +host_tick_rate 31829526 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -272,6 +272,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -289,6 +309,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 808784ec1..eef6bf91e 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -136,8 +136,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -231,41 +231,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 8e80e0787..3dc1278fb 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:11:50 +M5 compiled Nov 15 2010 08:52:32 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 13:43:59 M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index f38e46afc..91de8ff11 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 53800 # Simulator instruction rate (inst/s) -host_mem_usage 205552 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 59488297 # Simulator tick rate (ticks/s) +host_inst_rate 115372 # Simulator instruction rate (inst/s) +host_mem_usage 204236 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 127463354 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -436,6 +436,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.11% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.37% 88.48% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 1143 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -451,6 +471,26 @@ system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.67% # Ty system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAddAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdShift 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::MemRead 2103 21.07% 88.75% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::MemWrite 1123 11.25% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -466,6 +506,26 @@ system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.39% # Ty system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAdd 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAddAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAlu 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdCmp 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdCvt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMisc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMult 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMultAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdShift 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdShiftAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdSqrt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatAdd 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatAlu 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatCmp 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatCvt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatDiv 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMisc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMult 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMultAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatSqrt 0 0.00% 67.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type::MemRead 4224 21.22% 88.61% # Type of FU issued system.cpu.iq.ISSUE:FU_type::MemWrite 2266 11.39% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -487,6 +547,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.70% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 89 53.94% 63.64% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 60 36.36% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index f82b3de59..285549a9c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -136,8 +136,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -231,41 +231,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 98265dc36..70b3ce838 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 26 2010 21:00:10 -M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase -M5 started Sep 26 2010 21:00:21 -M5 executing on burrito -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing +M5 compiled Nov 15 2010 00:04:22 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 00:04:25 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index f3e784d13..7a8fad380 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 29064 # Simulator instruction rate (inst/s) -host_mem_usage 225548 # Number of bytes of host memory used -host_seconds 0.50 # Real time elapsed on the host -host_tick_rate 37472433 # Simulator tick rate (ticks/s) +host_inst_rate 33758 # Simulator instruction rate (inst/s) +host_mem_usage 203840 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host +host_tick_rate 43520237 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated @@ -262,6 +262,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 74.52% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 74.52% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 74.52% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 74.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 74.52% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 2869 16.04% 90.56% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 1689 9.44% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -279,6 +299,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 29.55% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 29.55% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 29.55% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 29.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 29.55% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 21 23.86% 53.41% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 41 46.59% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index c3c2d2e0e..17847f641 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -136,8 +136,8 @@ size=64 [system.cpu0.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 [system.cpu0.fuPool.FUList0] type=FUDesc @@ -231,41 +231,167 @@ opLat=1 [system.cpu0.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 + +[system.cpu0.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu0.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu0.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu0.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu0.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu0.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu0.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu0.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu0.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu0.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu0.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu0.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu0.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu0.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu0.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu0.fuPool.FUList5.opList +opList=system.cpu0.fuPool.FUList6.opList -[system.cpu0.fuPool.FUList5.opList] +[system.cpu0.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu0.fuPool.FUList6] +[system.cpu0.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 +opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 -[system.cpu0.fuPool.FUList6.opList0] +[system.cpu0.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu0.fuPool.FUList6.opList1] +[system.cpu0.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu0.fuPool.FUList7] +[system.cpu0.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu0.fuPool.FUList7.opList +opList=system.cpu0.fuPool.FUList8.opList -[system.cpu0.fuPool.FUList7.opList] +[system.cpu0.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -455,8 +581,8 @@ size=64 [system.cpu1.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 [system.cpu1.fuPool.FUList0] type=FUDesc @@ -550,41 +676,167 @@ opLat=1 [system.cpu1.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 + +[system.cpu1.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu1.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu1.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu1.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu1.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu1.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu1.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu1.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu1.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu1.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu1.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu1.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu1.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu1.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu1.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu1.fuPool.FUList5.opList +opList=system.cpu1.fuPool.FUList6.opList -[system.cpu1.fuPool.FUList5.opList] +[system.cpu1.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu1.fuPool.FUList6] +[system.cpu1.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 +opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 -[system.cpu1.fuPool.FUList6.opList0] +[system.cpu1.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu1.fuPool.FUList6.opList1] +[system.cpu1.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu1.fuPool.FUList7] +[system.cpu1.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu1.fuPool.FUList7.opList +opList=system.cpu1.fuPool.FUList8.opList -[system.cpu1.fuPool.FUList7.opList] +[system.cpu1.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -755,8 +1007,8 @@ size=64 [system.cpu2.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 [system.cpu2.fuPool.FUList0] type=FUDesc @@ -850,41 +1102,167 @@ opLat=1 [system.cpu2.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 + +[system.cpu2.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu2.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu2.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu2.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu2.fuPool.FUList5.opList +opList=system.cpu2.fuPool.FUList6.opList -[system.cpu2.fuPool.FUList5.opList] +[system.cpu2.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu2.fuPool.FUList6] +[system.cpu2.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1 +opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 -[system.cpu2.fuPool.FUList6.opList0] +[system.cpu2.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu2.fuPool.FUList6.opList1] +[system.cpu2.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu2.fuPool.FUList7] +[system.cpu2.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu2.fuPool.FUList7.opList +opList=system.cpu2.fuPool.FUList8.opList -[system.cpu2.fuPool.FUList7.opList] +[system.cpu2.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -1055,8 +1433,8 @@ size=64 [system.cpu3.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 [system.cpu3.fuPool.FUList0] type=FUDesc @@ -1150,41 +1528,167 @@ opLat=1 [system.cpu3.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 + +[system.cpu3.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu3.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu3.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu3.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu3.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu3.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu3.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu3.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu3.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu3.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu3.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu3.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu3.fuPool.FUList5.opList +opList=system.cpu3.fuPool.FUList6.opList -[system.cpu3.fuPool.FUList5.opList] +[system.cpu3.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu3.fuPool.FUList6] +[system.cpu3.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1 +opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 -[system.cpu3.fuPool.FUList6.opList0] +[system.cpu3.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu3.fuPool.FUList6.opList1] +[system.cpu3.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu3.fuPool.FUList7] +[system.cpu3.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu3.fuPool.FUList7.opList +opList=system.cpu3.fuPool.FUList8.opList -[system.cpu3.fuPool.FUList7.opList] +[system.cpu3.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 890ebb6d8..3330dd3da 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 26 2010 21:00:10 -M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase -M5 started Sep 26 2010 21:00:16 -M5 executing on burrito -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +M5 compiled Nov 15 2010 00:04:22 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 00:06:46 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 8e653945f..eea552a2f 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 45662 # Simulator instruction rate (inst/s) -host_mem_usage 235748 # Number of bytes of host memory used -host_seconds 25.27 # Real time elapsed on the host -host_tick_rate 4652764 # Simulator tick rate (ticks/s) +host_inst_rate 225525 # Simulator instruction rate (inst/s) +host_mem_usage 214280 # Number of bytes of host memory used +host_seconds 5.12 # Real time elapsed on the host +host_tick_rate 22978978 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1153797 # Number of instructions simulated sim_seconds 0.000118 # Number of seconds simulated @@ -272,6 +272,26 @@ system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 41.97% # Ty system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 41.97% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 41.97% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 41.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 41.97% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::MemRead 175866 38.63% 80.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88274 19.39% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -289,6 +309,26 @@ system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 15.76% # at system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 15.76% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 15.76% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 15.76% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 15.76% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::MemRead 75 40.76% 56.52% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::MemWrite 80 43.48% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available @@ -605,6 +645,26 @@ system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.51% # Ty system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::MemRead 95884 36.40% 83.91% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42396 16.09% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -622,6 +682,26 @@ system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.18% # at system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.18% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.18% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.18% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.18% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.50% 33.68% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::MemWrite 128 66.32% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available @@ -937,6 +1017,26 @@ system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.50% # Ty system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.50% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.50% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.50% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.50% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::MemRead 83455 36.32% 84.81% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34899 15.19% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -954,6 +1054,26 @@ system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.88% # at system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.67% 31.55% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::MemWrite 128 68.45% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available @@ -1268,6 +1388,26 @@ system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.00% # Ty system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::MemRead 89212 36.40% 84.40% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::MemWrite 38247 15.60% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -1285,6 +1425,26 @@ system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.21% # at system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.21% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.21% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.21% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.21% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::MemRead 54 28.12% 33.33% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::MemWrite 128 66.67% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |