diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/quick | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/quick')
23 files changed, 6819 insertions, 6819 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 88df9e22a..23658f386 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,222 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920895 # Number of seconds simulated -sim_ticks 1920895294000 # Number of ticks simulated -final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.914421 # Number of seconds simulated +sim_ticks 1914420945000 # Number of ticks simulated +final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1271848 # Simulator instruction rate (inst/s) -host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43474553061 # Simulator tick rate (ticks/s) -host_mem_usage 295012 # Number of bytes of host memory used -host_seconds 44.18 # Real time elapsed on the host -sim_insts 56195754 # Number of instructions simulated -sim_ops 56195754 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 336257 # number of replacements -system.cpu.l2cache.tagsinuse 65308.063316 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2448454 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401419 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.099497 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.996522 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814985 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1731448 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835257 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835257 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187565 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002550 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1919013 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916463 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002550 # number of overall hits -system.cpu.l2cache.overall_hits::total 1919013 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116861 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388827 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402116 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388827 # number of overall misses -system.cpu.l2cache.overall_misses::total 402116 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20916229000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2321129 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2321129 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173242 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52015.410976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52015.410976 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks -system.cpu.l2cache.writebacks::total 74180 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402116 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +host_inst_rate 1284205 # Simulator instruction rate (inst/s) +host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43773036105 # Simulator tick rate (ticks/s) +host_mem_usage 295308 # Number of bytes of host memory used +host_seconds 43.74 # Real time elapsed on the host +sim_insts 56164879 # Number of instructions simulated +sim_ops 56164879 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory +system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.347775 # Cycle average of tags in use +system.iocache.tagsinuse 1.347664 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1748614160000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.347664 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084229 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084229 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +57,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11444054806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11444054806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11464727804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11464727804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11464727804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11464727804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +81,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +107,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +123,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +146,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066995 # DTB read hits +system.cpu.dtb.read_hits 9062432 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357563 # DTB write hits +system.cpu.dtb.write_hits 6354530 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15424558 # DTB hits +system.cpu.dtb.data_hits 15416962 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975749 # ITB hits +system.cpu.itb.fetch_hits 4974475 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980755 # ITB accesses +system.cpu.itb.fetch_accesses 4979481 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +174,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3841790588 # number of cpu cycles simulated +system.cpu.numCycles 3828841890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195754 # Number of instructions committed -system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses +system.cpu.committedInsts 56164879 # Number of instructions committed +system.cpu.committedOps 56164879 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52037464 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483816 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066962 # number of integer instructions +system.cpu.num_func_calls 1482804 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6466141 # number of instructions that are conditional controls +system.cpu.num_int_insts 52037464 # number of integer instructions system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written +system.cpu.num_int_register_reads 71294843 # number of times the integer registers were read +system.cpu.num_int_register_writes 38508157 # number of times the integer registers were written system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15477180 # number of memory refs -system.cpu.num_load_insts 9103852 # Number of load instructions -system.cpu.num_store_insts 6373328 # Number of store instructions -system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles -system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles -system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933642 # Percentage of idle cycles +system.cpu.num_mem_refs 15469580 # number of memory refs +system.cpu.num_load_insts 9099291 # Number of load instructions +system.cpu.num_store_insts 6370289 # Number of store instructions +system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles +system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles +system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.937415 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814135 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -427,29 +257,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175957 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193009 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.callpal::total 192901 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1864235249000 97.38% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -482,51 +312,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 929101 # number of replacements -system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use -system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits -system.cpu.icache.overall_hits::total 55277821 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses -system.cpu.icache.overall_misses::total 929772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56207593 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23683.271185 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23683.271185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29128.935239 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29128.935239 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13158.031838 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13158.031838 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24889.817487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24889.817487 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,54 +471,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835257 # number of writebacks -system.cpu.dcache.writebacks::total 835257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069678 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069678 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304443 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304443 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52017.062113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52017.062113 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 74188 # number of writebacks +system.cpu.l2cache.writebacks::total 74188 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271970 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116859 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116859 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388829 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402119 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388829 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402119 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531884000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892328500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4a0324f9e..07e356a30 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629150 # Number of seconds simulated -sim_ticks 2629149747000 # Number of ticks simulated -final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.624688 # Number of seconds simulated +sim_ticks 2624688029000 # Number of ticks simulated +final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 556259 # Simulator instruction rate (inst/s) -host_op_rate 707830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24290841486 # Simulator tick rate (ticks/s) -host_mem_usage 380276 # Number of bytes of host memory used -host_seconds 108.24 # Real time elapsed on the host -sim_insts 60207390 # Number of instructions simulated -sim_ops 76612873 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory -system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 388710 # Simulator instruction rate (inst/s) +host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16947208284 # Simulator tick rate (ticks/s) +host_mem_usage 385844 # Number of bytes of host memory used +host_seconds 154.87 # Real time elapsed on the host +sim_insts 60201138 # Number of instructions simulated +sim_ops 76605123 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,244 +23,44 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 62933 # number of replacements -system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.791359 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226888 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 596416 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 596416 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113846 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484154 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8836 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844195 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484154 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340734 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10261 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20880 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2845 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10613 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144085 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154704 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10613 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144085 # number of overall misses -system.cpu.l2cache.overall_misses::total 154704 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8049111500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1495438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1495438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103451 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103451 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58379 # number of writebacks -system.cpu.l2cache.writebacks::total 58379 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154704 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory +system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -307,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14998169 # DTB read hits -system.cpu.dtb.read_misses 7372 # DTB read misses -system.cpu.dtb.write_hits 11231565 # DTB write hits -system.cpu.dtb.write_misses 2270 # DTB write misses +system.cpu.dtb.read_hits 14996726 # DTB read hits +system.cpu.dtb.read_misses 7357 # DTB read misses +system.cpu.dtb.write_hits 11231612 # DTB write hits +system.cpu.dtb.write_misses 2211 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15005541 # DTB read accesses -system.cpu.dtb.write_accesses 11233835 # DTB write accesses +system.cpu.dtb.read_accesses 15004083 # DTB read accesses +system.cpu.dtb.write_accesses 11233823 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26229734 # DTB hits -system.cpu.dtb.misses 9642 # DTB misses -system.cpu.dtb.accesses 26239376 # DTB accesses -system.cpu.itb.inst_hits 61501359 # ITB inst hits +system.cpu.dtb.hits 26228338 # DTB hits +system.cpu.dtb.misses 9568 # DTB misses +system.cpu.dtb.accesses 26237906 # DTB accesses +system.cpu.itb.inst_hits 61495107 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +105,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61505830 # ITB inst accesses -system.cpu.itb.hits 61501359 # DTB hits +system.cpu.itb.inst_accesses 61499578 # ITB inst accesses +system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61505830 # DTB accesses -system.cpu.numCycles 5258299494 # number of cpu cycles simulated +system.cpu.itb.accesses 61499578 # DTB accesses +system.cpu.numCycles 5249376058 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60207390 # Number of instructions committed -system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses +system.cpu.committedInsts 60201138 # Number of instructions committed +system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140176 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948958 # number of instructions that are conditional controls -system.cpu.num_int_insts 68878830 # number of integer instructions +system.cpu.num_func_calls 2139913 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read -system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written +system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27397151 # number of memory refs -system.cpu.num_load_insts 15662227 # Number of load instructions -system.cpu.num_store_insts 11734924 # Number of store instructions -system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles -system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles -system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.868680 # Percentage of idle cycles +system.cpu.num_mem_refs 27395681 # number of memory refs +system.cpu.num_load_insts 15660705 # Number of load instructions +system.cpu.num_store_insts 11734976 # Number of store instructions +system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles +system.cpu.num_busy_cycles 675707863.387743 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,112 +186,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856442 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,54 +300,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks -system.cpu.dcache.writebacks::total 596416 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 369069 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250541 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250541 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619610 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619610 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619610 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619610 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4633803000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4633803000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509109000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509109000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136482000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136482000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13142912000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13142912000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13142912000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13142912000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41013343500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41013343500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027206 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027206 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026045 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks +system.cpu.dcache.writebacks::total 595968 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619213 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -593,6 +355,244 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 61913 # number of replacements +system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 944044d4e..358803d5d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,264 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196023 # Number of seconds simulated -sim_ticks 5196022575000 # Number of ticks simulated -final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.187896 # Number of seconds simulated +sim_ticks 5187896410000 # Number of ticks simulated +final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1315892 # Simulator instruction rate (inst/s) -host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53344387183 # Simulator tick rate (ticks/s) -host_mem_usage 354072 # Number of bytes of host memory used -host_seconds 97.41 # Real time elapsed on the host -sim_insts 128174734 # Number of instructions simulated -sim_ops 247089109 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory +host_inst_rate 834857 # Simulator instruction rate (inst/s) +host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33766110220 # Simulator tick rate (ticks/s) +host_mem_usage 354356 # Number of bytes of host memory used +host_seconds 153.64 # Real time elapsed on the host +sim_insts 128269216 # Number of instructions simulated +sim_ops 247270559 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory -system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory -system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory +system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 826944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8107200 # Number of bytes written to this memory +system.physmem.bytes_written::total 8107200 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44802 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140567 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126675 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126675 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 552696 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1734092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2446248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1562714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1562714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1562714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 552696 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 86330 # number of replacements -system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543462 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200678 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 778172 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481001 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2268886 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6719 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2994 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 778172 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481001 # number of overall hits -system.cpu.l2cache.overall_hits::total 2268886 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41237 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1338 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 112514 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140867 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153751 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12879 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140867 # number of overall misses -system.cpu.l2cache.overall_misses::total 153751 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8011639500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422637 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063464 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52107.885477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52107.885477 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 79675 # number of writebacks -system.cpu.l2cache.writebacks::total 79675 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153751 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.bw_total::cpu.inst 159399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1734092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4008962 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 47503 # number of replacements -system.iocache.tagsinuse 0.108744 # Cycle average of tags in use +system.iocache.tagsinuse 0.106662 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy +system.iocache.warmup_cycle 5044925516000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.106662 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006666 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006666 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses system.iocache.ReadReq_misses::total 838 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -267,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129993932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10714208160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10714208160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10844202092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10844202092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10844202092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10844202092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -291,19 +83,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155124.023866 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -317,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +146,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10392045150 # number of cpu cycles simulated +system.cpu.numCycles 10375792820 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128174734 # Number of instructions committed -system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses +system.cpu.committedInsts 128269216 # Number of instructions committed +system.cpu.committedOps 247270559 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232005526 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls -system.cpu.num_int_insts 231827885 # number of integer instructions +system.cpu.num_conditional_control_insts 23152914 # number of instructions that are conditional controls +system.cpu.num_int_insts 232005526 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read -system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written +system.cpu.num_int_register_reads 567048885 # number of times the integer registers were read +system.cpu.num_int_register_writes 293217624 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22210252 # number of memory refs -system.cpu.num_load_insts 13855140 # Number of load instructions -system.cpu.num_store_insts 8355112 # Number of store instructions -system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles -system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940780 # Percentage of idle cycles +system.cpu.num_mem_refs 22238817 # number of memory refs +system.cpu.num_load_insts 13875768 # Number of load instructions +system.cpu.num_store_insts 8363049 # Number of store instructions +system.cpu.num_idle_cycles 9774979498.742117 # Number of idle cycles +system.cpu.num_busy_cycles 600813321.257884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057905 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942095 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790545 # number of replacements -system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use -system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits -system.cpu.icache.overall_hits::total 144363546 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses -system.cpu.icache.overall_misses::total 791064 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency +system.cpu.icache.replacements 793131 # number of replacements +system.cpu.icache.tagsinuse 510.350730 # Cycle average of tags in use +system.cpu.icache.total_refs 144484487 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 793643 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.052241 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 160314386000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.350730 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996779 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996779 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144484487 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144484487 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144484487 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144484487 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144484487 # number of overall hits +system.cpu.icache.overall_hits::total 144484487 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 793650 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 793650 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 793650 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 793650 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 793650 # number of overall misses +system.cpu.icache.overall_misses::total 793650 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10860662000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10860662000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10860662000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10860662000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10860662000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10860662000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145278137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145278137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145278137 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145278137 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145278137 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145278137 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13684.447804 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13684.447804 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13684.447804 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13684.447804 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,80 +223,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793650 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 793650 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 793650 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793650 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793650 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793650 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9273362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9273362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9273362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9273362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9273362000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9273362000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005463 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005463 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005463 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.447804 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.447804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3550 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3599 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.063919 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7874 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3610 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.181163 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5162043257000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.063919 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191495 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191495 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7876 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7876 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7878 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7878 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7878 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7878 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43455000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43455000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43455000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43455000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43455000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43455000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12331 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12331 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361285 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361285 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361226 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.361226 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361226 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.361226 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9754.208754 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9754.208754 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9754.208754 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,78 +305,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4455 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4455 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4455 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4455 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4455 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4455 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34545000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34545000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34545000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34545000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34545000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34545000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361285 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361285 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361226 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361226 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7754.208754 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7810 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7423 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.046109 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13594 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7438 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.827642 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5159593477000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.046109 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315382 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315382 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13598 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13598 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13598 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13598 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13598 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13598 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8635 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8635 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8635 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8635 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8635 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8635 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91582000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91582000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91582000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 91582000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91582000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 91582000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22233 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22233 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22233 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22233 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22233 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22233 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.388387 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.388387 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.388387 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.388387 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.388387 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.388387 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10605.906196 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10605.906196 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10605.906196 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,90 +385,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2904 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2904 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8635 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8635 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8635 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8635 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8635 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8635 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74312000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74312000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74312000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74312000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74312000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74312000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.388387 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.388387 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.388387 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8605.906196 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622132 # number of replacements -system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use -system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1618325 # number of replacements +system.cpu.dcache.tagsinuse 511.997377 # Cycle average of tags in use +system.cpu.dcache.total_refs 20032981 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1618837 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.374922 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 43788000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997377 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits -system.cpu.dcache.overall_hits::total 20001854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses -system.cpu.dcache.overall_misses::total 1624858 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11992560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11992560 # 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average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,46 +477,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks -system.cpu.dcache.writebacks::total 1539490 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315369 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001770 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016282 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087447 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063788 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001770 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016282 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087447 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52046.819378 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52519.441887 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52371.019070 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24987.360595 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24987.360595 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52024.373124 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52024.373124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52046.819378 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52123.171352 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52116.778371 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52046.819378 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52123.171352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52116.778371 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 80008 # number of writebacks +system.cpu.l2cache.writebacks::total 80008 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12922 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28238 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41165 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1345 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1345 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113260 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113260 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141498 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305699000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021630 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811218 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811218 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362308 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362308 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9447623bf..ba49bebdd 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21979500 # Number of ticks simulated -final_tick 21979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21628500 # Number of ticks simulated +final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39186 # Simulator instruction rate (inst/s) -host_op_rate 39182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134757534 # Simulator tick rate (ticks/s) -host_mem_usage 222636 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 48865 # Simulator instruction rate (inst/s) +host_op_rate 48859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165354272 # Simulator tick rate (ticks/s) +host_mem_usage 218640 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 876453059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 489183102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1365636161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 876453059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 876453059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 876453059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 489183102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1365636161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43960 # number of cpu cycles simulated +system.cpu.numCycles 43258 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1606 # Number of BP lookups @@ -90,12 +90,12 @@ system.cpu.execution_unit.executions 4463 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 12066 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 536 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36556 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7404 # Number of cycles cpu stages are processed. -system.cpu.activity 16.842584 # Percentage of cycles cpu is active +system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7403 # Number of cycles cpu stages are processed. +system.cpu.activity 17.113597 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -107,34 +107,34 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.879499 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.879499 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145359 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.145359 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 39048 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.173794 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40082 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.821656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39789 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.488171 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 42620 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.048226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 39501 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4459 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.143312 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.677707 # Cycle average of tags in use +system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use system.cpu.icache.total_refs 557 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.677707 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits @@ -149,12 +149,12 @@ system.cpu.icache.demand_misses::cpu.inst 351 # n system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses system.cpu.icache.overall_misses::total 351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19781500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19781500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19781500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19781500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19781500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19781500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses @@ -167,12 +167,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56357.549858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56357.549858 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -193,34 +193,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16493500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16493500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.489186 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.489186 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025022 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025022 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits @@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses system.cpu.dcache.overall_misses::total 348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5918000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5918000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15290000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15290000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21208000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21208000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21208000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21208000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -261,20 +261,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60942.528736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60942.528736 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1689000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits @@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5509500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9606000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9606000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9606000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9606000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,23 +309,23 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 194.900917 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.748296 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.152621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16152000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21542000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16152000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9397500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25549500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16152000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9397500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25549500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12487000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4239000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16726000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3129500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3129500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12487000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7368500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19855500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12487000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7368500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19855500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1a124af36..1c9a49b18 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12735500 # Number of ticks simulated -final_tick 12735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12394500 # Number of ticks simulated +final_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33074 # Simulator instruction rate (inst/s) -host_op_rate 33071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66088952 # Simulator tick rate (ticks/s) -host_mem_usage 223664 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 52290 # Simulator instruction rate (inst/s) +host_op_rate 52282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101684511 # Simulator tick rate (ticks/s) +host_mem_usage 219660 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory system.physmem.bytes_read::total 31296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory system.physmem.num_reads::total 489 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1572926073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 884456833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2457382906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1572926073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1572926073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1572926073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 884456833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2457382906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1978 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 1990 # DTB read hits +system.cpu.dtb.read_misses 56 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2033 # DTB read accesses -system.cpu.dtb.write_hits 1077 # DTB write hits -system.cpu.dtb.write_misses 31 # DTB write misses +system.cpu.dtb.read_accesses 2046 # DTB read accesses +system.cpu.dtb.write_hits 1084 # DTB write hits +system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1108 # DTB write accesses -system.cpu.dtb.data_hits 3055 # DTB hits +system.cpu.dtb.write_accesses 1114 # DTB write accesses +system.cpu.dtb.data_hits 3074 # DTB hits system.cpu.dtb.data_misses 86 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3141 # DTB accesses -system.cpu.itb.fetch_hits 2292 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 3160 # DTB accesses +system.cpu.itb.fetch_hits 2336 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2332 # ITB accesses +system.cpu.itb.fetch_accesses 2374 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +60,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 25472 # number of cpu cycles simulated +system.cpu.numCycles 24790 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2810 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1639 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 544 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 764 # Number of BTB hits +system.cpu.BPredUnit.lookups 2873 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 76 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8490 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16101 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1164 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2877 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1816 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 977 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2292 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14359 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.121318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.516372 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16442 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2336 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11482 79.96% 79.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 290 2.02% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 231 1.61% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 230 1.60% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 264 1.84% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 193 1.34% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 266 1.85% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 182 1.27% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 8.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14359 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.110317 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632106 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1012 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2694 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1150 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2739 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14902 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1150 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9643 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 342 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 379 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2542 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 303 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14192 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2589 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 256 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10635 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17782 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17765 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6065 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 736 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2623 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1340 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. +system.cpu.rename.skidInsts 728 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12668 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10483 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5989 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3489 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10578 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14359 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.730065 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.362537 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9920 69.09% 69.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1630 11.35% 80.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1188 8.27% 88.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 708 4.93% 93.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 458 3.19% 96.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 268 1.87% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 142 0.99% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 31 0.22% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14359 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 7.21% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 64 57.66% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7098 67.71% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2226 21.23% 88.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 11.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10483 # Type of FU issued -system.cpu.iq.rate 0.411550 # Inst issue rate -system.cpu.iq.fu_busy_cnt 111 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010589 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18693 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9514 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10578 # Type of FU issued +system.cpu.iq.rate 0.426704 # Inst issue rate +system.cpu.iq.fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10581 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1440 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 475 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1150 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2623 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1340 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 149 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 397 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 546 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9926 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2044 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 557 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3155 # number of memory reference insts executed -system.cpu.iew.exec_branches 1608 # Number of branches executed -system.cpu.iew.exec_stores 1111 # Number of stores executed -system.cpu.iew.exec_rate 0.389683 # Inst execution rate -system.cpu.iew.wb_sent 9680 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5005 # num instructions producing a value -system.cpu.iew.wb_consumers 6736 # num instructions consuming a value +system.cpu.iew.exec_refs 3174 # number of memory reference insts executed +system.cpu.iew.exec_branches 1621 # Number of branches executed +system.cpu.iew.exec_stores 1117 # Number of stores executed +system.cpu.iew.exec_rate 0.403066 # Inst execution rate +system.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9591 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5054 # num instructions producing a value +system.cpu.iew.wb_consumers 6863 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.373901 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.743023 # average fanout of values written-back +system.cpu.iew.wb_rate 0.386890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6396 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 461 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.483685 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.282622 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10366 78.48% 78.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1544 11.69% 90.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 533 4.04% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 227 1.72% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.24% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.80% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 105 0.79% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 30 0.23% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 134 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,70 +308,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 134 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25509 # The number of ROB reads -system.cpu.rob.rob_writes 26731 # The number of ROB writes -system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25250 # The number of ROB reads +system.cpu.rob.rob_writes 27045 # The number of ROB writes +system.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 3.997489 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.997489 # CPI: Total CPI of All Threads -system.cpu.ipc 0.250157 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.250157 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12615 # number of integer regfile reads -system.cpu.int_regfile_writes 7161 # number of integer regfile writes +system.cpu.cpi 3.890458 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads +system.cpu.ipc 0.257039 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12699 # number of integer regfile reads +system.cpu.int_regfile_writes 7211 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 158.802415 # Cycle average of tags in use -system.cpu.icache.total_refs 1839 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.856688 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use +system.cpu.icache.total_refs 1881 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 158.802415 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077540 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1839 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1839 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1839 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1839 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1839 # number of overall hits -system.cpu.icache.overall_hits::total 1839 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses -system.cpu.icache.overall_misses::total 453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16260000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16260000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16260000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16260000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16260000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16260000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2292 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2292 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2292 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2292 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197644 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.197644 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197644 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.197644 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197644 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.197644 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35894.039735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35894.039735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35894.039735 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35894.039735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35894.039735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35894.039735 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 158.537993 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077411 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077411 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1881 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1881 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1881 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1881 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1881 # number of overall hits +system.cpu.icache.overall_hits::total 1881 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses +system.cpu.icache.overall_misses::total 455 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15830500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15830500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15830500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15830500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15830500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15830500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2336 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2336 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2336 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2336 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194777 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.194777 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.194777 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.194777 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.194777 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.194777 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34792.307692 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34792.307692 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34792.307692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34792.307692 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,94 +380,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 139 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 139 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 139 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 139 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11585500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11585500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11585500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11585500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11585500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11585500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136998 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136998 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136998 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136998 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136998 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36896.496815 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36896.496815 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36896.496815 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36896.496815 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36896.496815 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36896.496815 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 142 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11526000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11526000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11526000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133990 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.133990 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.133990 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36824.281150 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36824.281150 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36824.281150 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36824.281150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36824.281150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36824.281150 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.882695 # Cycle average of tags in use -system.cpu.dcache.total_refs 2246 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.761364 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.969871 # Cycle average of tags in use +system.cpu.dcache.total_refs 2254 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 177 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.734463 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.882695 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026339 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026339 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1740 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1740 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 107.969871 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026360 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026360 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1748 # 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number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2770 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086614 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086614 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2781 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2781 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2781 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2781 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087683 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087683 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.189170 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.189170 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.189170 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.189170 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39763.636364 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39763.636364 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41916.434540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41916.434540 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41238.549618 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41238.549618 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41238.549618 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41238.549618 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.189500 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.189500 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.189500 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.189500 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37886.904762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37886.904762 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35924.791086 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35924.791086 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36550.284630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36550.284630 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,119 +476,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7186000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7186000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7186000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054068 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054068 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 177 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 177 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4341000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4341000 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35927.884615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37310.838446 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,50 +597,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 177 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 177 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10253500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14112500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2567500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2567500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6426500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10253500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6426500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16680000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10213000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14118000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2577000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2577000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10213000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6482000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10213000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6482000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16695000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32758.785942 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37466.019417 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33924.278846 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32758.785942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36514.204545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34110.429448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32758.785942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36514.204545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34110.429448 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.974359 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33937.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35301.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35301.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 6a791ec60..aa2f4f81d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 34409000 # Number of ticks simulated -final_tick 34409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 32544000 # Number of ticks simulated +final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55813 # Simulator instruction rate (inst/s) -host_op_rate 55804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 300451871 # Simulator tick rate (ticks/s) -host_mem_usage 222640 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 68117 # Simulator instruction rate (inst/s) +host_op_rate 68101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 346770993 # Simulator tick rate (ticks/s) +host_mem_usage 218620 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 517074021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312476387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 829550408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517074021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517074021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517074021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312476387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 829550408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 68818 # number of cpu cycles simulated +system.cpu.numCycles 65088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 68818 # Number of busy cycles +system.cpu.num_busy_cycles 65088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 128.208060 # Cycle average of tags in use +system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 128.208060 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062602 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062602 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.892123 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.892123 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025364 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025364 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.769601 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 128.220906 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.548695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003913 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001726 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005639 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d53f6132a..7f4e477cc 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7252000 # Number of ticks simulated -final_tick 7252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7079000 # Number of ticks simulated +final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57662 # Simulator instruction rate (inst/s) -host_op_rate 57638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175044086 # Simulator tick rate (ticks/s) -host_mem_usage 217908 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 8209 # Simulator instruction rate (inst/s) +host_op_rate 8209 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24342914 # Simulator tick rate (ticks/s) +host_mem_usage 218360 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1659128516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 750137893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2409266409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1659128516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1659128516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1659128516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 750137893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2409266409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 13 # DTB read misses +system.cpu.dtb.read_misses 34 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 725 # DTB read accesses -system.cpu.dtb.write_hits 368 # DTB write hits -system.cpu.dtb.write_misses 15 # DTB write misses +system.cpu.dtb.read_accesses 746 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 383 # DTB write accesses -system.cpu.dtb.data_hits 1080 # DTB hits -system.cpu.dtb.data_misses 28 # DTB misses +system.cpu.dtb.write_accesses 387 # DTB write accesses +system.cpu.dtb.data_hits 1079 # DTB hits +system.cpu.dtb.data_misses 54 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1108 # DTB accesses -system.cpu.itb.fetch_hits 1014 # ITB hits +system.cpu.dtb.data_accesses 1133 # DTB accesses +system.cpu.itb.fetch_hits 1015 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1044 # ITB accesses +system.cpu.itb.fetch_accesses 1045 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,183 +60,183 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14505 # number of cpu cycles simulated +system.cpu.numCycles 14159 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 1131 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 573 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 253 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 782 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 218 # Number of BTB hits +system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 211 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6900 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 429 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1183 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 857 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264 # Number of cycles fetch has spent blocked +system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 948 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1014 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 172 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.939926 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.361375 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6158 83.89% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 50 0.68% 84.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.76% 86.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 101 1.38% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 139 1.89% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 62 0.84% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 66 0.90% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 61 0.83% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 575 7.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077973 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.475698 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5395 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 291 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1141 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 501 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6151 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 501 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5491 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 174 # count of cycles rename stalled for serializing inst +system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1058 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5908 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4280 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6676 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6664 # Number of integer rename lookups +system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2512 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 145 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5051 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued +system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7341 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.548427 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.241979 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5680 77.37% 77.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 617 8.40% 85.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 387 5.27% 91.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 273 3.72% 94.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 198 2.70% 97.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 114 1.55% 99.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56 0.76% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.14% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 6 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.88% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 41.46% 46.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 53.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2876 71.44% 71.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 761 18.90% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 388 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4026 # Type of FU issued -system.cpu.iq.rate 0.277559 # Inst issue rate -system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010184 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15500 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7558 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4054 # Type of FU issued +system.cpu.iq.rate 0.286320 # Inst issue rate +system.cpu.iq.fu_busy_cnt 43 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4060 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed @@ -247,57 +247,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 501 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5407 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 150 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3874 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 152 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 350 # number of nop insts executed -system.cpu.iew.exec_refs 1109 # number of memory reference insts executed -system.cpu.iew.exec_branches 649 # Number of branches executed -system.cpu.iew.exec_stores 383 # Number of stores executed -system.cpu.iew.exec_rate 0.267080 # Inst execution rate -system.cpu.iew.wb_sent 3756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3694 # cumulative count of insts written-back +system.cpu.iew.exec_nop 342 # number of nop insts executed +system.cpu.iew.exec_refs 1134 # number of memory reference insts executed +system.cpu.iew.exec_branches 652 # Number of branches executed +system.cpu.iew.exec_stores 387 # Number of stores executed +system.cpu.iew.exec_rate 0.275019 # Inst execution rate +system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3708 # cumulative count of insts written-back system.cpu.iew.wb_producers 1740 # num instructions producing a value -system.cpu.iew.wb_consumers 2202 # num instructions consuming a value +system.cpu.iew.wb_consumers 2258 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.254671 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790191 # average fanout of values written-back +system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2822 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.225423 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5956 87.08% 87.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 217 3.17% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 4.65% 94.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.68% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 0.98% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 47 0.69% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.47% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 21 0.31% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,69 +308,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11924 # The number of ROB reads -system.cpu.rob.rob_writes 11305 # The number of ROB writes -system.cpu.timesIdled 172 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7164 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11671 # The number of ROB reads +system.cpu.rob.rob_writes 11260 # The number of ROB writes +system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.076665 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.076665 # CPI: Total CPI of All Threads -system.cpu.ipc 0.164564 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.164564 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4677 # number of integer regfile reads -system.cpu.int_regfile_writes 2861 # number of integer regfile writes +system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads +system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4712 # number of integer regfile reads +system.cpu.int_regfile_writes 2874 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 94.201337 # Cycle average of tags in use -system.cpu.icache.total_refs 769 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use +system.cpu.icache.total_refs 767 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.090426 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 94.201337 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045997 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045997 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 769 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 769 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 769 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 769 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 769 # number of overall hits -system.cpu.icache.overall_hits::total 769 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 245 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 245 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 245 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 245 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 245 # number of overall misses -system.cpu.icache.overall_misses::total 245 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 9112500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 9112500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 9112500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 9112500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 9112500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 9112500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1014 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1014 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241617 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.241617 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.241617 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.241617 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.241617 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.241617 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37193.877551 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37193.877551 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37193.877551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37193.877551 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits +system.cpu.icache.overall_hits::total 767 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses +system.cpu.icache.overall_misses::total 248 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,94 +379,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185404 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.185404 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.185404 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36875 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36875 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36875 # 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mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits -system.cpu.dcache.overall_hits::total 774 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 118 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3561500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3561500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7890000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7890000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7890000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7890000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses +system.cpu.dcache.overall_misses::total 202 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 973 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 973 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 973 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 973 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.204522 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.204522 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.204522 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.204522 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36682.203390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36682.203390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43969.135802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43969.135802 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39648.241206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39648.241206 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,14 +475,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -491,42 +491,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 981000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3492500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3492500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3492500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3492500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089838 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089838 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087359 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087359 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41172.131148 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41172.131148 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 123.109780 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 94.284624 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.825156 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002877 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000880 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6740500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2447000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9187500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 950000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6740500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6740500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3397000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10137500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -571,17 +571,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35853.723404 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40114.754098 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36897.590361 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39583.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37133.699634 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37133.699634 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,17 +601,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6136500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2258000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8394500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 876000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 876000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3134000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9270500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3134000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9270500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -623,17 +623,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.957447 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37016.393443 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33712.851406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index aabb78aae..83ebc2ad9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17541000 # Number of ticks simulated -final_tick 17541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16524000 # Number of ticks simulated +final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207586 # Simulator instruction rate (inst/s) -host_op_rate 207300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1409208031 # Simulator tick rate (ticks/s) -host_mem_usage 216876 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 93431 # Simulator instruction rate (inst/s) +host_op_rate 93371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 598358642 # Simulator tick rate (ticks/s) +host_mem_usage 217312 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 594720940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299184767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 893905707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 594720940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 594720940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 594720940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299184767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 893905707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 35082 # number of cpu cycles simulated +system.cpu.numCycles 33048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 35082 # Number of busy cycles +system.cpu.num_busy_cycles 33048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.027768 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.050296 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 80.027768 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.039076 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.039076 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.039087 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.439715 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 47.439715 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011582 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011582 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.121835 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 80.139278 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.982557 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003269 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 96198ee3a..cbe28c826 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10738000 # Number of ticks simulated -final_tick 10738000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 10412000 # Number of ticks simulated +final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28410 # Simulator instruction rate (inst/s) -host_op_rate 35442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66366492 # Simulator tick rate (ticks/s) -host_mem_usage 227572 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 32172 # Simulator instruction rate (inst/s) +host_op_rate 40134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72868464 # Simulator tick rate (ticks/s) +host_mem_usage 233868 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7936 # Number of bytes read from this memory -system.physmem.bytes_read::total 25728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1656919352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 739057553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2395976904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1656919352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 739057553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2395976904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -115,243 +115,243 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 21477 # number of cpu cycles simulated +system.cpu.numCycles 20825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2491 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1789 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1964 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.lookups 2492 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6988 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12142 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 958 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2639 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1622 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2325 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.169334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.586059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10418 79.79% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223 1.71% 81.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 193 1.48% 82.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 1.66% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.60% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.18% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 109 0.83% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 131 1.00% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115985 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.565349 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7128 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 89 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 945 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2432 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13276 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7383 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12436 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 239 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12439 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56552 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56280 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2229 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6758 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 47 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 766 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2732 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 47 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11190 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 47 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8841 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5157 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13057 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.677108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.355722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9364 71.72% 71.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1488 11.40% 83.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 792 6.07% 89.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 545 4.17% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 428 3.28% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 276 2.11% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 114 0.87% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 42 0.32% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13057 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.88% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 136 63.85% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 73 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5345 60.46% 60.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2263 25.60% 86.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1222 13.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8841 # Type of FU issued -system.cpu.iq.rate 0.411650 # Inst issue rate -system.cpu.iq.fu_busy_cnt 213 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024092 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31043 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16402 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7990 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8838 # Type of FU issued +system.cpu.iq.rate 0.424394 # Inst issue rate +system.cpu.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9034 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1531 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 653 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11245 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2732 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8445 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3250 # number of memory reference insts executed -system.cpu.iew.exec_branches 1412 # Number of branches executed -system.cpu.iew.exec_stores 1169 # Number of stores executed -system.cpu.iew.exec_rate 0.393211 # Inst execution rate -system.cpu.iew.wb_sent 8142 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8006 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3825 # num instructions producing a value -system.cpu.iew.wb_consumers 7724 # num instructions consuming a value +system.cpu.iew.exec_refs 3246 # number of memory reference insts executed +system.cpu.iew.exec_branches 1415 # Number of branches executed +system.cpu.iew.exec_stores 1167 # Number of stores executed +system.cpu.iew.exec_rate 0.404994 # Inst execution rate +system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3850 # num instructions producing a value +system.cpu.iew.wb_consumers 7766 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.372771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495210 # average fanout of values written-back +system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5517 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12113 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.473376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.288273 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9737 80.38% 80.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1166 9.63% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 419 3.46% 93.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 269 2.22% 95.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 155 1.28% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 162 1.34% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 54 0.45% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.32% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 112 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -362,69 +362,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 112 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23095 # The number of ROB reads -system.cpu.rob.rob_writes 23459 # The number of ROB writes -system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22290 # The number of ROB reads +system.cpu.rob.rob_writes 23328 # The number of ROB writes +system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.672977 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.672977 # CPI: Total CPI of All Threads -system.cpu.ipc 0.213996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.213996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38788 # number of integer regfile reads -system.cpu.int_regfile_writes 7902 # number of integer regfile writes +system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 38756 # number of integer regfile reads +system.cpu.int_regfile_writes 7886 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15082 # number of misc regfile reads +system.cpu.misc_regfile_reads 15116 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 149.911543 # Cycle average of tags in use -system.cpu.icache.total_refs 1558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.210702 # Average number of references to valid blocks. +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use +system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.911543 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073199 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1558 # number of overall hits -system.cpu.icache.overall_hits::total 1558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1931 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193164 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193164 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193164 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193164 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35747.989276 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35747.989276 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35747.989276 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits +system.cpu.icache.overall_hits::total 1564 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,110 +433,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 74 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 74 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 74 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10560500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10560500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.154842 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35319.397993 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35319.397993 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.954141 # Cycle average of tags in use -system.cpu.dcache.total_refs 2354 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.905405 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use +system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.954141 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021229 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021229 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2329 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2329 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2329 # number of overall hits -system.cpu.dcache.overall_hits::total 2329 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits +system.cpu.dcache.overall_hits::total 2306 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7113500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7113500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12639500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19753000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19753000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19753000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19753000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1918 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2831 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2831 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2831 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2831 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.099583 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.099583 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.177323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.177323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.177323 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.177323 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37243.455497 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37243.455497 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40641.479100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40641.479100 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39348.605578 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,124 +545,124 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055266 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36489.864865 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.052350 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.052350 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40476.190476 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40476.190476 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35707.482993 # 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Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 141.174021 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.600674 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001422 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005730 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::cpu.inst 141.702568 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.300474 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004324 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001413 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15191000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 299 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 406 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 406 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10097000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3413000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1657000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1657000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10097000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15167000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10097000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5070000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15167000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.936455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.903704 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.907731 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.936455 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.864865 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.912752 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.936455 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.864865 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.912752 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36105.357143 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39779.069767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36968.579235 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39535.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37232.843137 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37232.843137 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916479 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916479 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36189.964158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,50 +680,50 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9218000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3041500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12259500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9218000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4569000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9218000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4569000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13787000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.773585 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888889 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899329 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899329 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33158.273381 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37091.463415 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34054.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index e082161f0..4110b4ea0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10738000 # Number of ticks simulated -final_tick 10738000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 10412000 # Number of ticks simulated +final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30784 # Simulator instruction rate (inst/s) -host_op_rate 38403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71910456 # Simulator tick rate (ticks/s) -host_mem_usage 227312 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 40558 # Simulator instruction rate (inst/s) +host_op_rate 50593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91854675 # Simulator tick rate (ticks/s) +host_mem_usage 232720 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7936 # Number of bytes read from this memory -system.physmem.bytes_read::total 25728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1656919352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 739057553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2395976904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1656919352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 739057553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2395976904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,243 +70,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 21477 # number of cpu cycles simulated +system.cpu.numCycles 20825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2491 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1789 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1964 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.lookups 2492 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6988 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12142 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 958 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2639 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1622 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2325 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.169334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.586059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10418 79.79% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223 1.71% 81.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 193 1.48% 82.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 1.66% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.60% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.18% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 109 0.83% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 131 1.00% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115985 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.565349 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7128 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 89 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 945 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2432 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13276 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7383 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12436 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 239 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12439 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56552 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56280 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2229 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6758 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 47 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 766 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2732 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 47 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11190 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 47 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8841 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5157 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13057 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.677108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.355722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9364 71.72% 71.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1488 11.40% 83.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 792 6.07% 89.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 545 4.17% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 428 3.28% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 276 2.11% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 114 0.87% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 42 0.32% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13057 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.88% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 136 63.85% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 73 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5345 60.46% 60.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2263 25.60% 86.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1222 13.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8841 # Type of FU issued -system.cpu.iq.rate 0.411650 # Inst issue rate -system.cpu.iq.fu_busy_cnt 213 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024092 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31043 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16402 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7990 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8838 # Type of FU issued +system.cpu.iq.rate 0.424394 # Inst issue rate +system.cpu.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9034 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1531 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 653 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11245 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2732 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8445 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3250 # number of memory reference insts executed -system.cpu.iew.exec_branches 1412 # Number of branches executed -system.cpu.iew.exec_stores 1169 # Number of stores executed -system.cpu.iew.exec_rate 0.393211 # Inst execution rate -system.cpu.iew.wb_sent 8142 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8006 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3825 # num instructions producing a value -system.cpu.iew.wb_consumers 7724 # num instructions consuming a value +system.cpu.iew.exec_refs 3246 # number of memory reference insts executed +system.cpu.iew.exec_branches 1415 # Number of branches executed +system.cpu.iew.exec_stores 1167 # Number of stores executed +system.cpu.iew.exec_rate 0.404994 # Inst execution rate +system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3850 # num instructions producing a value +system.cpu.iew.wb_consumers 7766 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.372771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495210 # average fanout of values written-back +system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5517 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12113 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.473376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.288273 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9737 80.38% 80.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1166 9.63% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 419 3.46% 93.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 269 2.22% 95.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 155 1.28% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 162 1.34% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 54 0.45% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.32% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 112 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -317,69 +317,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 112 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23095 # The number of ROB reads -system.cpu.rob.rob_writes 23459 # The number of ROB writes -system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22290 # The number of ROB reads +system.cpu.rob.rob_writes 23328 # The number of ROB writes +system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.672977 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.672977 # CPI: Total CPI of All Threads -system.cpu.ipc 0.213996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.213996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38788 # number of integer regfile reads -system.cpu.int_regfile_writes 7902 # number of integer regfile writes +system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 38756 # number of integer regfile reads +system.cpu.int_regfile_writes 7886 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15082 # number of misc regfile reads +system.cpu.misc_regfile_reads 15116 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 149.911543 # Cycle average of tags in use -system.cpu.icache.total_refs 1558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.210702 # Average number of references to valid blocks. +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use +system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.911543 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073199 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1558 # number of overall hits -system.cpu.icache.overall_hits::total 1558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1931 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193164 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193164 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193164 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193164 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35747.989276 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35747.989276 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35747.989276 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits +system.cpu.icache.overall_hits::total 1564 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,110 +388,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 74 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 74 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 74 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10560500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10560500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.154842 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.954141 # Cycle average of tags in use -system.cpu.dcache.total_refs 2354 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.905405 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use +system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.954141 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021229 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021229 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2329 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2329 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2329 # number of overall hits -system.cpu.dcache.overall_hits::total 2329 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits +system.cpu.dcache.overall_hits::total 2306 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 502 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19753000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1918 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17259000 # 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miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.177323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.177323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.177323 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.177323 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37243.455497 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37243.455497 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40641.479100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40641.479100 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39348.605578 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,124 +500,124 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055266 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37091.463415 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34054.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index ae539a028..059498d9f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27316000 # Number of ticks simulated -final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000026 # Number of seconds simulated +sim_ticks 25969000 # Number of ticks simulated +final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78983 # Simulator instruction rate (inst/s) -host_op_rate 98109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 472376751 # Simulator tick rate (ticks/s) -host_mem_usage 225996 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 147661 # Simulator instruction rate (inst/s) +host_op_rate 183366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 839095918 # Simulator tick rate (ticks/s) +host_mem_usage 231680 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 527163567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 292868648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 820032216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 527163567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 527163567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 527163567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 292868648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 820032216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 54632 # number of cpu cycles simulated +system.cpu.numCycles 51938 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 2138 # nu system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 54632 # Number of busy cycles +system.cpu.num_busy_cycles 51938 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.832264 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.832264 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.056070 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.056070 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53211.618257 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.122861 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.122861 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020294 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020294 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51234.042553 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 154.336658 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 106.089659 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.246999 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003238 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001472 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004710 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 28611e3d6..1d71c4fe2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20518000 # Number of ticks simulated -final_tick 20518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20184000 # Number of ticks simulated +final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56112 # Simulator instruction rate (inst/s) -host_op_rate 56102 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197957466 # Simulator tick rate (ticks/s) -host_mem_usage 223380 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 50290 # Simulator instruction rate (inst/s) +host_op_rate 50282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174536927 # Simulator tick rate (ticks/s) +host_mem_usage 219492 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 988790330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 430451311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1419241641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 988790330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 988790330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 988790330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 430451311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1419241641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1005152596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 437574316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1442726912 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1005152596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1005152596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1005152596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 437574316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1442726912 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 41037 # number of cpu cycles simulated +system.cpu.numCycles 40369 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1146 # Number of BP lookups @@ -59,13 +59,13 @@ system.cpu.branch_predictor.RASInCorrect 32 # Nu system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5095 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5096 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8491 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8492 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1321 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1320 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2235 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken). @@ -76,12 +76,12 @@ system.cpu.execution_unit.executions 3144 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9756 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35650 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5387 # Number of cycles cpu stages are processed. -system.cpu.activity 13.127178 # Percentage of cycles cpu is active +system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34984 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5385 # Number of cycles cpu stages are processed. +system.cpu.activity 13.339444 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -93,72 +93,72 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 7.058308 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.943412 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.058308 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141677 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.943412 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144021 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.141677 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37412 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.144021 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 36744 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 8.833492 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38215 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 8.979663 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 37547 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 6.876721 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2785 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 6.786558 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 39795 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 6.990513 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 37585 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 6.896381 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 39127 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.026537 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38135 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.071667 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.076618 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.193639 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 147.247157 # Cycle average of tags in use -system.cpu.icache.total_refs 411 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 147.108411 # Cycle average of tags in use +system.cpu.icache.total_refs 410 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.247157 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071898 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071898 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits -system.cpu.icache.overall_hits::total 411 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 147.108411 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071830 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071830 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits +system.cpu.icache.overall_hits::total 410 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19614000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19614000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19614000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19614000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19614000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19614000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 755 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 755 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 755 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 755 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 755 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 755 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.455629 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.455629 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.455629 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.455629 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.455629 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.455629 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57017.441860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 57017.441860 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 57017.441860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 57017.441860 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19298000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19298000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19298000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19298000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19298000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19298000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.456233 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.456233 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56098.837209 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56098.837209 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56098.837209 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -179,34 +179,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17429500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17429500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17429500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17429500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17429500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17429500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.422517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.422517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.422517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54637.931034 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54637.931034 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17456000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17456000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17456000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17456000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17456000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17456000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54721.003135 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54721.003135 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.284631 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.235833 # Cycle average of tags in use system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.284631 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021798 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021798 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.235833 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021786 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021786 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits @@ -223,14 +223,14 @@ system.cpu.dcache.demand_misses::cpu.data 254 # n system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses system.cpu.dcache.overall_misses::total 254 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5537500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5537500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10150000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10150000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15687500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15687500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15687500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15687500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5402500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5402500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9244000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9244000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14646500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14646500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14646500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14646500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -247,14 +247,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.121648 system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60851.648352 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60851.648352 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62269.938650 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62269.938650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61761.811024 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61761.811024 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59368.131868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59368.131868 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56711.656442 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56711.656442 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -279,14 +279,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2913500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2913500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8052000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8052000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8052000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8052000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5111000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5111000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2905000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2905000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8016000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8016000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8016000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8016000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -295,26 +295,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59063.218391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59063.218391 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57127.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58347.826087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58347.826087 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58747.126437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58747.126437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56960.784314 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56960.784314 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 204.307813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 204.139180 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 148.858961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.448851 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006235 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 148.719836 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.419344 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004539 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006230 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17061000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5022000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22083000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2843500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2843500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 17061000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7865500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24926500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 17061000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7865500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24926500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5017500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2851000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2851000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7868500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24979000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7868500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24979000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53820.189274 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57724.137931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54660.891089 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55754.901961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55754.901961 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54783.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54783.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53976.340694 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57672.413793 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54772.277228 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55901.960784 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55901.960784 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54898.901099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54898.901099 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +395,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13201000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3966500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17167500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2221000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2221000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13201000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19388500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13201000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19388500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13248500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17211000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2227500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2227500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13248500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6190000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19438500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13248500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6190000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19438500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -417,17 +417,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.533123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45591.954023 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42493.811881 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43549.019608 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43549.019608 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41793.375394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45545.977011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42601.485149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43676.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43676.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ad536cc25..1fd33095f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12925500 # Number of ticks simulated -final_tick 12925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12603500 # Number of ticks simulated +final_tick 12603500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52967 # Simulator instruction rate (inst/s) -host_op_rate 52957 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132735366 # Simulator tick rate (ticks/s) -host_mem_usage 224404 # Number of bytes of host memory used +host_inst_rate 49943 # Simulator instruction rate (inst/s) +host_op_rate 49935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122043566 # Simulator tick rate (ticks/s) +host_mem_usage 220512 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21696 # Nu system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 480 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1678542416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 698154810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2376697226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1678542416 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1678542416 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1678542416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 698154810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2376697226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1721426588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 715991590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2437418177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1721426588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1721426588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1721426588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 715991590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2437418177 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,101 +46,101 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25852 # number of cpu cycles simulated +system.cpu.numCycles 25208 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2052 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1365 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2076 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1377 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1625 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 468 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1640 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 471 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 254 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 262 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8806 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12660 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2052 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 722 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1287 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 809 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12782 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2076 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 733 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3147 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1298 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 705 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1908 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.923414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.233238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1923 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.958099 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.266693 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10597 77.29% 77.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1289 9.40% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 106 0.77% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 138 1.01% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 293 2.14% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 99 0.72% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 151 1.10% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 124 0.90% 93.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 913 6.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10194 76.41% 76.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1306 9.79% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 106 0.79% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 141 1.06% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 294 2.20% 90.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 100 0.75% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 154 1.15% 92.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 127 0.95% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 919 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079375 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.489711 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8966 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 966 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2934 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 143 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082355 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.507061 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8622 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 899 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2969 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11758 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11860 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9155 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 277 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2801 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 144 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11265 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13414 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13410 # Number of integer rename lookups +system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8807 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 544 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2833 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11360 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 96 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13517 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3481 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1172 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3542 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 277 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8008 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3225 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1836 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.584099 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.244040 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8869 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8060 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1840 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.604153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.265993 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10210 74.47% 74.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1436 10.47% 84.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 842 6.14% 91.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 525 3.83% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 351 2.56% 97.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 220 1.60% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.62% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9853 73.86% 73.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1401 10.50% 84.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 847 6.35% 90.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 533 4.00% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 353 2.65% 97.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 227 1.70% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 84 0.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 29 0.22% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13341 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available @@ -176,113 +176,113 @@ system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4734 59.12% 59.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2177 27.19% 86.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1088 13.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4766 59.13% 59.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2195 27.23% 86.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1090 13.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8008 # Type of FU issued -system.cpu.iq.rate 0.309763 # Inst issue rate +system.cpu.iq.FU_type_0::total 8060 # Type of FU issued +system.cpu.iq.rate 0.319740 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018981 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29921 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12064 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7226 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018859 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29653 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7261 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8158 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8210 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1209 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1225 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 247 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 94 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1172 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 170 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10299 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7665 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 343 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7692 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2065 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 368 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1409 # number of nop insts executed -system.cpu.iew.exec_refs 3123 # number of memory reference insts executed -system.cpu.iew.exec_branches 1292 # Number of branches executed +system.cpu.iew.exec_nop 1417 # number of nop insts executed +system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_branches 1305 # Number of branches executed system.cpu.iew.exec_stores 1062 # Number of stores executed -system.cpu.iew.exec_rate 0.296495 # Inst execution rate -system.cpu.iew.wb_sent 7314 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7228 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2794 # num instructions producing a value -system.cpu.iew.wb_consumers 3985 # num instructions consuming a value +system.cpu.iew.exec_rate 0.305141 # Inst execution rate +system.cpu.iew.wb_sent 7351 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7263 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2827 # num instructions producing a value +system.cpu.iew.wb_consumers 4035 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.279592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.701129 # average fanout of values written-back +system.cpu.iew.wb_rate 0.288123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.700620 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4420 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4478 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.450027 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.233846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.463668 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.253066 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10496 81.26% 81.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1026 7.94% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 636 4.92% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 301 2.33% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.15% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 90 0.70% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 76 0.59% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 38 0.29% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10143 80.90% 80.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 988 7.88% 88.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 634 5.06% 93.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 313 2.50% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.18% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 91 0.73% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 75 0.60% 98.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12537 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,67 +295,67 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23031 # The number of ROB reads -system.cpu.rob.rob_writes 21266 # The number of ROB writes +system.cpu.rob.rob_reads 22709 # The number of ROB reads +system.cpu.rob.rob_writes 21393 # The number of ROB writes system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12142 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11867 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 5.013964 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.013964 # CPI: Total CPI of All Threads -system.cpu.ipc 0.199443 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.199443 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10440 # number of integer regfile reads -system.cpu.int_regfile_writes 5074 # number of integer regfile writes +system.cpu.cpi 4.889061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.889061 # CPI: Total CPI of All Threads +system.cpu.ipc 0.204538 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.204538 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10482 # number of integer regfile reads +system.cpu.int_regfile_writes 5097 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.misc_regfile_reads 151 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.949608 # Cycle average of tags in use -system.cpu.icache.total_refs 1474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.691170 # Cycle average of tags in use +system.cpu.icache.total_refs 1486 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.309942 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.345029 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.949608 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079077 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079077 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits -system.cpu.icache.overall_hits::total 1474 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses -system.cpu.icache.overall_misses::total 434 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15909000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15909000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15909000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15909000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15909000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.227463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.227463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.227463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.227463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.227463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36656.682028 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36656.682028 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36656.682028 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36656.682028 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 161.691170 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078951 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078951 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1486 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1486 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1486 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1486 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1486 # number of overall hits +system.cpu.icache.overall_hits::total 1486 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15633000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15633000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15633000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15633000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15633000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15633000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1923 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1923 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1923 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1923 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227249 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.227249 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.227249 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.227249 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.227249 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.227249 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35773.455378 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35773.455378 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35773.455378 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35773.455378 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,94 +364,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179245 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.179245 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.179245 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36308.479532 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36308.479532 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36308.479532 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36308.479532 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36308.479532 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36308.479532 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12431000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12431000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12431000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12431000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12431000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12431000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177847 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.177847 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.177847 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36347.953216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36347.953216 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 90.879080 # Cycle average of tags in use -system.cpu.dcache.total_refs 2407 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 90.751581 # Cycle average of tags in use +system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.070922 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 17.085106 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 90.879080 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022187 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022187 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1830 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1830 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits -system.cpu.dcache.overall_hits::total 2407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 348 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 348 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses -system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5699000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5699000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13075000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13075000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18774000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18774000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18774000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18774000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1978 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1978 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 90.751581 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022156 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022156 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1833 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 576 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2409 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2409 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2409 # number of overall hits +system.cpu.dcache.overall_hits::total 2409 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses +system.cpu.dcache.overall_misses::total 498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5432500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5432500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11660000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11660000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17092500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17092500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17092500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17092500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2903 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2903 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2903 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2903 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074823 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.074823 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.170858 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.170858 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.170858 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.170858 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38506.756757 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38506.756757 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37571.839080 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37571.839080 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37850.806452 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37850.806452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37850.806452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37850.806452 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075177 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075177 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377297 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.377297 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.171311 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.171311 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.171311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.171311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36459.731544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36459.731544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33409.742120 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33409.742120 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34322.289157 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34322.289157 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,14 +460,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 298 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 298 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 357 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 357 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 357 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 357 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -476,42 +476,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5913000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5913000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2072000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2072000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5906500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5906500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5906500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5906500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045409 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048570 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048570 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048504 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048504 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42605.555556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42605.555556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.306774 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.970580 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.083724 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.223050 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005007 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001746 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006754 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 163.825301 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.145280 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001744 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -529,17 +529,17 @@ system.cpu.l2cache.demand_misses::total 480 # nu system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12053000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3723500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15776500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12053000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5721500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17774500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12053000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5721500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17774500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3740000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15824000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2020500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2020500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12084000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5760500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17844500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12084000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5760500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17844500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) @@ -562,17 +562,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993789 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35554.572271 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41372.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36775.058275 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37030.208333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37030.208333 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35646.017699 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41555.555556 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36885.780886 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39617.647059 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39617.647059 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37176.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37176.041667 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,17 +592,17 @@ system.cpu.l2cache.demand_mshr_misses::total 480 system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10969500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3448000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14417500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10969500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5287500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16257000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10969500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5287500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16257000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11000500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14466000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1861500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1861500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11000500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5327000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16327500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11000500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5327000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16327500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses @@ -614,17 +614,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32358.407080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38311.111111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33607.226107 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32449.852507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38505.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33720.279720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 654ee7d3b..b337ea793 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 33399000 # Number of ticks simulated -final_tick 33399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 31633000 # Number of ticks simulated +final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212162 # Simulator instruction rate (inst/s) -host_op_rate 212025 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1217250605 # Simulator tick rate (ticks/s) -host_mem_usage 223376 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 284864 # Simulator instruction rate (inst/s) +host_op_rate 284628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1547353604 # Simulator tick rate (ticks/s) +host_mem_usage 219460 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 576783736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 264439055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 841222791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 576783736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 576783736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 576783736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 264439055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 841222791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 66798 # number of cpu cycles simulated +system.cpu.numCycles 63266 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5814 # Number of instructions committed @@ -65,18 +65,18 @@ system.cpu.num_mem_refs 2089 # nu system.cpu.num_load_insts 1163 # Number of load instructions system.cpu.num_store_insts 926 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 66798 # Number of busy cycles +system.cpu.num_busy_cycles 63266 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 133.141027 # Cycle average of tags in use +system.cpu.icache.tagsinuse 132.545353 # Cycle average of tags in use system.cpu.icache.total_refs 5513 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 133.141027 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.065010 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.065010 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.064719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -89,12 +89,12 @@ system.cpu.icache.demand_misses::cpu.inst 303 # n system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses system.cpu.icache.overall_misses::total 303 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses @@ -107,12 +107,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.742269 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.742269 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021421 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021421 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits @@ -171,14 +171,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -195,14 +195,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.881290 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 134.495649 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 54.385641 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004104 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001660 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index b2cd52879..233f5f73b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11763500 # Number of ticks simulated -final_tick 11763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11490500 # Number of ticks simulated +final_tick 11490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53396 # Simulator instruction rate (inst/s) -host_op_rate 53387 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108411505 # Simulator tick rate (ticks/s) -host_mem_usage 219412 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 46998 # Simulator instruction rate (inst/s) +host_op_rate 46991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93211132 # Simulator tick rate (ticks/s) +host_mem_usage 217464 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28992 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1909635738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 549496323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2459132061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1909635738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1909635738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1909635738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 549496323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2459132061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory +system.physmem.num_reads::total 453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1955006310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 568121492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2523127801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1955006310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1955006310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1955006310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 568121492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2523127801 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,243 +46,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 23528 # number of cpu cycles simulated +system.cpu.numCycles 22982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2457 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2014 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2481 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2031 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2037 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 618 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2060 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 620 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7380 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14306 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2457 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 778 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2377 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1402 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 936 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7156 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14473 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 780 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2399 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1409 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 837 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1859 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.229249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.662964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1870 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 316 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.275829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.704070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9261 79.58% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 173 1.49% 81.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 162 1.39% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 137 1.18% 83.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 198 1.70% 85.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.27% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 250 2.15% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 106 0.91% 89.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1203 10.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8945 78.85% 78.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 173 1.53% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 163 1.44% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 136 1.20% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 199 1.75% 84.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 148 1.30% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 251 2.21% 88.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.95% 89.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 10.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104429 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.608041 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7505 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1074 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2213 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 351 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12646 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 11344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107954 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.629754 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7303 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 957 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2216 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 791 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 355 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12764 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7717 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 446 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 386 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2059 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 246 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11999 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10316 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19545 # Number of integer rename lookups +system.cpu.rename.SquashCycles 791 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7518 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2068 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 254 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12054 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 208 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10357 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19653 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19598 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5318 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5359 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 543 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1909 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 528 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2068 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1915 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10820 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10860 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9196 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 160 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4145 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9235 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4823 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4140 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11638 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.790170 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.525459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.814087 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.547249 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8215 70.59% 70.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1109 9.53% 80.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 778 6.68% 86.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 515 4.43% 91.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 472 4.06% 95.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 322 2.77% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 140 1.20% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 48 0.41% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7932 69.92% 69.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1090 9.61% 79.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 771 6.80% 86.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 520 4.58% 90.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 472 4.16% 95.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 326 2.87% 97.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 145 1.28% 99.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.43% 99.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11344 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.34% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 75 43.86% 46.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.29% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 76 43.43% 45.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 95 54.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5661 61.56% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1833 19.93% 81.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1700 18.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5682 61.53% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1849 20.02% 81.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1702 18.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9196 # Type of FU issued -system.cpu.iq.rate 0.390853 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018595 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30299 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15649 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8318 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9235 # Type of FU issued +system.cpu.iq.rate 0.401836 # Inst issue rate +system.cpu.iq.fu_busy_cnt 175 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018950 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30091 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15718 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8353 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9376 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1090 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1107 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 863 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 229 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10884 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 101 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1909 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 138 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10924 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2068 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1915 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8699 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1698 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 497 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 381 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8741 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1709 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3253 # number of memory reference insts executed -system.cpu.iew.exec_branches 1376 # Number of branches executed -system.cpu.iew.exec_stores 1555 # Number of stores executed -system.cpu.iew.exec_rate 0.369730 # Inst execution rate -system.cpu.iew.wb_sent 8502 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4327 # num instructions producing a value -system.cpu.iew.wb_consumers 6939 # num instructions consuming a value +system.cpu.iew.exec_refs 3273 # number of memory reference insts executed +system.cpu.iew.exec_branches 1381 # Number of branches executed +system.cpu.iew.exec_stores 1564 # Number of stores executed +system.cpu.iew.exec_rate 0.380341 # Inst execution rate +system.cpu.iew.wb_sent 8540 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8380 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4334 # num instructions producing a value +system.cpu.iew.wb_consumers 6987 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.354684 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.623577 # average fanout of values written-back +system.cpu.iew.wb_rate 0.364633 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.620295 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5101 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5141 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.316329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.548849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.335888 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8424 77.61% 77.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1042 9.60% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 639 5.89% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 261 2.40% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.68% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 104 0.96% 98.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.62% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.38% 99.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94 0.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8133 77.07% 77.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1033 9.79% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 640 6.06% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 254 2.41% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.74% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 109 1.03% 98.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 61 0.58% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.40% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 97 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10553 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -293,68 +293,68 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21653 # The number of ROB reads -system.cpu.rob.rob_writes 22571 # The number of ROB writes -system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21389 # The number of ROB reads +system.cpu.rob.rob_writes 22658 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11638 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 4.062155 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.062155 # CPI: Total CPI of All Threads -system.cpu.ipc 0.246175 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.246175 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13809 # number of integer regfile reads -system.cpu.int_regfile_writes 7224 # number of integer regfile writes +system.cpu.cpi 3.967887 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.967887 # CPI: Total CPI of All Threads +system.cpu.ipc 0.252023 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.252023 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13882 # number of integer regfile reads +system.cpu.int_regfile_writes 7254 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.502715 # Cycle average of tags in use -system.cpu.icache.total_refs 1427 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 173.017509 # Cycle average of tags in use +system.cpu.icache.total_refs 1435 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.008427 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.030899 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.502715 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1427 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1427 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1427 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1427 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1427 # number of overall hits -system.cpu.icache.overall_hits::total 1427 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses -system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16299000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16299000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16299000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16299000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16299000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16299000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1859 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1859 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1859 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1859 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232383 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.232383 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.232383 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.232383 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.232383 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.232383 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37729.166667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37729.166667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37729.166667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37729.166667 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 173.017509 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084481 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084481 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits +system.cpu.icache.overall_hits::total 1435 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15962500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15962500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15962500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15962500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15962500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15962500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1870 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1870 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1870 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1870 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232620 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.232620 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.232620 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.232620 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.232620 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.232620 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36695.402299 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36695.402299 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36695.402299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36695.402299 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,94 +363,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 76 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 76 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 76 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13111000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13111000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191501 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191501 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191501 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36828.651685 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36828.651685 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13118500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13118500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13118500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13118500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13118500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13118500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.190374 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.190374 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.190374 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36849.719101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36849.719101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.218136 # Cycle average of tags in use -system.cpu.dcache.total_refs 2196 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.742574 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.294290 # Cycle average of tags in use +system.cpu.dcache.total_refs 2199 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.558824 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.218136 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015434 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015434 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2196 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2196 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2196 # number of overall hits -system.cpu.dcache.overall_hits::total 2196 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses -system.cpu.dcache.overall_misses::total 420 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12824500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12824500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16557000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16557000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16557000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16557000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1570 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.294290 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015453 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015453 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1487 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1487 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 712 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 712 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits +system.cpu.dcache.overall_hits::total 2199 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 94 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 94 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 428 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 428 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 428 # number of overall misses +system.cpu.dcache.overall_misses::total 428 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3573500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3573500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11341500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14915000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14915000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14915000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14915000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1581 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2616 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2616 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2616 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2616 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.057962 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.057962 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.160550 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.160550 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.160550 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.160550 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41016.483516 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41016.483516 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38980.243161 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38980.243161 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39421.428571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39421.428571 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2627 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2627 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2627 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2627 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.059456 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.059456 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319312 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319312 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162923 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162923 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.162923 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.162923 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38015.957447 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38015.957447 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33956.586826 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33956.586826 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34848.130841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34848.130841 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,58 +459,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 37 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 282 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 282 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 39 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2168500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2168500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4254500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4254500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4254500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4254500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034395 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034395 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2204500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2204500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4252000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4252000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4252000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4252000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034788 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034788 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038609 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038609 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40157.407407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40157.407407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44382.978723 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44382.978723 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038828 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038828 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038828 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038828 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40081.818182 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40081.818182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43563.829787 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43563.829787 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41686.274510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41686.274510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41686.274510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41686.274510 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 203.045072 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.278770 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 405 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012346 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 406 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012315 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.614713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.430359 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005237 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006196 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.783445 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.495324 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005242 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006204 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits @@ -518,60 +518,60 @@ system.cpu.l2cache.demand_hits::total 5 # nu system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits system.cpu.l2cache.overall_hits::total 5 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 405 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 406 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 453 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 351 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses -system.cpu.l2cache.overall_misses::total 452 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12737500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2108500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14846000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2028500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2028500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12737500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4137000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16874500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12737500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4137000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16874500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses +system.cpu.l2cache.overall_misses::total 453 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12757000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2149000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14906000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1998500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12757000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4147500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16904500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12757000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4147500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16904500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 356 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 458 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 458 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987835 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.989059 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.989083 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.989059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36289.173789 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39046.296296 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36656.790123 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43159.574468 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43159.574468 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37332.964602 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37332.964602 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.989083 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36344.729345 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39072.727273 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36714.285714 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42521.276596 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42521.276596 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36344.729345 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40661.764706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37316.777042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36344.729345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40661.764706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37316.777042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,49 +581,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 405 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 406 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11613500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1942500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13556000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1882000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1882000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11613500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3824500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15438000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11613500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3824500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15438000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 453 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11632000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1980500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13612500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1853000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1853000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11632000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3833500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11632000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3833500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15465500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33086.894587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35972.222222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33471.604938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40042.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40042.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33139.601140 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36009.090909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33528.325123 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39425.531915 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39425.531915 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 00104c1c9..9881f90a7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18878500 # Number of ticks simulated -final_tick 18878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18570500 # Number of ticks simulated +final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36734 # Simulator instruction rate (inst/s) -host_op_rate 36730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130153209 # Simulator tick rate (ticks/s) -host_mem_usage 229488 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 42410 # Simulator instruction rate (inst/s) +host_op_rate 42404 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147804999 # Simulator tick rate (ticks/s) +host_mem_usage 221464 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,35 +19,35 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 979738856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454273380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1434012236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 979738856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 979738856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 979738856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454273380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1434012236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 995988261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 461807706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1457795967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 995988261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 995988261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 995988261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 461807706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1457795967 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 37758 # number of cpu cycles simulated +system.cpu.numCycles 37142 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1630 # Number of BP lookups +system.cpu.branch_predictor.lookups 1632 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1167 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.596567 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 37.532134 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1125 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5623 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9611 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1685 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1682 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 1483 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken). @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 3966 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 10163 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9963 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 500 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31528 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6230 # Number of cycles cpu stages are processed. -system.cpu.activity 16.499815 # Percentage of cycles cpu is active +system.cpu.timesIdled 471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30915 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. +system.cpu.activity 16.765387 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -75,72 +75,72 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.088042 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.972405 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.088042 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141083 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.972405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143423 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.141083 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33195 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4563 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.084856 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34564 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.459134 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34714 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.143423 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32576 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4566 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.293361 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33943 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3199 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.612891 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34098 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.061868 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36776 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.195574 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36160 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.600773 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34592 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3166 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.384978 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.643907 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33973 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.532120 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.498326 # Cycle average of tags in use -system.cpu.icache.total_refs 829 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.328432 # Cycle average of tags in use +system.cpu.icache.total_refs 828 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.845361 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.498326 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066650 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066650 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits -system.cpu.icache.overall_hits::total 829 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 136.328432 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066567 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066567 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 828 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 828 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 828 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 828 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 828 # number of overall hits +system.cpu.icache.overall_hits::total 828 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19654500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19654500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19654500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19654500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19654500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19654500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1179 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1179 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1179 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1179 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.296862 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.296862 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.296862 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.296862 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.296862 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.296862 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56155.714286 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56155.714286 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56155.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56155.714286 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19327000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19327000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19327000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19327000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19327000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19327000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297114 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.297114 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.297114 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.297114 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.297114 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.297114 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,34 +161,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15991000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15991000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.246819 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.246819 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.246819 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54951.890034 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54951.890034 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54951.890034 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54951.890034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54951.890034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54951.890034 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15994000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15994000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15994000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54962.199313 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54962.199313 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.673308 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.607202 # Cycle average of tags in use system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.673308 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020184 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020184 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.607202 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020168 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020168 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits @@ -205,14 +205,14 @@ system.cpu.dcache.demand_misses::cpu.data 343 # n system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses system.cpu.dcache.overall_misses::total 343 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3569000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3569000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17304500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17304500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20873500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20873500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20873500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20873500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3485500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3485500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15720000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15720000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19205500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19205500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19205500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19205500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -229,20 +229,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.247118 system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58508.196721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58508.196721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61363.475177 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61363.475177 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60855.685131 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60855.685131 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60855.685131 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60855.685131 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57139.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57139.344262 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55744.680851 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55744.680851 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2306500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51255.555556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits @@ -261,14 +261,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3064500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3064500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3073000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3073000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4525000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4525000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7589500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7589500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7589500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7589500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7598000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7598000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7598000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7598000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -277,26 +277,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56907.407407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56907.407407 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55864.197531 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55864.197531 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56218.518519 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56218.518519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56218.518519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56218.518519 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.089529 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 161.896728 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 136.006338 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.083191 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000796 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004947 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 135.841585 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.055143 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004146 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000795 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004941 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2985000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18639000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4433500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15654000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23072500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15654000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7418500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23072500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15675500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3006500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18682000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4441500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4441500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15675500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7448000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23123500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15675500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7448000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23123500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54166.089965 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56320.754717 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54500 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54734.567901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54734.567901 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54544.917258 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54544.917258 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54240.484429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56726.415094 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54625.730994 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54833.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54833.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54665.484634 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54665.484634 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14482000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3454500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3454500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5797500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17936500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5797500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17936500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2365000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14525000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5827500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17987500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5827500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17987500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42003.460208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44207.547170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42345.029240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42076.124567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44622.641509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42470.760234 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42746.913580 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42746.913580 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 3eb56a69e..37ab13bca 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29527000 # Number of ticks simulated -final_tick 29527000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27800000 # Number of ticks simulated +final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69145 # Simulator instruction rate (inst/s) -host_op_rate 69130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 383102769 # Simulator tick rate (ticks/s) -host_mem_usage 229488 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 251441 # Simulator instruction rate (inst/s) +host_op_rate 251244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1310200039 # Simulator tick rate (ticks/s) +host_mem_usage 220428 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 552714465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 290446032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 843160497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552714465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552714465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552714465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 290446032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 843160497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 59054 # number of cpu cycles simulated +system.cpu.numCycles 55600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 59054 # Number of busy cycles +system.cpu.num_busy_cycles 55600 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 117.127109 # Cycle average of tags in use +system.cpu.icache.tagsinuse 117.043638 # Cycle average of tags in use system.cpu.icache.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 117.127109 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.057191 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.057191 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.057150 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55673.151751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.138993 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.138993 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020053 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020053 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2982000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4536000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4536000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7518000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55688.888889 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 142.279716 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 116.596239 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 25.683477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004342 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004339 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 87ffbf265..36ed22f0b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,269 +1,269 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12607000 # Number of ticks simulated -final_tick 12607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12215000 # Number of ticks simulated +final_tick 12215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20393 # Simulator instruction rate (inst/s) -host_op_rate 36936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47780701 # Simulator tick rate (ticks/s) -host_mem_usage 271708 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 33465 # Simulator instruction rate (inst/s) +host_op_rate 60609 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75963972 # Simulator tick rate (ticks/s) +host_mem_usage 227744 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9216 # Number of bytes read from this memory -system.physmem.bytes_read::total 28672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1543269612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 731022448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2274292060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1543269612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1543269612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1543269612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 731022448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2274292060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory +system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1598035203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 770200573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2368235776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1598035203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1598035203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1598035203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 770200573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2368235776 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 25215 # number of cpu cycles simulated +system.cpu.numCycles 24431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3186 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3186 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 582 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2623 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits +system.cpu.BPredUnit.lookups 3187 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3187 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 588 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2597 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8059 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15139 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4132 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2534 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3329 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1963 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 17595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.538335 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.007747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7858 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15336 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4160 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2551 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3088 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 59 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 17124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.595013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.047737 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 13576 77.16% 77.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 181 1.03% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 155 0.88% 79.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 205 1.17% 80.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 167 0.95% 81.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 166 0.94% 82.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 255 1.45% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.06% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2703 15.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13067 76.31% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 184 1.07% 77.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 158 0.92% 78.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 198 1.16% 79.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 177 1.03% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 181 1.06% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 237 1.38% 82.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 1.12% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2730 15.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 17595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126353 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.600397 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8491 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3340 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3724 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1929 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25781 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1929 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8836 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2060 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 411 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3455 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 904 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24174 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 785 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 26591 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 58087 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 58071 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 17124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130449 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.627727 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8263 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3049 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3749 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1947 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26028 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1947 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8634 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1940 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3487 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 694 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24257 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 601 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 26511 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 58176 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 58160 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 15531 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2042 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1780 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 15451 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2379 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1816 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21436 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21504 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18052 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 228 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 18146 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10979 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14783 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 17595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.025973 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.871104 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 17124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.059682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.899800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12050 68.49% 68.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1507 8.56% 77.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 947 5.38% 82.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 676 3.84% 86.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 766 4.35% 90.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 693 3.94% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 642 3.65% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 270 1.53% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11674 68.17% 68.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1321 7.71% 75.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 996 5.82% 81.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 705 4.12% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 752 4.39% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 712 4.16% 94.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 641 3.74% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 280 1.64% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 43 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 17595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 141 77.47% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21 11.54% 89.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166 80.19% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21 10.14% 90.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 20 9.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14462 80.11% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2078 11.51% 91.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1508 8.35% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14557 80.22% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2050 11.30% 91.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1535 8.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18052 # Type of FU issued -system.cpu.iq.rate 0.715923 # Inst issue rate -system.cpu.iq.fu_busy_cnt 182 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010082 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 54101 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32345 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18146 # Type of FU issued +system.cpu.iq.rate 0.742745 # Inst issue rate +system.cpu.iq.fu_busy_cnt 207 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011407 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53836 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32525 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16639 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18226 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18345 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 132 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 130 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1327 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1929 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1947 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1327 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21473 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1780 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 21541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 44 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2379 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1816 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 642 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 708 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17072 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1925 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 643 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17109 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1898 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1037 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3318 # number of memory reference insts executed +system.cpu.iew.exec_refs 3313 # number of memory reference insts executed system.cpu.iew.exec_branches 1690 # Number of branches executed -system.cpu.iew.exec_stores 1393 # Number of stores executed -system.cpu.iew.exec_rate 0.677057 # Inst execution rate -system.cpu.iew.wb_sent 16795 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16596 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10614 # num instructions producing a value -system.cpu.iew.wb_consumers 16437 # num instructions consuming a value +system.cpu.iew.exec_stores 1415 # Number of stores executed +system.cpu.iew.exec_rate 0.700299 # Inst execution rate +system.cpu.iew.wb_sent 16835 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16643 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10619 # num instructions producing a value +system.cpu.iew.wb_consumers 16444 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.658180 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.645738 # average fanout of values written-back +system.cpu.iew.wb_rate 0.681225 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.645767 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11727 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11795 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 596 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15666 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.622048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.485565 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 595 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15177 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.642090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514380 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12031 76.80% 76.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1491 9.52% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 525 3.35% 89.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 708 4.52% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 369 2.36% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 134 0.86% 97.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 127 0.81% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 76 0.49% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 205 1.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11633 76.65% 76.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1329 8.76% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 606 3.99% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 700 4.61% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 357 2.35% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 136 0.90% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 126 0.83% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 80 0.53% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 210 1.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15666 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15177 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,68 +274,68 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 205 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 210 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36933 # The number of ROB reads -system.cpu.rob.rob_writes 44901 # The number of ROB writes +system.cpu.rob.rob_reads 36507 # The number of ROB reads +system.cpu.rob.rob_writes 45058 # The number of ROB writes system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7307 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 4.686803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.686803 # CPI: Total CPI of All Threads -system.cpu.ipc 0.213365 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.213365 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 30057 # number of integer regfile reads -system.cpu.int_regfile_writes 17963 # number of integer regfile writes +system.cpu.cpi 4.541078 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.541078 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220212 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220212 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 30201 # number of integer regfile reads +system.cpu.int_regfile_writes 17927 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7481 # number of misc regfile reads +system.cpu.misc_regfile_reads 7454 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.992239 # Cycle average of tags in use -system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.134426 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 147.121871 # Cycle average of tags in use +system.cpu.icache.total_refs 1595 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.195440 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.992239 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071285 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071285 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits -system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 397 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 397 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 397 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 397 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 397 # number of overall misses -system.cpu.icache.overall_misses::total 397 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14592000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14592000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14592000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14592000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14592000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14592000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1963 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1963 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1963 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1963 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1963 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1963 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.202241 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.202241 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.202241 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.202241 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.202241 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.202241 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36755.667506 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36755.667506 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36755.667506 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36755.667506 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 147.121871 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071837 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071837 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1595 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1595 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1595 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1595 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1595 # number of overall hits +system.cpu.icache.overall_hits::total 1595 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses +system.cpu.icache.overall_misses::total 399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14232000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14232000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14232000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14232000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14232000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200100 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.200100 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.200100 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.200100 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.200100 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.200100 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35669.172932 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35669.172932 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35669.172932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35669.172932 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,48 +350,48 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 92 system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 305 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 305 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 305 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11283000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11283000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11283000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155374 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155374 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.155374 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36993.442623 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36993.442623 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 307 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 307 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 307 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 307 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 307 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11314000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11314000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11314000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11314000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11314000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11314000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153962 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153962 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153962 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36853.420195 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36853.420195 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.306580 # Cycle average of tags in use -system.cpu.dcache.total_refs 2452 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.146853 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.059195 # Cycle average of tags in use +system.cpu.dcache.total_refs 2428 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.630137 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.306580 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020339 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020339 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1594 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1594 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.059195 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020766 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020766 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2452 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2452 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2452 # number of overall hits -system.cpu.dcache.overall_hits::total 2452 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2428 # number of overall hits +system.cpu.dcache.overall_hits::total 2428 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses @@ -400,38 +400,38 @@ system.cpu.dcache.demand_misses::cpu.data 209 # n system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses system.cpu.dcache.overall_misses::total 209 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3068500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3068500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8232000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8232000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8232000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8232000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1727 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1727 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4790000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4790000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3017000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3017000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7807000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7807000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7807000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7807000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1703 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2661 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2661 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2661 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2661 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077012 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.077012 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2637 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2637 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078097 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078097 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.078542 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.078542 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.078542 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.078542 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38823.308271 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38823.308271 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40375 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39387.559809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39387.559809 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.079257 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.079257 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.079257 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.079257 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36015.037594 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36015.037594 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39697.368421 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39697.368421 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37354.066986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37354.066986 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -440,117 +440,117 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 65 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 68 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 68 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2714500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2714500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2840500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2840500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5555000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5555000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5555000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5555000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039375 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2865000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2865000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041691 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041691 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054115 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054115 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054115 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054115 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39919.117647 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39919.117647 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37375 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37375 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38576.388889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38576.388889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38576.388889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38576.388889 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055745 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055745 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055745 # 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miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997319 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994709 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996721 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993485 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997773 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996721 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995595 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993485 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997773 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36100.328947 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38882.352941 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36608.870968 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36342.105263 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36342.105263 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36100.328947 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37541.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36563.616071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36100.328947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37541.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36563.616071 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995595 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36078.688525 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38809.859155 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36594.414894 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36697.368421 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36697.368421 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36078.688525 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37717.687075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36611.725664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36078.688525 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37717.687075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36611.725664 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,50 +559,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 68 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 372 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 376 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 448 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 448 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10010000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2437500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12447500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10010000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14979500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10010000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4969500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14979500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10035000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2539500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12574500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2558000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2558000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5097500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15132500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10035000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5097500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15132500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997319 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994709 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997773 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995595 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997773 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32927.631579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35845.588235 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33461.021505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33315.789474 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33315.789474 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995595 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.639344 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35767.605634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33442.819149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33657.894737 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33657.894737 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index c50a3998a..bc1030252 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29676000 # Number of ticks simulated -final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 28356000 # Number of ticks simulated +final_tick 28356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72347 # Simulator instruction rate (inst/s) -host_op_rate 131001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 398795084 # Simulator tick rate (ticks/s) -host_mem_usage 269536 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 134366 # Simulator instruction rate (inst/s) +host_op_rate 243261 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 707485860 # Simulator tick rate (ticks/s) +host_mem_usage 226568 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 489553848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288987734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 778541582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 489553848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 489553848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 489553848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288987734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 778541582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 512343067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302440401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814783467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512343067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512343067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512343067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302440401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814783467 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 59352 # number of cpu cycles simulated +system.cpu.numCycles 56712 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1986 # nu system.cpu.num_load_insts 1052 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 59352 # Number of busy cycles +system.cpu.num_busy_cycles 56712 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.746399 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.556077 # Cycle average of tags in use system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.746399 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051634 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051634 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 105.556077 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051541 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051541 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.866493 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.800961 # Cycle average of tags in use system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.866493 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019743 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 80.800961 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.019727 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.019727 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits @@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) @@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067472 system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 134.266314 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 134.040949 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.749768 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.516546 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003227 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000870 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.564188 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.476761 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 8a8cdff85..2a32b08b0 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 14993500 # Number of ticks simulated -final_tick 14993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 14818500 # Number of ticks simulated +final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32330 # Simulator instruction rate (inst/s) -host_op_rate 32329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38030689 # Simulator tick rate (ticks/s) -host_mem_usage 224252 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host +host_inst_rate 71701 # Simulator instruction rate (inst/s) +host_op_rate 71694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83350191 # Simulator tick rate (ticks/s) +host_mem_usage 220256 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory -system.physmem.bytes_read::total 62336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory -system.physmem.num_reads::total 974 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2659285690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1498249241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4157534932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2659285690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2659285690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2659285690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1498249241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4157534932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory +system.physmem.bytes_read::total 62720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory +system.physmem.num_reads::total 980 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2699328542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1533218612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4232547154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2699328542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2699328542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2699328542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1533218612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4232547154 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4043 # DTB read hits -system.cpu.dtb.read_misses 104 # DTB read misses +system.cpu.dtb.read_hits 4173 # DTB read hits +system.cpu.dtb.read_misses 101 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4147 # DTB read accesses -system.cpu.dtb.write_hits 2093 # DTB write hits -system.cpu.dtb.write_misses 65 # DTB write misses +system.cpu.dtb.read_accesses 4274 # DTB read accesses +system.cpu.dtb.write_hits 2094 # DTB write hits +system.cpu.dtb.write_misses 67 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2158 # DTB write accesses -system.cpu.dtb.data_hits 6136 # DTB hits -system.cpu.dtb.data_misses 169 # DTB misses +system.cpu.dtb.write_accesses 2161 # DTB write accesses +system.cpu.dtb.data_hits 6267 # DTB hits +system.cpu.dtb.data_misses 168 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6305 # DTB accesses -system.cpu.itb.fetch_hits 5063 # ITB hits -system.cpu.itb.fetch_misses 68 # ITB misses +system.cpu.dtb.data_accesses 6435 # DTB accesses +system.cpu.itb.fetch_hits 5272 # ITB hits +system.cpu.itb.fetch_misses 65 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5131 # ITB accesses +system.cpu.itb.fetch_accesses 5337 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -61,358 +61,358 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 29988 # number of cpu cycles simulated +system.cpu.numCycles 29638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6234 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3551 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1730 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4726 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits +system.cpu.BPredUnit.lookups 6610 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3711 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1792 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4939 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 751 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 185 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 34888 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6234 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1621 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5843 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1806 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5063 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24485 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.424872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.811431 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 944 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1602 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 36672 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6610 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6124 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5272 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 24286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.510006 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.874831 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18642 76.14% 76.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 463 1.89% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 348 1.42% 79.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 451 1.84% 81.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 433 1.77% 83.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 338 1.38% 84.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 497 2.03% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 532 2.17% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2781 11.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18162 74.78% 74.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 487 2.01% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 349 1.44% 78.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 481 1.98% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 433 1.78% 81.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 367 1.51% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 502 2.07% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 575 2.37% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2930 12.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24485 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.207883 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.163399 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35160 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5629 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5043 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2441 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 657 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 429 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 30497 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 762 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2441 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35832 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2821 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 862 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4769 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2029 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28347 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2069 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21319 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 35425 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35391 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 24286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223024 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.237330 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34845 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5279 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5199 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2549 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 678 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 456 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 31855 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 699 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2549 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35545 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2460 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4962 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2034 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 29496 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2078 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22198 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 36809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 36775 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12179 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 54 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5554 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2631 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1322 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13058 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 56 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5621 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2720 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2538 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1270 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2704 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1337 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21355 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6343 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24485 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.872167 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446196 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26000 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21936 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12217 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6791 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 24286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.903236 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.464516 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15521 63.39% 63.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3217 13.14% 76.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2370 9.68% 86.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1453 5.93% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1034 4.22% 96.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 556 2.27% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 237 0.97% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 75 0.31% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 22 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15163 62.44% 62.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3175 13.07% 75.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2422 9.97% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1558 6.42% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1052 4.33% 96.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 575 2.37% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 252 1.04% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.26% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 25 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24485 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 24286 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.18% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 104 58.43% 64.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 35.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 6.15% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 105 58.66% 64.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63 35.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7361 67.94% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2308 21.30% 89.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1160 10.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7498 68.11% 68.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2352 21.36% 89.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1154 10.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10834 # Type of FU issued +system.cpu.iq.FU_type_0::total 11009 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7172 68.17% 68.19% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 68.20% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 68.20% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2223 21.13% 89.35% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1121 10.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7399 67.71% 67.73% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.74% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2369 21.68% 89.44% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1154 10.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10521 # Type of FU issued +system.cpu.iq.FU_type_1::total 10927 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14533 68.05% 68.07% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 68.08% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4531 21.22% 89.32% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2281 10.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14897 67.91% 67.93% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.94% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4721 21.52% 89.48% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2308 10.52% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21355 # Type of FU issued -system.cpu.iq.rate 0.712118 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 95 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 83 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 178 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004449 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003887 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008335 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 67413 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 36435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19171 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 21936 # Type of FU issued +system.cpu.iq.rate 0.740131 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 179 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004103 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004057 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008160 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 68413 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 38274 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19529 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21507 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22089 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 457 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1537 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 471 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1355 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 405 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1521 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 472 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 573 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25387 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 653 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5169 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2592 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1220 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2104 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2055 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4159 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1354 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2549 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 597 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26207 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5424 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2673 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 269 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1293 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20406 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2135 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2153 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4288 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1530 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 84 # number of nop insts executed -system.cpu.iew.exec_nop::1 78 # number of nop insts executed -system.cpu.iew.exec_nop::total 162 # number of nop insts executed -system.cpu.iew.exec_refs::0 3212 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3127 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6339 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1650 # Number of branches executed -system.cpu.iew.exec_branches::1 1625 # Number of branches executed -system.cpu.iew.exec_branches::total 3275 # Number of branches executed -system.cpu.iew.exec_stores::0 1108 # Number of stores executed -system.cpu.iew.exec_stores::1 1072 # Number of stores executed -system.cpu.iew.exec_stores::total 2180 # Number of stores executed -system.cpu.iew.exec_rate 0.666967 # Inst execution rate -system.cpu.iew.wb_sent::0 9882 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9596 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19478 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9755 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9436 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19191 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5007 # num instructions producing a value -system.cpu.iew.wb_producers::1 4861 # num instructions producing a value -system.cpu.iew.wb_producers::total 9868 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6484 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6279 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12763 # num instructions consuming a value +system.cpu.iew.exec_nop::0 78 # number of nop insts executed +system.cpu.iew.exec_nop::1 77 # number of nop insts executed +system.cpu.iew.exec_nop::total 155 # number of nop insts executed +system.cpu.iew.exec_refs::0 3247 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3223 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6470 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1671 # Number of branches executed +system.cpu.iew.exec_branches::1 1692 # Number of branches executed +system.cpu.iew.exec_branches::total 3363 # Number of branches executed +system.cpu.iew.exec_stores::0 1112 # Number of stores executed +system.cpu.iew.exec_stores::1 1070 # Number of stores executed +system.cpu.iew.exec_stores::total 2182 # Number of stores executed +system.cpu.iew.exec_rate 0.688508 # Inst execution rate +system.cpu.iew.wb_sent::0 9974 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9875 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19849 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9831 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9718 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19549 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5093 # num instructions producing a value +system.cpu.iew.wb_producers::1 5062 # num instructions producing a value +system.cpu.iew.wb_producers::total 10155 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6638 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6585 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13223 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.325297 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.314659 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.639956 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.772209 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.774168 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.773172 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.331703 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.327890 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.659592 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.767249 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.768717 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.767980 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12568 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13400 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 24431 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.523065 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.302863 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 24235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.527295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312718 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18816 77.02% 77.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2827 11.57% 88.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1198 4.90% 93.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 508 2.08% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 350 1.43% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 244 1.00% 98.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 205 0.84% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 82 0.34% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 201 0.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18649 76.95% 76.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2814 11.61% 88.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1163 4.80% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 521 2.15% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 359 1.48% 96.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 238 0.98% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 198 0.82% 98.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 82 0.34% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 211 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 24431 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 24235 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -443,27 +443,27 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 201 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 117663 # The number of ROB reads -system.cpu.rob.rob_writes 53150 # The number of ROB writes -system.cpu.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5503 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 119797 # The number of ROB reads +system.cpu.rob.rob_writes 54926 # The number of ROB writes +system.cpu.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5352 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 4.706215 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.705476 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.352923 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.212485 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.212518 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.425003 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25299 # number of integer regfile reads -system.cpu.int_regfile_writes 14501 # number of integer regfile writes +system.cpu.cpi::0 4.651287 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.650557 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325461 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.214994 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.215028 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430022 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25729 # number of integer regfile reads +system.cpu.int_regfile_writes 14801 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -471,50 +471,50 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 314.927989 # Cycle average of tags in use -system.cpu.icache.total_refs 4192 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.707200 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 316.337538 # Cycle average of tags in use +system.cpu.icache.total_refs 4394 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.007974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 314.927989 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.153773 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.153773 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4192 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4192 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4192 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4192 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4192 # number of overall hits -system.cpu.icache.overall_hits::total 4192 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 871 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 871 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 871 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 871 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 871 # number of overall misses -system.cpu.icache.overall_misses::total 871 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34167000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34167000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34167000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34167000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34167000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34167000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.172032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.172032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.172032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.172032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.172032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.172032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39227.324914 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39227.324914 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39227.324914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39227.324914 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 316.337538 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.154462 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.154462 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4394 # number of overall hits +system.cpu.icache.overall_hits::total 4394 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 878 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 878 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 878 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 878 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 878 # number of overall misses +system.cpu.icache.overall_misses::total 878 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33797000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33797000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33797000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33797000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33797000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33797000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5272 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5272 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5272 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5272 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5272 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5272 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.166540 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.166540 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.166540 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.166540 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.166540 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.166540 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38493.166287 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38493.166287 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38493.166287 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38493.166287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38493.166287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38493.166287 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,96 +523,96 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24783500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24783500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.123445 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.123445 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.123445 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39653.600000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39653.600000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39653.600000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39653.600000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39653.600000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39653.600000 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24965000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24965000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24965000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24965000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24965000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24965000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118930 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.118930 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.118930 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39816.586922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39816.586922 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 215.917106 # Cycle average of tags in use -system.cpu.dcache.total_refs 4606 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.160000 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 217.393335 # Cycle average of tags in use +system.cpu.dcache.total_refs 4714 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.316384 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 215.917106 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.052714 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.052714 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3594 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3594 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 217.393335 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.053075 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.053075 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3702 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3702 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4606 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4606 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4606 # number of overall hits -system.cpu.dcache.overall_hits::total 4606 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4714 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4714 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4714 # number of overall hits +system.cpu.dcache.overall_hits::total 4714 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 344 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 344 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1042 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1042 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1042 # number of overall misses -system.cpu.dcache.overall_misses::total 1042 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14022500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28872500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28872500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42895000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42895000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42895000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42895000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3918 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1062 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1062 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1062 # number of overall misses +system.cpu.dcache.overall_misses::total 1062 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14235500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14235500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24441000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24441000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38676500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38676500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38676500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38676500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5648 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5648 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5648 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5648 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082695 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082695 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5776 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5776 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5776 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5776 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184490 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184490 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184490 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184490 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43279.320988 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43279.320988 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40212.395543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40212.395543 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41166.026871 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41166.026871 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.183864 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.183864 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.183864 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.183864 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41382.267442 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41382.267442 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34040.389972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34040.389972 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36418.549906 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36418.549906 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36418.549906 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36418.549906 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,173 +621,173 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # 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number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 707 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 209 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 209 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6369000 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6308500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6308500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16010500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16010500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051656 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051656 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43893.162393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 40581.108830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38715.088283 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43893.162393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 40581.108830 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38918.400000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45361.244019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 40532.973621 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42191.780822 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42191.780822 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 49000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3750 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4083.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 209 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22168000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8579500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30747500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5752000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5752000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22168000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14331500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 36499500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22168000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14331500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 36499500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 980 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22361500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8845500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5705500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5705500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22361500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 36912500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22361500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36912500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997608 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35582.664526 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41851.219512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37134.661836 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39397.260274 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39397.260274 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35778.400000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42322.966507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37418.465228 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39078.767123 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39078.767123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 2b7ec11ce..e278da8a8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25614500 # Number of ticks simulated -final_tick 25614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25317500 # Number of ticks simulated +final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72825 # Simulator instruction rate (inst/s) -host_op_rate 72819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123010334 # Simulator tick rate (ticks/s) -host_mem_usage 229416 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 47783 # Simulator instruction rate (inst/s) +host_op_rate 47781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79779918 # Simulator tick rate (ticks/s) +host_mem_usage 220364 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 744578266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344804700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1089382967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 744578266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 744578266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 744578266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344804700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1089382967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51230 # number of cpu cycles simulated +system.cpu.numCycles 50636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 5020 # Number of BP lookups @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 11058 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22262 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 524 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33874 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17356 # Number of cycles cpu stages are processed. -system.cpu.activity 33.878587 # Percentage of cycles cpu is active +system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17355 # Number of cycles cpu stages are processed. +system.cpu.activity 34.274034 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -75,36 +75,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.378842 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.378842 # CPI: Total CPI of All Threads -system.cpu.ipc 0.295959 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads +system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.295959 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38098 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37504 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 25.633418 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 42042 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.934804 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 42414 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.208667 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48346 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47752 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.629514 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41913 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9317 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.186609 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41318 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 164.536889 # Cycle average of tags in use +system.cpu.icache.tagsinuse 164.702089 # Cycle average of tags in use system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 164.536889 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080340 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080340 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 164.702089 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080421 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits @@ -117,12 +117,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20585000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20585000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20585000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20585000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20585000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20585000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20235000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20235000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20235000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20235000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20235000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses @@ -135,12 +135,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55785.907859 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55785.907859 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55785.907859 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55785.907859 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54837.398374 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54837.398374 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,34 +161,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16326500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16329000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16329000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54240.863787 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54240.863787 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.169435 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54249.169435 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 96.547387 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 96.602865 # Cycle average of tags in use system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 96.547387 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023571 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023571 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 96.602865 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023585 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023585 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits @@ -207,14 +207,14 @@ system.cpu.dcache.demand_misses::cpu.data 359 # n system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses system.cpu.dcache.overall_misses::total 359 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3488000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3488000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18458000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18458000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21946000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21946000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21946000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21946000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3411000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3411000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16758500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16758500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20169500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20169500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20169500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20169500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -233,20 +233,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61322.259136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61130.919220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61130.919220 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58810.344828 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58810.344828 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55676.079734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55676.079734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2258500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50188.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2987500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2987500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4730000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4730000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7717500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7717500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7717500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7717500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7727500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7727500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -281,26 +281,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55647.058824 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55682.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.042677 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.928542 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.114135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005952 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15989500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2926500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15989500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7561500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23551000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15989500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7561500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23551000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16005500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18945500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4645500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4645500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16005500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7585500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23591000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16005500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7585500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23591000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53476.588629 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53738.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53892.448513 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53892.448513 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53530.100334 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53822.443182 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54652.941176 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54652.941176 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53983.981693 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53983.981693 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12379500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14664500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5889000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18268500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5889000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18268500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12396000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14694500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3614500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12396000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18309000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12396000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18309000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -403,17 +403,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41403.010033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43113.207547 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41660.511364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42400 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41745.738636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42523.529412 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42523.529412 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index c96167523..5ed8e97b3 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,267 +1,267 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20275500 # Number of ticks simulated -final_tick 20275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19879000 # Number of ticks simulated +final_tick 19879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60587 # Simulator instruction rate (inst/s) -host_op_rate 60583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85082969 # Simulator tick rate (ticks/s) -host_mem_usage 230436 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 39676 # Simulator instruction rate (inst/s) +host_op_rate 39674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54630622 # Simulator tick rate (ticks/s) +host_mem_usage 221392 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1063746887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 460851767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524598654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1063746887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1063746887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1063746887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 460851767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524598654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1078525077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 470043765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1548568841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1078525077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1078525077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1078525077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 470043765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1548568841 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 40552 # number of cpu cycles simulated +system.cpu.numCycles 39759 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6886 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4580 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1118 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5120 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2601 # Number of BTB hits +system.cpu.BPredUnit.lookups 6854 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4554 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1112 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4710 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2490 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 458 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 477 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12252 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32221 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6886 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3059 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9555 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3174 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7365 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12088 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31936 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6854 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2967 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9404 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3148 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7222 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 767 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5498 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 31903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.009968 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.184021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 741 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5545 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 31399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.017102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.199996 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22348 70.05% 70.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4753 14.90% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 493 1.55% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 436 1.37% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 686 2.15% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 773 2.42% 92.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 236 0.74% 93.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 275 0.86% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1903 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21995 70.05% 70.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4682 14.91% 84.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 472 1.50% 86.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 410 1.31% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 687 2.19% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 719 2.29% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.75% 93.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 265 0.84% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1934 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 31903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.169807 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.794560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12897 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8133 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8716 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1960 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30041 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1960 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13576 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 285 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7298 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8274 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 510 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27346 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 31399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.172389 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.803240 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12738 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7939 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8587 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 195 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1940 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29749 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1940 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13426 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7130 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8156 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 488 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27133 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 172 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24383 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50854 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50854 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 140 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24210 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50486 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50486 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10564 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 704 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2903 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2471 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10391 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 723 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2887 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3597 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2432 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23123 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 669 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21711 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8357 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 31903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.680532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.296567 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 22935 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 673 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 91 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5610 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 198 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 31399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.687824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.304127 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22407 70.23% 70.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3681 11.54% 81.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2373 7.44% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 903 2.83% 97.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 494 1.55% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 242 0.76% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22002 70.07% 70.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3599 11.46% 81.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2373 7.56% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1680 5.35% 94.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 925 2.95% 97.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 497 1.58% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 251 0.80% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 31903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31399 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45 26.16% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 13.95% 40.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103 59.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 47 27.33% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27 15.70% 43.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 98 56.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16013 73.76% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2266 10.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15947 73.84% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3395 15.72% 89.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2255 10.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21711 # Type of FU issued -system.cpu.iq.rate 0.535387 # Inst issue rate +system.cpu.iq.FU_type_0::total 21597 # Type of FU issued +system.cpu.iq.rate 0.543198 # Inst issue rate system.cpu.iq.fu_busy_cnt 172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007922 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75603 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32175 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19936 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.007964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74856 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31925 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19878 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21883 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21769 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1413 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1372 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1023 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 984 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1960 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 99 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24957 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 410 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2471 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1940 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24765 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 456 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3597 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2432 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 673 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 290 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 979 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1247 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20532 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20456 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3252 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1141 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1165 # number of nop insts executed -system.cpu.iew.exec_refs 5418 # number of memory reference insts executed -system.cpu.iew.exec_branches 4292 # Number of branches executed -system.cpu.iew.exec_stores 2146 # Number of stores executed -system.cpu.iew.exec_rate 0.506313 # Inst execution rate -system.cpu.iew.wb_sent 20199 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19936 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9239 # num instructions producing a value -system.cpu.iew.wb_consumers 11338 # num instructions consuming a value +system.cpu.iew.exec_nop 1157 # number of nop insts executed +system.cpu.iew.exec_refs 5386 # number of memory reference insts executed +system.cpu.iew.exec_branches 4298 # Number of branches executed +system.cpu.iew.exec_stores 2134 # Number of stores executed +system.cpu.iew.exec_rate 0.514500 # Inst execution rate +system.cpu.iew.wb_sent 20129 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19878 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9203 # num instructions producing a value +system.cpu.iew.wb_consumers 11321 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.491616 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.814870 # average fanout of values written-back +system.cpu.iew.wb_rate 0.499962 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.812914 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9713 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9531 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1118 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.506075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.188090 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1112 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.202047 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22536 75.22% 75.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4135 13.80% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1423 4.75% 93.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 788 2.63% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 331 1.10% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 258 0.86% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 318 1.06% 99.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.24% 99.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22110 75.01% 75.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4076 13.83% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1418 4.81% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 772 2.62% 96.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 337 1.14% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 264 0.90% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 327 1.11% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.24% 99.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 100 0.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29476 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -272,68 +272,68 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 100 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 53914 # The number of ROB reads -system.cpu.rob.rob_writes 51717 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 53246 # The number of ROB reads +system.cpu.rob.rob_writes 51332 # The number of ROB writes +system.cpu.timesIdled 190 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8360 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 2.809088 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.809088 # CPI: Total CPI of All Threads -system.cpu.ipc 0.355987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.355987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32709 # number of integer regfile reads -system.cpu.int_regfile_writes 18169 # number of integer regfile writes -system.cpu.misc_regfile_reads 7069 # number of misc regfile reads +system.cpu.cpi 2.754156 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.754156 # CPI: Total CPI of All Threads +system.cpu.ipc 0.363088 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.363088 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32578 # number of integer regfile reads +system.cpu.int_regfile_writes 18091 # number of integer regfile writes +system.cpu.misc_regfile_reads 7032 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 199.209373 # Cycle average of tags in use -system.cpu.icache.total_refs 5019 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.805310 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 199.192019 # Cycle average of tags in use +system.cpu.icache.total_refs 5061 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15.017804 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 199.209373 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.097270 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.097270 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5019 # number of overall hits -system.cpu.icache.overall_hits::total 5019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16863000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16863000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16863000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16863000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16863000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16863000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5498 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5498 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5498 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5498 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087123 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.087123 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.087123 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.087123 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.087123 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.087123 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35204.592902 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35204.592902 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35204.592902 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35204.592902 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 199.192019 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.097262 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.097262 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5061 # number of overall hits +system.cpu.icache.overall_hits::total 5061 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 484 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 484 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 484 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 484 # number of overall misses +system.cpu.icache.overall_misses::total 484 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16465500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16465500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16465500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16465500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16465500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16465500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5545 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087286 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.087286 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.087286 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.087286 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.087286 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.087286 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34019.628099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34019.628099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34019.628099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34019.628099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,56 +342,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 140 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 140 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 140 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 140 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 140 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 140 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12213000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12213000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061659 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.061659 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.061659 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12143500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12143500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12143500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060775 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.060775 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.060775 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36034.124629 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36034.124629 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.759786 # Cycle average of tags in use -system.cpu.dcache.total_refs 4074 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.051665 # Cycle average of tags in use +system.cpu.dcache.total_refs 4061 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.904110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.815068 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.759786 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025088 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025088 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3035 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.051665 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025159 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025159 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3022 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3022 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4068 # number of overall hits -system.cpu.dcache.overall_hits::total 4068 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 4055 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4055 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4055 # number of overall hits +system.cpu.dcache.overall_hits::total 4055 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses @@ -400,40 +400,40 @@ system.cpu.dcache.demand_misses::cpu.data 530 # n system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses system.cpu.dcache.overall_misses::total 530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4649500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17651000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17651000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22300500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22300500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22300500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22300500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4244000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4244000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15546000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15546000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19790000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19790000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19790000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19790000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3143 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4598 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4598 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4598 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4598 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038340 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.038340 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4585 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4585 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4585 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4585 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038498 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038498 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115268 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115268 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43156.479218 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42076.415094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42076.415094 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.115594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35074.380165 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35074.380165 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38009.779951 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38009.779951 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37339.622642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37339.622642 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,103 +458,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5811000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5811000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5823000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5823000 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39674.698795 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031843 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031843 # 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average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995859 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35237.313433 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38690.476190 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35783.919598 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39012.048193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39012.048193 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36340.956341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38873.287671 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10738000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5225500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15963500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995859 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32031.157270 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35531.746032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32582.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35391.566265 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35391.566265 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32053.731343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35619.047619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32618.090452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35921.686747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35921.686747 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 4464561a4..af9b5d77e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 43106000 # Number of ticks simulated -final_tick 43106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000041 # Number of seconds simulated +sim_ticks 41368000 # Number of ticks simulated +final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377775 # Simulator instruction rate (inst/s) -host_op_rate 377609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1073121241 # Simulator tick rate (ticks/s) -host_mem_usage 229408 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 652409 # Simulator instruction rate (inst/s) +host_op_rate 651936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1777530278 # Simulator tick rate (ticks/s) +host_mem_usage 220352 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 412749965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 204890270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 617640236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 412749965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 412749965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 412749965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 204890270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 617640236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 86212 # number of cpu cycles simulated +system.cpu.numCycles 82736 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 86212 # Number of busy cycles +system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 152.957781 # Cycle average of tags in use +system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.957781 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074686 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074686 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.669722 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.669722 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023845 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023845 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2968000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2968000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4760000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4760000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 183.688794 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.283537 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.405257 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000958 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005606 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits |